Patents Issued in April 14, 2022
  • Publication number: 20220115386
    Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate and first gate structures and source/drain doped layers on the substrate. Each of the source/drain doped layers is located at two sides of one first gate structure. The semiconductor device further includes a dielectric layer on the substrate. The dielectric layer contains first grooves, exposing the source/drain doped layers, wherein each first groove includes a first-groove bottom part and a first-groove top part located above the first-groove bottom part, and a size of the first-groove top part is larger than a size of the first-groove bottom part. The semiconductor device further includes a first conductive structure located in the first-groove bottom part, an insulating layer located in the first-groove top part and on the first conductive structure, and a second conductive structure located in the dielectric layer and connected to the first gate structure.
    Type: Application
    Filed: December 16, 2021
    Publication date: April 14, 2022
    Inventor: Fei ZHOU
  • Publication number: 20220115387
    Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Inventors: Chih-Chuan Yang, Chia-Hao PAO, Wen-Chun Keng, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20220115388
    Abstract: Transistors (N1 to N12) corresponding to drive transistors (PD1, PD2), access transistors (PG1, PG2), read drive transistor (RPD1), and read access transistor (RPG1) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. The transistors (P1, P2) overlap the transistors (N3, N8), respectively, in plan view.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventor: Masanobu HIROSE
  • Publication number: 20220115389
    Abstract: Transistors (N3, N4) corresponding to a drive transistor (PD1), transistors (N5, N6) corresponding to a drive transistor (PD2), transistors (N7, N8) corresponding to an access transistor (PG1), and transistors (N1, N2) corresponding to an access transistor (PG2) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. Further, the transistors (P1, P2) overlap the transistors (N3, N6) in plan view.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventor: Masanobu Hirose
  • Publication number: 20220115390
    Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same. The device includes a substrate including a cell array region and an extension region, stack structures extending in a first direction and including gate electrodes stacked on the substrate, vertical structures penetrating the stack structures on the cell array region, a mold structure on a portion of the extension region, a first support structure extending in the first direction between the stack structures, second support structures penetrating the stack structures on the extension region and spaced apart in a second direction from the first support structure, and a third support structure surrounding the mold structure in a plan view. Respective top surfaces of ones of the second support structures and a top surface of the third support structure is higher than a top surface of ones of the vertical structures.
    Type: Application
    Filed: July 16, 2021
    Publication date: April 14, 2022
    Inventors: Sehoon Lee, Byoungil Lee
  • Publication number: 20220115391
    Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei-Cheng Wu, Li-Feng Teng, Chien-Hung Chang
  • Publication number: 20220115392
    Abstract: A three-dimensional memory includes a stack structure, a dummy structure and a gate line slit. The stack structure includes gate line layers and isolation layers stacked alternatively in the vertical direction. The dummy structure includes a first dummy section and a second dummy section. The gate line slit has one end extending into a gap formed by at least one of the first dummy section or the second dummy section. At least one of the first dummy section and the second dummy section partially overlaps a projection of the gate line slit onto the horizontal plane to realize connection between the dummy structure and the gate line slit.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Zhong Zhang, Yuhui Han, Cuicui Kong, Kun Zhang
  • Publication number: 20220115393
    Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.
    Type: Application
    Filed: June 11, 2021
    Publication date: April 14, 2022
    Inventors: Changyeon Yu, Pansuk Kwak
  • Publication number: 20220115394
    Abstract: A semiconductor memory device includes a mold structure including gate electrodes stacked on a first substrate, a channel structure that penetrates a first region of the mold structure to cross the gate electrodes, a first through structure that penetrates a second region of the mold structure, and a second through structure that penetrates a third region of the mold structure. The mold structure further includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell blocks and the dummy block includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.
    Type: Application
    Filed: May 6, 2021
    Publication date: April 14, 2022
    Inventors: MYUNG HUN LEE, DONG HA SHIN, PAN SUK KWAK, DAE SEOK BYEON
  • Publication number: 20220115395
    Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: QIANG XU, Zhiliang Xia, Ping Yan, Guangji Li, Zongliang Huo
  • Publication number: 20220115396
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, pillar structures vertically extending through the alternating stack, bump stack structures including a base bump portion located underneath the alternating stack and a respective subset of the bump portions located in the alternating stack that overlie the base bump portion, and protrusion structures located over the alternating stack and laterally spaced from the bump stack structures. Each of the insulating layers and the electrically conductive layers include a planar portion located between a planar top surface and a planar bottom surface and the bump portions that are adjoined to the planar portion at a respective periphery and having a respective raised top surface that is vertically raised from the planar top surface and a respective raised bottom surface that is raised from the planar bottom surface.
    Type: Application
    Filed: October 13, 2020
    Publication date: April 14, 2022
    Inventor: Yosuke TAKAHATA
  • Publication number: 20220115397
    Abstract: A semiconductor device including a substrate; a horizontal conductive layer disposed on the substrate; a support layer disposed on the horizontal conductive layer; a stack structure including a plurality of gate electrodes, stacked to be spaced apart from each other in a direction perpendicular to an upper surface of the support layer, and a plurality of interlayer insulating layers stacked alternately with the plurality of gate electrodes; a channel structure penetrating through the stack structure; a separation structure penetrating through the horizontal conductive layer, the support layer, and the stack structure and extending in a first direction; and a conductive pattern disposed on a level between the horizontal conductive layer and a lowermost interlayer insulating layer, among the plurality of interlayer insulating layers, and protruding outwardly of the separation structure from a side surface of the separation structure.
    Type: Application
    Filed: July 16, 2021
    Publication date: April 14, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Wonseok CHO, Seulbi LEE
  • Publication number: 20220115398
    Abstract: A 3-dimensional (3D) flash memory having a structure that mitigates an interference phenomenon between neighboring cells in an oxide-nitride-oxide (ONO) layer, which is a charge storage layer, and a method of manufacturing the same are provided.
    Type: Application
    Filed: January 23, 2020
    Publication date: April 14, 2022
    Inventor: Yun Heub SONG
  • Publication number: 20220115399
    Abstract: In certain embodiments, a method of fabricating a device includes forming, on a substrate, a layer stack of alternating layers of a first spin-on material and a second spin-on material. Each layer of the first spin-on material and the second spin-on material is formed by spin-on deposition. The method includes etching first openings through the layer stack and filling the first openings with a third material. The method includes etching second openings through the layer stack, removing the first spin-on material from the layer stack, and replacing the first spin-on material with a fourth material. The fourth material is a first metal-containing material.
    Type: Application
    Filed: September 10, 2021
    Publication date: April 14, 2022
    Inventors: Soo Doo Chae, Karthikeyan Pillai, Lior Huli, Na Young Bae, Hojin Kim
  • Publication number: 20220115400
    Abstract: A NAND flash memory and manufacturing method thereof are provided. The NAND flash memory is capable of preventing a short circuit between gates extending along a vertical direction. The NAND flash memory includes a substrate; a plurality of channel stacks formed on the substrate and extending along an X direction; an interlayer dielectric formed between the channel stacks; a plurality of trenches formed apart from each other in the interlayer dielectric and arranged along a Y direction; an insulator stack including a charge storage layer formed to cover sidewalls of each of the trenches; and a plurality of conductive vertical gates elongating along the vertical direction in a space formed by the insulator stack in each of the trenches and extending along the Y direction.
    Type: Application
    Filed: September 30, 2021
    Publication date: April 14, 2022
    Applicant: Winbond Electronics Corp.
    Inventor: Riichiro Shirota
  • Publication number: 20220115401
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
  • Publication number: 20220115402
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure including a memory block including a plurality of memory cells. The 3D memory device also includes a first top select structure and a bottom select structure in the memory block and aligned with each other vertically; and a second top select structure in the memory block is separated from the first top select structure by at least one of the plurality of memory cells. The first top select structure, the bottom select structure, and the second top select structure each includes an insulating material.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Zongliang Huo, Haohao Yang, Wei Xu, Ping Yan, Pan Huang, Wenbin Zhou
  • Publication number: 20220115403
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki MARUYAMA, Yoshiaki FUKUZUMI, Yuki SUGIURA, Shinya ARAI, Fumie KIKUSHIMA, Keisuke SUDA, Takashi ISHIDA
  • Publication number: 20220115404
    Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Applicant: SK hynix Inc.
    Inventors: Kun Young LEE, Sun Young KIM, Jae Gil LEE
  • Publication number: 20220115405
    Abstract: A MOS IC includes first and second sets of adjacent transistor logic, each of which include collinear gate interconnects extending in a first direction with the same gate pitch. The first set of transistor logic has a first cell height h1 and a first number of Mx layer tracks that extend unidirectionally in a second direction orthogonal to the first direction. The second set of transistor logic has a second cell height h2 and a second number of Mx layer tracks that extend unidirectionally in the second direction, where h2>h1 and the second number of Mx layer tracks is greater than the first number of Mx layer tracks. At least one of a height ratio hR=h2/h1 is a non-integer value or a subset of the first set of transistor logic and a subset of the second set of transistor logic are within one logic cell.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 14, 2022
    Inventors: Hyeokjin LIM, Venugopal BOYNAPALLI, Foua VANG, Seung Hyuk KANG
  • Publication number: 20220115406
    Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.
    Type: Application
    Filed: December 24, 2021
    Publication date: April 14, 2022
    Inventors: Hyeon Gyu YOU, In Gyum KIM, Gi Young YANG, Ji Su YU, Jin Young LIM, Hak Chul JUNG
  • Publication number: 20220115407
    Abstract: An array substrate and a display panel are provided. The array substrate includes one or more sub-pixels, and one or more connecting members corresponding to the first sub-pixels. A layer where the connecting members are located is insulated from the source/drain layer. Data lines connected to the first sub-pixels include first sub-data lines adjacent to the first sub-pixels. Both ends of each of the connecting members are connected to a corresponding first sub-data line through via holes. This improves a charging rate of sub-pixels.
    Type: Application
    Filed: May 21, 2020
    Publication date: April 14, 2022
    Applicant: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Munan Lin, Bangyin Peng, Ilgon Kim
  • Publication number: 20220115408
    Abstract: A display device includes a first region and a second region each including a plurality of pixels, and a plurality of wires connected to the plurality of pixels, respectively, to transmit a signal, where the number of pixels per unit area in the second region is less than the number of pixels per unit area in the first region, and the number of wires per unit area in the second region is less than the number of wires per unit area in the first region.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 14, 2022
    Inventors: Dong-Hwi KIM, Jin JEON
  • Publication number: 20220115409
    Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Inventors: Motomu KURATA, Shinya SASAGAWA, Ryota HODO, Katsuaki TOCHIBAYASHI, Tomoaki MORIWAKA, Jiro NISHIDA, Hidekazu MIYAIRI, Shunpei YAMAZAKI
  • Publication number: 20220115410
    Abstract: A display panel and a manufacturing method are provided. The display panel includes a substrate, a source/drain layer, a light shielding layer, a dielectric layer disposed on the substrate and covering the light shielding layer and the source/drain layer, and an oxide semiconductor layer disposed on the dielectric layer. The oxide semiconductor layer is connected to the source/drain layer and the light shielding layer through a first hole and a second hole, respectively. A metal layer is etched to form the source/drain layer and the light shielding layer simultaneously. The dielectric layer arranged on the substrate covers the light shielding layer and the source/drain layer. The dielectric layer functions as an isolating layer, which reduces the number of oxide TFT layers of the display panel, simplifying the film structure of the display panel, reducing the processes and masks required for production, thereby increasing production efficiency and reducing production costs.
    Type: Application
    Filed: May 29, 2019
    Publication date: April 14, 2022
    Inventor: Macai Lu
  • Publication number: 20220115411
    Abstract: The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20220115412
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20220115413
    Abstract: A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.
    Type: Application
    Filed: March 27, 2020
    Publication date: April 14, 2022
    Inventors: Chao LUO, Feng GUAN, Zhi WANG, Jianhua DU, Yang LV, Zhaohui QIANG, Chao LI
  • Publication number: 20220115414
    Abstract: The present application provides an array substrate and a display device. The array substrate includes a first conductive layer, a second conductive layer, and an insulating layer. The first conductive layer includes at least two first conductive members disposed side by side in the bonding area. The second conductive layer includes at least two second conductive members; each of the second conductive members is provided corresponding to and electrically connected to each of the first conductive members, and at least two of the second conductive members and at least two of the first conductive members are electrically connected through a same via-hole on the insulating layer.
    Type: Application
    Filed: April 21, 2020
    Publication date: April 14, 2022
    Applicant: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Xiaojin HE, Chengcai DONG, Ilgon KIM
  • Publication number: 20220115415
    Abstract: A method of manufacturing a display panel and a display panel are provided. A groove is formed on a buffer layer through performing exposure and etching processes, so as to divide the buffer layer into independent units. A gate insulating layer, a dielectric layer, and a passivation layer are converted from continuous layers to independent layers on the buffer layer. Therefore, heterogeneous interface stress accumulated in the independent unit is reduced, it prevents the deformation of the glass substrate, protects the glass substrate, reduces fragmentation phenomenon, and improves process reliability and yield.
    Type: Application
    Filed: April 10, 2020
    Publication date: April 14, 2022
    Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaohui NIE
  • Publication number: 20220115416
    Abstract: The present disclosure discloses an array substrate, a display panel and a display device. The array substrate includes a base substrate and a capacitor, the capacitor includes a first electrode, a dielectric portion and a second electrode sequentially located on the base substrate; wherein the dielectric portion includes: a first plane facing the second electrode, and a first slope surface extending from the first plane to the base substrate; and an orthographic projection, on the base substrate, of the second electrode is located in a region where an orthographic projection, on the base substrate, of the first plane of the dielectric portion is located.
    Type: Application
    Filed: September 28, 2020
    Publication date: April 14, 2022
    Inventors: Da ZHOU, Taoran ZHANG, Zailong MO, Linxuan LI, Wenjin HUANG
  • Publication number: 20220115417
    Abstract: A glossy display panel, a manufacturing method thereof and a display device are provided. The glossy display panel includes a display area and a non-display area; wherein the non-display area includes a binding area, and the glossy display panel includes a first conductive pattern located on a base substrate and located in the binding area; a first insulating layer covering the first conductive pattern, wherein the first insulating layer is provided with a first via hole, and an orthographic projection of the first via hole onto the base substrate is located within an orthographic projection of the first conductive pattern onto the base substrate; a glossy reflection layer, wherein an orthographic projection of the glossy reflection layer onto the base substrate does not overlap with an orthographic projection of the binding area onto the base substrate; and a chip on film.
    Type: Application
    Filed: April 30, 2020
    Publication date: April 14, 2022
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xueyan TIAN, Jianchao ZHU, Libin LIU, Liangjian LI, Caiyu QU, Dengyun CHEN, Ximeng LI
  • Publication number: 20220115418
    Abstract: A photo sensor element, including a substrate, a first electrode, a second electrode, and a photosensitive layer, is provided. The first electrode is located on the substrate and has multiple first openings. The second electrode overlaps the first electrode and the first openings. The photosensitive layer is sandwiched between the first electrode and the second electrode, and overlaps the first electrode and the second electrode.
    Type: Application
    Filed: April 19, 2021
    Publication date: April 14, 2022
    Applicant: Au Optronics Corporation
    Inventors: Cheng-Hsing Lin, Shu-Wen Tzeng
  • Publication number: 20220115419
    Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
    Type: Application
    Filed: October 11, 2021
    Publication date: April 14, 2022
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Francois GUYADER, Sara PELLEGRINI, Bruce RAE
  • Publication number: 20220115420
    Abstract: A hyperspectral element includes (1) a multi filter including: a first sub filter through which first wavelength light having a first wavelength passes; and a second sub filter through which second wavelength light having a second wavelength passes, the second wavelength being different from the first wavelength; and (2) a multi detector configured to detect the first wavelength light and the second wavelength light, wherein the first sub filter and the second sub filter may be arranged in series in an optical path of incident light which is incident onto the multi filter.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 14, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Youngzoon YOON
  • Publication number: 20220115421
    Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Inventors: Tsung-Wei HUANG, Chao-Ching CHANG, Yun-Wei CHENG, Chih-Lung CHENG, Yen-Chang CHEN, Wen-Jen TSAI, Cheng Han LIN, Yu-Hsun CHIH, Sheng-Chan LI, Sheng-Chau CHEN
  • Publication number: 20220115422
    Abstract: Disclosed is an image sensor including a substrate that includes a plurality of pixel sections and having a first surface and a second surface opposite to each other, an antireflective layer disposed on the second surface of the substrate, a passivation layer disposed on the antireflective layer, a plurality of color filters disposed on the passivation layer and corresponding pixel sections, a plurality of micro-lenses disposed on the color filters, and a gap region that separates the micro-lenses from each other. The gap region extends between the color filters and separates the color filters from each other. The gap region exposes a portion of a top surface of the passivation layer. A thickness of the passivation layer is less than a thickness of the antireflective layer.
    Type: Application
    Filed: July 6, 2021
    Publication date: April 14, 2022
    Inventors: MINKWAN KIM, IN SUNG JOE, Jinhyung KIM, Dhami PARK, INYONG PARK, Kisang YOON
  • Publication number: 20220115423
    Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 14, 2022
    Applicant: Raytheon Company
    Inventors: Eric Miller, Christian M. Boemler, Justin Gordon Adams Wehner, Drew Fairbanks, Sean P. Kilcoyne
  • Publication number: 20220115424
    Abstract: According to an aspect, a detection device includes: a substrate; a plurality of photodiodes arranged on the substrate; an insulating film that covers the photodiodes; and a conductive layer provided on the insulating film. Each photodiode includes a plurality of first regions, in each of which a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer are stacked such that the p-type semiconductor layer is directly in contact with the i-type semiconductor layer and the i-type semiconductor layer is directly in contact with the n-type semiconductor layer. The i-type semiconductor layers in the first regions are separated from one another in a plan view. The n-type semiconductor layers in the first regions are separated from one another in the plan view. The conductive layer is coupled to each of the n-type semiconductor layers in the first regions through a contact hole provided in the insulating film.
    Type: Application
    Filed: October 6, 2021
    Publication date: April 14, 2022
    Inventors: Tadayoshi KATSUTA, Yoshitaka OZEKI
  • Publication number: 20220115425
    Abstract: An optical package structure and a method for manufacturing an optical package structure are provided. The optical package structure includes a sensor, an optical component and a fixing element. The optical component directly contacts the sensor. An interfacial area is defined by a contacting region of the optical component and the sensor. The fixing element is disposed outside of the interfacial area for bonding the optical component and the sensor.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 14, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Ling HUANG, Lu-Ming LAI, Ying-Chung CHEN
  • Publication number: 20220115426
    Abstract: Provided are an image sensor package with improved reliability and a method of fabricating the same. The image sensor package includes a package substrate, an image sensor chip mounted on the package substrate, a transparent cover on the image sensor chip, an encapsulant encapsulating the image sensor chip and covering a side surface of the transparent cover, a dam on a surface of the image sensor chip and surrounding a portion of the upper surface of the image sensor, the transparent cover on the dam, a bonding wire connecting a chip pad of the image sensor chip to a substrate pad of the package substrate, the dam covering a first end of the bonding wire connected to the chip pad, and a stress reducing layer covering a second end of the bonding wire connected to the substrate pad, the stress reducing layer including substantially the same material as the dam.
    Type: Application
    Filed: April 26, 2021
    Publication date: April 14, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Bongjin SON
  • Publication number: 20220115427
    Abstract: Picture quality deterioration is curbed. A solid-state imaging device according to an embodiment includes: a semiconductor substrate (131) including a light-receiving element; an on-chip lens (132) disposed on a first surface of the semiconductor substrate; a resin layer (133) covering the on-chip lens; and a glass substrate (134) disposed on the side of the first surface of the semiconductor substrate separately from the resin layer.
    Type: Application
    Filed: February 21, 2020
    Publication date: April 14, 2022
    Inventors: YUTAKA OOKA, TAIZO TAKACHI, YUICHI YAMAMOTO
  • Publication number: 20220115428
    Abstract: An imaging device includes a plurality of optical sensors on an integrated circuit and a plurality of sets of interference filters, where a set of interference filters of the plurality of sets of interference filters includes a plurality of interference filters that are arranged in a pattern with each interference filter of a set of filters being configured to pass light in a different wavelength range. A plurality of sets of absorption filters is included, with a set of absorption filters of the plurality of sets of absorption filters including a plurality of absorption filters arranged in a pattern and each absorption filter is associated with one or more interference filters to create an absorption filter and interference filter pair. Each absorption filter and interference filter pair is associated with one or more optical sensors and is configured to pass light in a narrower wavelength range than the absorption filter alone.
    Type: Application
    Filed: September 13, 2021
    Publication date: April 14, 2022
    Applicant: Spectricity
    Inventor: Jonathan Borremans
  • Publication number: 20220115429
    Abstract: Photoelectric conversion apparatus includes semiconductor layer in which first photoelectric converters are arranged in light-receiving region and second photoelectric converters are arranged in light-shielded region, light-shielding wall arranged above the semiconductor layer and defining apertures respectively corresponding to the first photoelectric converters, and light-shielding film arranged above the semiconductor layer. The light-shielding film includes first portion extending along principal surface of the semiconductor layer to cover the second photoelectric converters. The first portion has lower surface and upper surface. The light-shielding wall includes second portion whose distance from the semiconductor layer is larger than distance between the upper surface and the principal surface. Thickness of the first portion in direction perpendicular to the principal surface is larger than thickness of the second portion in direction parallel to the principal surface.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Toshiyuki Ogawa, Sho Suzuki, Takehito Okabe, Mitsuhiro Yomori, Yukinobu Suzuki, Akihiro Kawano, Tsutomu Tange
  • Publication number: 20220115430
    Abstract: A photoelectric conversion apparatus includes a semiconductor substrate, a floating diffusion, an amplifying transistor, first and second contact plugs, a wire, and a metal portion. The semiconductor substrate has a first plane and a second plane to be entered by light, and includes a photoelectric conversion element. The amplifying transistor includes a first gate electrode. The first contact plug is connected to the floating diffusion. The second contact plug is connected to the first gate electrode. The wire is configured to electrically connect the first gate electrode and the floating diffusion to each other. The metal portion, which is arranged between the first plane and a third plane, covers at least a part of the photoelectric conversion element in a planar view, and has an opening over which at least a part of the wire is superimposed in a planar view.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Yusuke Onuki, Fumihiro Inui
  • Publication number: 20220115431
    Abstract: A method for forming a pixel includes forming, in a semiconductor substrate, a wide trench having an upper depth with respect to a planar top surface of the semiconductor substrate. The method also includes ion-implanting a floating-diffusion region between the planar top surface and a junction depth in the semiconductor substrate. In a cross-sectional plane perpendicular to the planar top surface, the floating-diffusion region has (i) an upper width between the planar top surface and the upper depth, and (ii) between the upper depth and the junction depth, a lower width that exceeds the upper width. Part of the floating-diffusion region is beneath the wide trench and between the upper depth and the junction depth.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Hui ZANG, Gang CHEN
  • Publication number: 20220115432
    Abstract: Example embodiments relate to an image sensor configured to achieve a high photoelectric conversion efficiency and a low dark current. The image sensor includes first and second electrodes, a plurality of photodetection layers provided between the first and second electrodes, and an interlayer provided between the photodetection layers. The photodetection layers convert incident light into an electrical signal and include a semiconductor material. The interlayer includes a metallic or semi metallic material having anisotropy in electrical conductivity.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sanghyun JO, Jaeho LEE, Eunkyu LEE, Seongjun PARK, Kiyoung LEE, Jinseong HEO
  • Publication number: 20220115433
    Abstract: A display device includes a substrate, a photosensitive element formed above the substrate, a signal line formed above the substrate, and a transparent conductive member electrically connected to the signal line and the photosensitive element. In a normal direction of the substrate, the signal line does not overlap with the photosensitive element.
    Type: Application
    Filed: September 8, 2021
    Publication date: April 14, 2022
    Applicant: InnoLux Corporation
    Inventors: Hsiao-Feng LIAO, Shu-Fen LI, Chuan-Chi CHIEN, I-An YAO
  • Publication number: 20220115434
    Abstract: A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventor: Seong Yeol Mun
  • Publication number: 20220115435
    Abstract: To improve color reproduction areas in a display device having light-emitting elements. A display region has a plurality of picture elements. Each picture element includes: first and second pixels each including a light-emitting element which has a chromaticity whose x-coordinate in a CIE-XY chromaticity diagram is 0.50 or more; third and fourth pixels each including a light-emitting element which has a chromaticity whose y-coordinate in the diagram is 0.55 or more; and fifth and sixth pixels each including a light-emitting element which has a chromaticity whose x-coordinate and y-coordinate in the diagram are 0.20 or less and 0.25 or less, respectively. The light-emitting elements in the first and second pixels have different emission spectrums from each other; the light-emitting elements in the third and fourth pixels have different emission spectrums from each other; and the light-emitting elements in the fifth and sixth pixels have different emission spectrums from each other.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi Miyaguchi