Patents Issued in April 14, 2022
  • Publication number: 20220115336
    Abstract: A semiconductor device that includes a semiconductor substrate having a first main face and a second main face opposite each other; a dielectric film on a part of the first main face, the dielectric film having an electrode layer disposing portion and a protective layer covering portion, and a thickness of the protective layer covering portion in an outer peripheral end of the dielectric film is smaller than a thickness of the electrode layer disposing portion of the dielectric film; a first electrode layer on the electrode layer disposing portion of the dielectric film; and a protective layer continuously covering a range from an end portion of the first electrode layer to the outer peripheral end of the dielectric film.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Yohei Yamaguchi, Tomoyuki Ashimine
  • Publication number: 20220115337
    Abstract: A semiconductor device includes a semiconductor substrate, a conductive segment, a conductive layer, a first contact element and a second contact element. The semiconductor substrate includes an active region. The conductive segment is formed on the semiconductor substrate, and extends across the active region. The conductive layer is formed over the semiconductor substrate and the conductive segment. The first contact element, formed between the conductive segment and a first conductive portion of the conductive layer, is arranged to electrically connect the conductive segment to the first conductive portion. The second contact element is formed between the conductive segment and a second conductive portion of the conductive layer. The first contact element and the second contact element are formed on the conductive segment and spaced apart from each other. The second contact element is arranged to electrically isolate the conductive segment from the second conductive portion.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventor: SHIH-LIEN LINUS LU
  • Publication number: 20220115338
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first conductive component, a second conductive component, a planarization layer and an antenna layer. The second conductive component is disposed adjacent to the first conductive component. The second conductive component and the first conductive component have different thicknesses. The planarization layer is disposed on the first conductive component. The antenna layer is disposed on the first conductive component and the second conductive component.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 14, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20220115339
    Abstract: An antenna package includes a conductive layer, an interconnection structure and an antenna. The interconnection structure is disposed on the conductive layer. The interconnection structure includes a conductive via and a first package body. The conductive via has a first surface facing the conductive layer, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The first package body covers the lateral surface of the conductive via and exposes the first surface and the second surface of the conductive via. The first package body is spaced apart from the conductive layer. The antenna is electrically connected to the second surface of the conductive via.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 14, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Lin SHIH, Chih-Cheng LEE
  • Publication number: 20220115340
    Abstract: A monolithic microwave integrated circuit (MMIC) system includes a growth substrate, a device layer coupled to the growth substrate, a plurality of MMIC device elements coupled to the device layer, and a plurality of metallization structures coupled to the plurality of MMIC device elements. The MMIC system also includes a carrier substrate coupled to the plurality of metallization structures and a cooling structure coupled to the carrier substrate.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 14, 2022
    Applicant: Qromis, Inc.
    Inventors: Ozgur Aktas, Vladimir Odnoblyudov, Cem Basceri
  • Publication number: 20220115341
    Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Wei HSIEH, Kuo-Chang KANG
  • Publication number: 20220115342
    Abstract: An electronic component includes a substrate having a first main surface on one side and a second main surface on the other side, a chip having a first chip main surface on one side and a second chip main surface on the other side, and a plurality of electrodes formed on the first chip main surface and/or the second chip main surface, the chip being arranged on the first main surface of the substrate, a sealing insulation layer that seals the chip on the first main surface of the substrate such that the second main surface of the substrate is exposed, the sealing insulation layer having a sealing main surface that opposes the first main surface of the substrate, and a plurality of external terminals formed to penetrate through the sealing insulation layer so as to be exposed from the sealing main surface of the sealing insulation layer, the external terminals being respectively electrically connected to the plurality of electrodes of the chip.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 14, 2022
    Inventor: Masatoshi AKETA
  • Publication number: 20220115343
    Abstract: A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.
    Type: Application
    Filed: February 12, 2021
    Publication date: April 14, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
  • Publication number: 20220115344
    Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.
    Type: Application
    Filed: August 18, 2021
    Publication date: April 14, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji Won KIM, Jae Ho AHN, Sung-Min HWANG, Joon-Sung LIM, Suk Kang SUNG
  • Publication number: 20220115345
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first bond pad isolation structure within a substrate. A second bond pad isolation structure is formed with the substrate. The second bond pad isolation structure is disposed laterally between inner sidewalls of the first bond pad isolation structure. The first bond pad isolation structure and the second bond pad isolation structure are formed concurrently with one another. A bond pad is formed extending through the substrate. The bond pad comprises a conductive body overlying the second bond pad isolation structure and a conductive protrusion extending from the conductive body to below the substrate. The second bond pad isolation structure laterally wraps around the conductive protrusion.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Shih-Pei Chou, Jiech-Fun Lu
  • Publication number: 20220115346
    Abstract: A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Inventors: Brice McPherson, Daniel Martin, Jennifer Stabach
  • Publication number: 20220115347
    Abstract: Disclosed herein is a semiconductor device including a conductive member that has a main surface facing in a thickness direction, a semiconductor element that has a plurality of pads facing the main surface, a plurality of electrodes that are individually formed with respect to the plurality of pads and protrude from the plurality of pads toward the main surface, and a bonding layer for electrically bonding the main surface to the plurality of electrodes. The bonding layer includes a first region having conductivity and a second region having electrical insulation. The first region includes a metal portion. At least a part of the second region includes a resin portion.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 14, 2022
    Inventors: Yosui Futamura, Yuto Nishiyama, Masahiko Nakamura
  • Publication number: 20220115348
    Abstract: An electronic device for interconnection with an integrated circuit device is provided. The electronic device includes an interconnection surface configured to oppose the integrated circuit device with an interconnect structure disposed therebetween. The electronic device also includes at least one electronic device contact pad disposed on the interconnection surface for bonding to the interconnect structure. The at least one electronic device contact pad has at least one 3-dimensional projection configured to extend from the electronic device contact pad toward the integrated circuit device. The at least one 3-dimensional projection is configured to aid in bonding the electronic device contact pad to the interconnect structure to electrically couple the electronic device to the integrated circuit device.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 14, 2022
    Inventors: Sean F. Harris, Sean P. Kilcoyne, Aaron M. Ramirez, Joseph N. Wilde
  • Publication number: 20220115349
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond bump disposed on an upper surface of an upper conductive structure. The upper conductive structure overlies a substrate. A buffer layer is disposed along the upper surface of the upper conductive structure. The bond bump comprises a sidewall having a straight sidewall segment overlying a curved sidewall segment.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Ching-Sheng Chu, Chern-Yow Hsu
  • Publication number: 20220115350
    Abstract: Provided is a semiconductor package device including a lower redistribution substrate including a first redistribution pattern, the first redistribution pattern including a first interconnection portion and a first via portion provided on the first interconnection portion, a semiconductor chip disposed on the lower redistribution substrate, the semiconductor chip including a chip pad facing the lower redistribution substrate, an upper redistribution substrate vertically spaced apart from the lower redistribution substrate, the upper redistribution substrate including a second redistribution pattern, a vertical conductive structure disposed between the lower redistribution substrate and the upper redistribution substrate and disposed at a side of the semiconductor chip, a third redistribution pattern disposed between the lower redistribution substrate and the vertical conductive structure, and an encapsulant disposed on the semiconductor chip, the vertical conductive structure, and the third redistribution pat
    Type: Application
    Filed: May 11, 2021
    Publication date: April 14, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: KYUNG DON MUN, MYUNGSAM KANG
  • Publication number: 20220115351
    Abstract: There is provided a semiconductor device including: a semiconductor element; a support substrate configured to support the semiconductor element; an intermediate metal layer interposed between the semiconductor element and the support substrate in a thickness direction of the support substrate, wherein the semiconductor element and the intermediate metal layer are bonded by solid phase diffusion bonding; and a first positioning portion including a portion of the semiconductor element and a first portion of the intermediate metal layer and configured to suppress relative movement between the semiconductor element and the intermediate metal layer.
    Type: Application
    Filed: October 6, 2021
    Publication date: April 14, 2022
    Inventor: Katsuhiko YOSHIHARA
  • Publication number: 20220115352
    Abstract: The present disclosure relates to the field of semiconductor technology, and discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.
    Type: Application
    Filed: June 15, 2020
    Publication date: April 14, 2022
    Inventor: Ling-Yi Chuang
  • Publication number: 20220115353
    Abstract: A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Inventor: Satoshi SHIRAKI
  • Publication number: 20220115354
    Abstract: Techniques are disclosed for facilitating interconnecting semiconductor devices. In one example, a method of interconnecting a first substrate to a second substrate is provided. The method includes forming a first plurality of contacts on the first substrate. The method further includes forming an insulative layer on the first substrate. The method further includes forming a second plurality of contacts on the second substrate. The method further includes joining the first plurality of contacts to the second plurality of contacts to form interconnects between the first substrate and the second substrate. When the first and second substrates are joined, at least a portion of each of the interconnects is surrounded by the insulative layer. Related systems and devices are also provided.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Inventors: Richard E. BORNFREUND, Edward K. HUANG
  • Publication number: 20220115355
    Abstract: A stack package is disclosed. A first semiconductor die and a supporter are disposed on a package substrate. The supporter may include a second side facing a first side of the first semiconductor die having a substantially inclined surface. A second semiconductor die is stacked on the first semiconductor die and on the supporter. An encapsulant layer is formed to fill a portion between the supporter and the first semiconductor die.
    Type: Application
    Filed: March 16, 2021
    Publication date: April 14, 2022
    Applicant: SK hynix Inc.
    Inventor: Tae Hoon KIM
  • Publication number: 20220115356
    Abstract: The present application discloses a fan-out packaging structure and a packaging method for a chip. The structure includes first and second chips with oppositely fitted bottoms; metal terminals distributed around the first chip, one side of the metal terminals being on a same plane with the front of the first chip; a lead connected between the front of the second chip and the other side of the metal terminal; a packaging layer for packaging the first chip, the second chip, the lead the metal terminals; and a lead-out layer disposed on a first surface of the packaging layer and electrically connected to one side of the metal terminals and/or the front of the first chip.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 14, 2022
    Applicant: NATIONAL CENTER FOR ADVANCED PACKAGING CO., LTD.
    Inventors: Peng SUN, Yulong REN, Liqiang CAO
  • Publication number: 20220115357
    Abstract: A memory device includes: a first wafer including a first substrate, a plurality of first electrode layers and a plurality of first interlayer dielectric layers alternately stacked along first vertical channels projecting in a vertical direction on a top surface of the first substrate, and a dielectric stack comprising a plurality of dielectric layers and the plurality of first interlayer dielectric layers alternately stacked on the top surface of the first substrate; and a second wafer disposed on the first wafer, and including a second substrate, and a plurality of second electrode layers that are alternately stacked with a plurality of second interlayer dielectric layers along second vertical channels projecting in the vertical direction on a bottom surface of the second substrate and have pad parts overlapping with the dielectric stack in the vertical direction.
    Type: Application
    Filed: December 18, 2021
    Publication date: April 14, 2022
    Inventors: Sung Lae OH, Ki Soo KIM, Sang Woo PARK, Dong Hyuk CHAE
  • Publication number: 20220115358
    Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
  • Publication number: 20220115359
    Abstract: Provided is a micro-LED display, a micro-LED transferring substrate, and a method of transferring micro-LEDs using the micro-LED transferring substrate. The micro-LED includes a backplane substrate; and a plurality of sub-pixels provided on the backplane substrate, wherein at least one sub-pixel from among the plurality of sub-pixels includes a first micro-LED; and a second micro-LED different from the first micro-LED.
    Type: Application
    Filed: April 16, 2021
    Publication date: April 14, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunjoon KIM, Kyungwook HWANG, Joonyong PARK, Seogwoo HONG, Junsik HWANG
  • Publication number: 20220115360
    Abstract: A mixed light light-emitting diode device includes first, second, and third chips, each having a first-type semiconductor layer with a first surface, a second-type semiconductor layer with a second surface opposite to the first surface, and a third surface indenting from the first surface and situated on the second-type semiconductor layer. The second and third chips have their first surfaces disposed above and facing the first surface of the first chip. A first-type electrode penetrates through the second and first surfaces of the first chip and contacts all first surfaces of first, second, and third chips. Two second-type electrodes each penetrates through the second and third surfaces of the first chip and connect the first chip to one of the second and third chips.
    Type: Application
    Filed: September 22, 2021
    Publication date: April 14, 2022
    Inventors: Shih-Sian LIANG, Wei-Ming TSENG
  • Publication number: 20220115361
    Abstract: Discussed is a display device, including a substrate having an assembly region and a non-assembly region, semiconductor light emitting devices arranged on the substrate, a first wiring electrode and a second wiring electrode extended from each of the semiconductor light emitting devices, respectively, to supply an electric signal to the semiconductor light emitting devices, pair electrodes arranged on the substrate to generate an electric field when an electric current is supplied, and provided with first and second pair electrodes disposed on an opposite side to the first and second wiring electrodes with respect to the semiconductor light emitting devices, a dielectric layer disposed on the pair electrodes, and bus electrodes electrically connected to the pair electrodes, wherein the pair electrodes are arranged in parallel to each other along a direction in the assembly region, and wherein the bus electrodes are disposed in the non-assembly region.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Applicant: LG ELECTRONICS INC.
    Inventors: Juchan CHOI, Changseo PARK, Bongchu SHIM, Kiseong JEON
  • Publication number: 20220115362
    Abstract: A processor package module comprises a processor-memory stack including one or more compute die stacked and interconnected with a memory stack on a substrate. One or more photonic die is on the substrate to transmit and receive optical I/O, the one or more photonic die connected to the processor-memory stack and connected to external components through a fiber array. The substrate is mounted into a socket housing, such as a land grid array (LGA) socket. An array of processor package modules are interconnected on a processor substrate via fiber arrays and optical connectors to form a processor chip complex.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 14, 2022
    Inventors: Debendra MALLIK, Ravindranath MAHAJAN, Dipankar DAS
  • Publication number: 20220115363
    Abstract: A display device includes a substrate including pixels, a first electrode and a second electrode disposed on the substrate and spaced apart from each other, an inclined pattern disposed on the first electrode and the second electrode, the inclined pattern forming a space, and a first light emitting element disposed between the first electrode and the second electrode inside of the space formed by the inclined pattern.
    Type: Application
    Filed: May 3, 2021
    Publication date: April 14, 2022
    Applicant: Samsung Display Co., LTD.
    Inventor: Hyun KIM
  • Publication number: 20220115364
    Abstract: A display device includes a first conductive layer disposed on a substrate, a passivation layer disposed on the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, a connection pattern, the first electrode, the second electrode, and the connection pattern being spaced apart from each other, and a light emitting element, a first end and a second end of the light emitting element being disposed on the first electrode and the second electrode, respectively, wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.
    Type: Application
    Filed: September 10, 2021
    Publication date: April 14, 2022
    Applicant: Samsung Display Co., LTD.
    Inventors: Kyung Jin JEON, So Young KOO, Eok Su KIM, Hyung Jun KIM, Yun Yong NAM, Jun Hyung LIM
  • Publication number: 20220115365
    Abstract: An organic light emitting diode (OLED) display device is provided. The OLED display device includes a display panel and a camera. A first alignment mark is formed on a low pixel density area of the display panel, a second alignment mark is formed in the camera, and arrangements of the first alignment mark and the second alignment mark are consistent. Therefore, an alignment accuracy between the camera and the display panel is improved, and a purpose of adopting a blind hole in the area where the camera is mounted on the display device and displaying normally is achieved.
    Type: Application
    Filed: January 17, 2020
    Publication date: April 14, 2022
    Inventor: Dong Zhan
  • Publication number: 20220115366
    Abstract: A photoelectric conversion apparatus includes: a first substrate including an avalanche photodiode; and a second substrate, in which the first substrate and the second substrate are stacked on each other, and further includes: a temperature detection unit arranged in at least one of the first substrate and the second substrate and having an output characteristic depending on a temperature; and a temperature value generating circuit arranged outside the first substrate and configured to convert output from the temperature detection unit into a temperature value signal that is a signal indicating temperature information.
    Type: Application
    Filed: October 11, 2021
    Publication date: April 14, 2022
    Inventors: Yasuharu Ota, Yukihiro Kuroda, Kazuhiro Morimoto
  • Publication number: 20220115367
    Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Srinivas PIETAMBARAM, Gang DUAN, Deepak KULKARNI
  • Publication number: 20220115368
    Abstract: The disclosure provides integrated circuit (IC) structures and methods to form the same. Methods according to the disclosure may be performed on a substrate having a first doping type, the substrate extending between a first end and a second end. A deep well is formed within the substrate, the deep well including a well boundary defined between the deep well and a remainder of the substrate. The well boundary is horizontally distal to a midpoint between the first end and the second end of the substrate. A first active semiconductor region is formed at least partially over the substrate, and an oppositely-doped second active semiconductor region is formed at least partially over the deep well.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 14, 2022
    Inventors: Kaustubh Shanbhag, Glenn Workman
  • Publication number: 20220115369
    Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Kyu RYU, Min-Su KIM, Yong-Geol KIM, Dae-Seong LEE
  • Publication number: 20220115370
    Abstract: A method of making a semiconductor device includes steps related to forming source and drain wells of a transistor in a semiconductor substrate; forming a gate electrode of the transistor over the semiconductor substrate; forming an isolation structure in the semiconductor substrate adjacent to the transistor; and depositing a first inter-dielectric layer (ILD) material over the transistor and the isolation structure. The method also includes steps for depositing a capacitor film stack over the first ILD material, forming a pattern in the capacitor film stack over the isolation structure, and forming a capacitor plate by etching a conductive material of the capacitor film stack. Etching the conductive material includes performing a liquid etch process with a selectivity of at least 16 with regard to other materials in the capacitor film stack.
    Type: Application
    Filed: October 13, 2020
    Publication date: April 14, 2022
    Inventors: Cheng-Hung TSAI, Xi-Zong CHEN, Hsiao Chien LIN, Chia-Tsung TSO, Chih-Teng LIAO
  • Publication number: 20220115371
    Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; a control electrode provided inside a trench of the semiconductor part; a third electrode provided inside the trench; a diode element provided at the front surface of the semiconductor part; a resistance element provided on the front surface of the semiconductor part via an insulating film, the diode element being electrically connected to the second electrode; a first interconnect electrically connecting the diode element and the resistance element, the first interconnect being electrically connected to the third electrode; and a second interconnect electrically connecting the resistance element and the semiconductor part. The resistance element is connected in series to the diode element. The diode element is provided to have a rectifying property reverse to a current direction flowing from the resistance element to the second electrode.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Inventors: Hiroaki Katou, Tatsuya Nishiwaki, Kenya Kobayashi
  • Publication number: 20220115372
    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 14, 2022
    Inventors: Aaron LILAK, Patrick MORROW, Gilbert DEWEY, Willy RACHMADY, Rishabh MEHANDRU
  • Publication number: 20220115373
    Abstract: A SiC integrated circuit structure which allows multiple power MOSFETs or LDMOSs to exist in the same piece of semiconductor substrate and still function as individual devices which form the components of a given circuit architecture, for example, and not by limitation, in a half-bridge module. In one example, a deep isolation trench is etched into the silicon carbide substrate surrounding each individual LDMOS device. The trench is filled with an insulating material. The depth of the trench may be deeper than the thickness of an epitaxial layer to ensure electrical isolation between the individual epitaxial layer regions housing the individual LDMOSs. The width of the trench may be selected to withstand the potential difference between the bias levels of the body regions of neighboring power LDMOS devices.
    Type: Application
    Filed: November 23, 2021
    Publication date: April 14, 2022
    Applicant: CoolCAD Electronics, LLC
    Inventors: Neil GOLDSMAN, Akin AKTURK, Zeynep DILLI, Mitchell Adrian GROSS, Usama KHALID, Christopher James DARMODY
  • Publication number: 20220115374
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked structure and a second stacked structure extending above the isolation structure. The first stacked structure includes a plurality of first nanostructures stacked in a vertical direction, and the second stacked structure includes a plurality of second nanostructures stacked in the vertical direction. The semiconductor device structure includes a first dummy fin structure formed over the isolation structure, and the first dummy fin structure is between the first stacked structure and the second stacked structure. The semiconductor device structure also includes a first capping layer formed over the first dummy fin structure, and an interface between the first dummy fin structure and the first capping layer is lower than a top surface of a topmost first nanostructure.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng CHIANG, Shi-Ning JU, Chih-Hao WANG, Kuan-Ting PAN, Zhi-Chang LIN
  • Publication number: 20220115375
    Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.
    Type: Application
    Filed: June 16, 2021
    Publication date: April 14, 2022
    Inventors: Yang Xu, Hyunkwan Yu, Namkyu Cho, Dongmyoung Kim, Kanghun Moon, Sanggil Lee, Sihyung Lee
  • Publication number: 20220115376
    Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of lower electrodes arranged on a semiconductor substrate in a honeycomb structure; and a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed. A center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.
    Type: Application
    Filed: May 14, 2021
    Publication date: April 14, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cheonbae Kim, Seungjin Kim, Dongkyun Lee
  • Publication number: 20220115377
    Abstract: A semiconductor device includes a substrate including an isolation layer pattern and an active pattern, a buffer insulation layer pattern on the substrate, a polysilicon structure on the active pattern and the buffer insulation layer pattern, the polysilicon structure contacting a portion of the active pattern, and the polysilicon structure extending in a direction parallel to an upper surface of the substrate, a first diffusion barrier layer pattern on an upper surface of the polysilicon structure, the first diffusion barrier layer pattern including polysilicon doped with at least carbon, a second diffusion barrier layer pattern on the first diffusion barrier layer pattern, the second diffusion barrier layer pattern including at least a metal, and a first metal pattern and a first capping layer pattern stacked on the second diffusion barrier layer pattern.
    Type: Application
    Filed: May 27, 2021
    Publication date: April 14, 2022
    Inventors: Hyokyoung KIM, Jamin KOO, Jonghyeok KIM, Daeyoung MOON
  • Publication number: 20220115378
    Abstract: Disclosed is a vertically stacked 3D memory device, and the memory device may include a bit line extended vertically from a substrate, and including a first vertical portion and a second vertical portion, a vertical active layer configured to surround the first and second vertical portions of the bit line, a word line configured to surround the vertical active layer and the first vertical portion of the bit line, and a capacitor spaced apart vertically from the word line, and configured to surround the vertical active layer and the second vertical portion of the bit line.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Kun-Young LEE, Sun-Young KIM
  • Publication number: 20220115379
    Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.
    Type: Application
    Filed: April 30, 2021
    Publication date: April 14, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yanghee Lee, Seokhan Park, Sungchang Park, Boun Yoon, Ilyoung Yoon, Youngsuk Lee, Junseop Lee, Seungho Han, Jaeyong Han, Jeehwan Heo
  • Publication number: 20220115380
    Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a capacitor including first and second electrodes and a dielectric layer. The dielectric layer may include a zirconium aluminum oxide layer including a first zirconium region adjacent to the first electrode, a first aluminum region, a second aluminum region adjacent to the second electrode, and a second zirconium region between the first and second aluminum regions. The first and second zirconium regions may include zirconium and oxygen and may be devoid of aluminum. The first and second aluminum regions may include aluminum and oxygen and may be devoid of zirconium. The first aluminum region and the first zirconium region may be spaced apart by a first distance, and the first aluminum region and the second zirconium region may be spaced apart by a second distance shorter than the first distance.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Kyooho Jung, Jeong-Gyu Song, Younsoo Kim, Jooho Lee
  • Publication number: 20220115381
    Abstract: The present disclosure provides a semiconductor structure having a fin structure and a method of manufacturing the semiconductor structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 14, 2022
    Inventor: MIN-CHUNG CHENG
  • Publication number: 20220115382
    Abstract: A semiconductor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dongjun LEE, Sang Chul SHIN, Bong-Soo KIM, Jiyoung KIM
  • Publication number: 20220115383
    Abstract: Disclosed are semiconductor devices and their fabrication methods. The method includes forming an etching target on a substrate including cell and key regions, forming lower and upper mask layers on the etching target, performing photolithography to form an upper mask pattern including a hole on the cell region, a preliminary key pattern on the key region, a bar pattern on the key region, and a trench between the preliminary key pattern and the bar pattern, forming pillar and dam patterns filling the hole and the trench, performing photolithography to remove the upper mask pattern except for the bar pattern, using the pillar pattern, the dam pattern, and the bar pattern as an etching mask to form a lower mask pattern, and using the lower mask pattern as an etching mask to form an etching target pattern on the cell region and a key pattern on the key region.
    Type: Application
    Filed: April 22, 2021
    Publication date: April 14, 2022
    Inventors: HYUN-CHUL YOON, SUNGUN KWON, HANSEUNG KWAK, JIHEE KIM, SUNGHOON CHOI
  • Publication number: 20220115384
    Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region and a core/peripheral region around the cell region, forming a gate insulating film on the substrate of the core/peripheral region, forming a first conductive film of a first conductive type on the gate insulating film, forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction, after forming the diffusion blocking film, forming an impurity pattern including impurities within the first conductive film, diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type and forming a metal gate electrode on the second conductive film, wherein the diffusion blocking film includes helium (He) and/or argon (Ar).
    Type: Application
    Filed: April 28, 2021
    Publication date: April 14, 2022
    Inventors: Ho Kyun An, Bumsoo KIM
  • Publication number: 20220115385
    Abstract: The disclosure relates to a method for manufacturing a semiconductor device, a semiconductor device and a memory, and belongs to the field of semiconductor technologies. The method for manufacturing the semiconductor device includes: a semiconductor substrate is provided; a shallow trench isolation structure and a plurality of grooves arranged at intervals are formed on the semiconductor substrate, and a substrate bulge is formed between two adjacent grooves; a gate oxide layer is deposited on the surface of the semiconductor substrate, and the gate oxide layer covers the grooves and the substrate bulge; a gate structure is formed on the gate oxide layer, the gate structure includes a first gate structure and a second gate structure, and the first gate structure covers the surface of the substrate bulge; and a source electrode and a drain electrode are formed in the semiconductor substrate.
    Type: Application
    Filed: September 8, 2021
    Publication date: April 14, 2022
    Inventors: Shiran ZHANG, Zhengqing SUN, Youquan YU