Abstract: Provided is a FET resistive frequency mixing device having improved RF-LO and IF-LO isolations. The frequency mixing device includes: a field effect transistor (FET), a local oscillation matching circuit connected to a gate of the FET to transfer a local oscillation signal to the gate of the FET, a gate biasing circuit connected to the gate of the FET, a radio frequency (RF) matching circuit having a first terminal connected to a drain side of the FET and a second terminal serving as a RF terminal to receive or output a RF signal, an intermediate frequency (IF) matching circuit having a first terminal connected to the drain side of the FET and a second terminal serving as an IF terminal to receive or output an IF signal, and a series resonance circuit providing a path from the drain of the FET to ground for the local oscillation signal.

Abstract: Maximum voltage detection in a power management circuit is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. The voltage processing circuit includes a maximum signal detector circuit configured to generate a windowed time-variant target voltage that is higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. In this regard, the windowed time-variant target voltage can tolerate a certain amount of group delay within the group delay tolerance window(s).

Abstract: A power management circuit operable with group delay is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. Accordingly, the voltage processing circuit generates a windowed time-variant target voltage higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. As a result, the power management circuit can generate a time-variant voltage based on the windowed time-variant target voltage to help a power amplifier to avoid amplitude clipping when amplifying an analog signal.

Abstract: A common-mode rejection receiver including a first differential amplifier arranged to receive a differential signal including receiving a positive signal of the differential signal at a first non-inverting input port and receiving a negative signal of the differential signal at a first inverting input port, and output a first differentiated signal based on a voltage differential between the positive signal and the negative signal. A clamping circuit is arranged to limit a magnitude of the first differentiated signal to a pre-determined limit. A second differential amplifier is arranged to receive the positive signal at a second inverting input port and receive the negative signal at a second non-inverting input port, and output a second differentiated signal. A matching circuit is arranged to receive the second differentiated signal output and output a matched signal. A summing circuit adds the clamped signal and matched signal and outputs a receiver output signal.

Abstract: An embodiment of the invention is a time-delay invariant predistortion approach to linearize power amplifiers in wireless RF transmitters. The predistortion architecture is based on the stored-compensation or memory-compensation principle by using a combined time-delay addressing method, and therefore, the architecture has an intrinsic, self-calibrating time-delay compensation function. The predistortion architecture only uses a lookup table to conduct both the correction of non-linear responses of a power amplifier and the compensation of any time-delay effects presented in the same system. Due to the time-delay invariant characteristic, the predistortion design has a wider dynamic range processing advantage for wireless RF signals, and therefore can be implemented in multi-carrier and multi-channel wireless systems.

Abstract: A device configured to perform wireless communication includes: a pre-distortion circuit configured to generate a pre-distorted input signal by performing pre-distortion on an input signal based on a parameter set comprising a plurality of coefficients; a power amplifier configured to generate an output signal by amplifying an RF signal based on the pre-distorted input signal; and a parameter obtaining circuit configured to obtain second memory polynomial modeling information corresponding to an operating frequency band based on first memory polynomial modeling information corresponding to each of a plurality of frequency sections and obtain a parameter set according to an indirect learning structure by using the second memory polynomial modeling information.

Abstract: The present disclosure relates to the field of amplifier circuits (driver amplifiers) for electro-optical modulators, in particular for amplifying an electrical signal for driving electro-optical modulators, an amplifier circuit is proposed for amplifying a signal comprising a gain amplifier, a distributed amplifier, a resistor, and a current source, wherein the input of the distributed amplifier is electrically connected to the output of the gain amplifier; the resistor terminates the input of the distributed amplifier; and the current source is electrically connected in parallel to the resistor. A method of setting a bias voltage of such an amplifier circuit is also proposed. Furthermore, a transmitter, in particular an optical transmitter, comprising such an amplifier circuit and a system comprising such a transmitter and a signal source are also proposed.

Abstract: The present disclosure relates to a gain stage for an amplifier and to the amplifier. The amplifier may be a broad-band amplifier, trans-impedance amplifier and/or driver amplifier. The gain stage includes a differential input transconductor, a loading network and a differential output terminal. Further, the gain stage includes at least one pair of inductances connected within the loading network or between the differential input transconductor and the differential output terminal.

Abstract: An amplification circuit includes a switch circuit, an amplifier, and a control circuit. The switch circuit has a first terminal coupled to a radio frequency signal input terminal or a system voltage terminal, a second terminal coupled to an input terminal of the amplifier, and a control terminal configured to receive a control signal. The amplifier amplifies a radio frequency signal. The control circuit generates the control signal according to a driving current generated by the amplifier. When the control circuit determines that the amplifier operates in a high power mode, the control circuit controls the control signal to adjust a conducting level between the first terminal and the second terminal of the switch circuit according to the intensity of the driving current.

Abstract: The present invention provides an offset calibration circuit used in a signal processing circuit, wherein the offset calibration circuit includes a supply voltage detection circuit and a calibration circuit. The supply voltage detection circuit is configured to detect a level of a supply voltage to generate a detection result, wherein the supply voltage is provided to an output stage in the signal processing circuit. The calibration circuit is configured to calculate a digital compensation value according to the detection result, wherein the digital compensation value is used for a digital processing circuit in the signal processing circuit to perform a DC offset calibration.

Abstract: A circuit for generating a radio frequency signal is provided. The circuit includes an amplifier configured to generate a radio frequency signal based on a baseband signal. Further, the circuit includes a power supply configured to generate a variable supply voltage based on a control signal indicating a desired supply voltage, and to supply the variable supply voltage to the amplifier. The circuit further includes an envelope tracking circuit configured to generate the control signal based on a bandwidth of the baseband signal, and to supply the control signal to the power supply.

Abstract: The present disclosure provides an audio circuit capable of inhibiting a current when mute is deactivated. An output terminal of a class D amplifier circuit is connected to an electroacoustic conversion element through a low-pass filter. An output node of a bridge circuit is connected to the output terminal. An integrator integrates and outputs, in a non-mute period in which a mute control signal is negated, a difference between an input signal and a feedback signal corresponding to an output signal generated at the output terminal, and outputs a predetermined bias voltage in a mute period in which the mute control signal is asserted. A PWM comparator compares the output of the integrator with a periodic voltage. A driver switches, in the non-mute period, the bridge circuit according to an output of the PWM comparator, and fixes an output of the bridge circuit in the mute period.

Abstract: A chopper amplifying circuit employing a negative impedance compensation technique, including a differential input end, a first-level chopper switch, a first-level amplifying circuit, a second-level chopper switch, a second-level amplifying circuit, a negative impedance converting circuit, a negative feedback unit, an input capacitor, and a differential output end, is provided. The differential input end is connected to the first-level chopper switch. An output terminal of the first-level chopper switch is connected to the first-level amplifying circuit through the input capacitor. The first-level amplifying circuit is connected to the second-level chopper switch, which is connected to the second-level amplifying circuit. The second-level amplifying circuit is connected to the differential output end, and is also connected to a feedback input end of the first-level amplifying circuit through the negative feedback unit.

Abstract: A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.

Abstract: An amplifier device and a duplexer circuit are provided. The amplifier device includes a first differential amplifier circuit and a controller. The first differential amplifier circuit includes first and second radio frequency (RF) input terminals, first and second transistors, first and second adjustable capacitor circuits, and first and second RF output terminals. The controller adjusts capacitance values of the first adjustable capacitor circuit of the first differential amplifier circuit and the second adjustable capacitor circuit of the first differential amplifier circuit according to at least one of a characteristic related to a first RF input signal of the first differential amplifier circuit, a characteristic related to the second RF input signal of the first differential amplifier circuit, a matching deviation between the first transistor and the second transistor of the first differential amplifier circuit, and a characteristic of the amplifier device.

Abstract: Disclosed is an operational amplifier based on a metal-oxide TFT. The operational amplifier includes an auxiliary amplifier and a bootstrap gain-increasing amplifier. The auxiliary amplifier adopts a two-stage positive feedback structure, including a fifth transistor, a seventh transistor, an eleventh transistor, a first amplifying unit, and a second amplifying unit. A gate of the fifth transistor serves as an input end of the operational amplifier. The bootstrap gain-increasing amplifier includes two second circuits in mutual symmetry. Each of the second circuits includes a first transistor, a second transistor, and a current source unit with a bootstrap structure.

Abstract: A multi-stage amplifier circuit includes a pre-stage amplifier circuit and a floating control circuit. The pre-stage amplifier circuit amplifies a voltage difference between its input terminals, to generate plural pre-stage transconductance currents flowing through corresponding plural pre-stage transconductance nodes. The floating control circuit includes: a floating reference transistor configured as a source follower and a floating amplifier. The floating amplifier and the floating reference transistor are coupled to form feedback control and to generate an upper driving signal and a lower driving signal according to a floating reference level in the floating control circuit. The upper driving signal is higher than the lower driving signal with a predetermined voltage difference. The floating control circuit is electrically connected to the plural pre-stage transconductance nodes and is floating in common mode relative to the pre-stage transconductance nodes.

Abstract: An amplifier for converting a differential input signal to a single ended output signal. In particular, the amplifier including a converting circuit for converting a differential input signal into a single ended output signal, the converting circuit including an input section for receiving the differential input signal and an output section including an output port for providing the single ended output signal, where the output section includes a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

Abstract: Various technologies described herein pertain to variable gain amplification for a sensor application. A multistage variable gain amplifier system provides variable gain amplification of an input signal. The multistage variable gain amplifier system includes a plurality of amplification stages. The multistage variable gain amplifier system further includes a power detector configured to detect a power level of an input signal received by the multistage variable gain amplifier system. The multistage variable gain amplifier system also includes a controller configured to control the amplification stages based on the power level of the input signal. The multistage variable gain amplifier system can output an output signal such that the amplification stages are controlled to adjust a gain applied to the input signal by the multistage variable gain amplifier system to output the output signal.

Abstract: In one example, a zone player may include a network interface, at least one processor, a non-transitory computer-readable medium, and program instructions stored on the non-transitory computer-readable medium that may be executable by the at least one processor such that the zone player is configured to receive an instruction to change a volume setting of the zone player to a requested volume level; in response to receiving the instruction to change the volume setting of the zone player to the requested volume level, adjust the volume setting of the zone player to an adapted volume level that is lower than the requested volume level; and after adjusting the volume setting of the zone player to the adapted volume level, send an indication that the volume setting of the zone player has been adjusted to the requested volume level rather than the adapted volume level.

Abstract: Volume leveler controller and controlling method are disclosed. In one embodiment, A volume leveler controller includes an audio content classifier for identifying the content type of an audio signal in real time; and an adjusting unit for adjusting a volume leveler in a continuous manner based on the content type as identified. The adjusting unit may configured to positively correlate the dynamic gain of the volume leveler with informative content types of the audio signal, and negatively correlate the dynamic gain of the volume leveler with interfering content types of the audio signal.

Abstract: A coupled resonator filter is disclosed. The coupled resonator filter is provided with high quality factor, and comprises: a first resonance unit, a second resonance unit and a main adjustment unit. In the present invention, the main adjustment unit is electrically connected between the first resonance unit and the second resonance unit, and comprises an adjustable capacitor. By changing a capacitance of the adjustable capacitor, a coupling coefficient between the first resonance unit and the second resonance unit is adjusted. As a result, the coupled resonator filter of the present invention included advantages of high controllability of the frequency bandwidth and high inhibition rate of noise signal.

Abstract: Embodiments presented herein relate to isolating a receiver circuit of an electronic device from a transmission signal and from a noise signal at a frequency range of a received signal. To do so, an isolation circuit is disposed between the receiver circuit and a transmission circuit. The isolation circuit may include multiple variable impedance devices and one or more antennas. The impedances of the variable impedance devices and the one or more antennas may be balanced such that the receiver circuit is effectively removed from the transceiver circuitry and isolated from the transmission signal. The impedance of the variable impedance devices and the one or more antennas may also be configured to isolate the receiver circuit from a noise signal generated at the transmission circuit having a frequency in the range of the receive signal.

Abstract: Embodiments presented herein relate to isolating a receiver circuit of an electronic device from a transmission signal and from a noise signal at a frequency range of a received signal. To do so, an isolation circuit is disposed between the receiver circuit and a transmission circuit. The isolation circuit may include multiple variable impedance devices and one or more antennas. The impedances of the variable impedance devices and the one or more antennas may be balanced such that the receiver circuit is effectively removed from the transceiver circuitry and isolated from the transmission signal. The impedance of the variable impedance devices and the one or more antennas may also be configured to isolate the receiver circuit from a noise signal generated at the transmission circuit having a frequency in the range of the receive signal.

Abstract: Resonator devices and filter devices are disclosed. An acoustic resonator includes a substrate and a piezoelectric plate having front and back surfaces separated by a piezoelectric plate thickness greater than or equal to 50 nm and less than or equal to 200 nm. An acoustic Bragg reflector is between the substrate and the back surface of the piezoelectric plate. A conductor pattern including an interdigital transducer (IDT) is on the front surface of the piezoelectric plate.

Abstract: The present invention relates to an acoustic wave transmission device for moving a fluid or fine particles inside the fluid to a desired position using acoustic waves, and more particularly, to an acoustic wave transmission device including an acoustic wave transmission medium that minimizes acoustic wave interference due to the acoustic wave transmission medium by reducing reflection and refraction that may be generated when acoustic waves pass through the acoustic wave transmission medium in which a fluid is accommodated, and a manufacturing method of the acoustic wave transmission medium.

Abstract: A surface acoustic wave device includes a piezoelectric substrate made of ?° rotated Y-cut X-propagation LiNbO3 having a cut angle ?, an IDT electrode on the piezoelectric substrate and including a plurality of electrode fingers, and a dielectric film on the piezoelectric substrate and covering the IDT electrode. The IDT electrode includes a main electrode layer and an auxiliary conductive layer. The main electrode layer is, compared to the auxiliary conductive layer, closer to a side of the piezoelectric substrate. The main electrode layer includes Pt as a main component. Where the film thickness of the main electrode layer is denoted as h, the film thickness of the dielectric film is denoted as H, and a wavelength determined by the electrode finger pitch of the IDT electrode is denoted as ?, the relationship in Formula (1) and Equation (2A) to Equation (2D) is satisfied.

Abstract: A sensor device that includes an integrated sensor assembly having a surface acoustic wave (SAW) sensor disposed on a piezoelectric substrate. The SAW sensor is adapted to measure an environmental condition of an environment in response to an RF signal. The SAW sensor includes an interdigitated transducer (IDT) formed on a substrate having at least a layer of a piezoelectric material. The SAW sensor includes either one or more SAW reflectors of a second IDT formed on the piezoelectric material. The SAW sensor further includes an RF antenna formed on the piezoelectric material. The SAW sensor and the RF antenna are integrated with one another on the piezoelectric material.

Abstract: Certain aspects of the present disclosure provide a surface acoustic wave (SAW) device and methods for fabricating such a SAW device. One example SAW device generally includes a piezoelectric substrate, an interdigital transducer (IDT) disposed above the piezoelectric substrate, and a plurality of first regions of dielectric material. The IDT comprises a first electrode having a first plurality of fingers and a second electrode having a second plurality of fingers interdigitated with the first plurality of fingers of the first electrode. The plurality of first regions are disposed above the piezoelectric substrate and between the first and second pluralities of fingers of the IDT, and the dielectric material has a relative permittivity greater than 3.9.

Abstract: Acoustic resonator devices and acoustic filter devices. An acoustic resonator includes a piezoelectric plate having front and back surfaces, a portion of the piezoelectric plate forming a diaphragm, and a conductor pattern on the front surface, the conductor pattern comprising an interdigital transducer (IDT), interleaved fingers of the IDT on the diaphragm. A ratio of a mark of the interleaved fingers to a pitch of the interleaved fingers is greater than or equal to 0.12 and less than or equal to 0.3. A thickness of the interleaved fingers is greater than or equal to 0.85 times a thickness of the piezoelectric plate and less than or equal to 2.5 times the thickness of the piezoelectric plate.

Abstract: A bulk acoustic wave resonator includes a substrate, a first electrode, wherein a cavity is formed between the substrate and the first electrode, a piezoelectric layer disposed on the first electrode and overlapping at least a portion of the first electrode, a second electrode disposed on the piezoelectric layer and overlapping at least a portion of the piezoelectric layer, a passivation layer having at least a portion disposed on the second electrode and overlapping at least a portion of the second electrode, and a lower frame spaced apart from the substrate and having a portion of the cavity disposed therebetween. Any one of the second electrode and the passivation layer includes a protruding portion having a first thickness and an extended portion having a second thickness less than the first thickness, and an inner end of the lower frame and an end of the protruding portion are spaced apart horizontally.

Abstract: An acoustic wave device includes first and second acoustic wave resonator units. In a first IDT electrode of the first acoustic wave resonator unit, an intersecting width region includes a central region and first and second low acoustic velocity regions at outer side portions of the central region. The first and second high acoustic velocity regions include openings along an acoustic wave propagation direction. In the second acoustic wave resonator unit, a second IDT electrode includes a central region and first and second low acoustic velocity regions at outer side portions in an intersecting width direction of the central region. At an outer side portion of the first low acoustic velocity region, openings are at a third busbar. At an outer side portion of the second low acoustic velocity region, openings are not provided for a fourth busbar.

Abstract: A bulk-acoustic wave filter device includes: a substrate; a resonance portion in which a cavity is disposed between the substrate and the resonance portion; and a cap configured to form an internal space together with the substrate, wherein filling gas including at least one of hydrogen gas and helium gas is filled in at least one of the cavity and the internal space formed by the substrate and the cap.

Abstract: Acoustic resonators and filter devices, and methods for making acoustic resonators and filter devices. An acoustic resonator includes a substrate having a surface and a single-crystal piezoelectric plate having front and back surfaces. The back surface is attached to the surface of the substrate except for a portion of the piezoelectric plate forming a diaphragm spanning a cavity in the substrate. A conductor pattern formed is formed on the front surface of the piezoelectric plate, including an interdigital transducer (IDT) with interleaved fingers of the IDT on the diaphragm. An insulating layer is formed between the piezoelectric plate and portions of the conductor pattern other than the interleaved fingers.

Abstract: An acoustic resonator device includes a diaphragm including a portion of the piezoelectric plate spanning a cavity in a substrate. A conductor pattern on a surface of the piezoelectric plate includes an interdigital transducer (IDT) with a first busbar, a second busbar, and a plurality of interleaved fingers, wherein the plurality of interleaved fingers extend alternately from the first and second busbars, overlapping portions of the plurality of interleaved fingers on the diaphragm. The conductor pattern also includes first and second reflector elements on the diaphragm proximate and parallel to a first finger of the plurality of interleaved fingers, and third and fourth reflector element on the diaphragm proximate and parallel to a last finger of the plurality of interleaved fingers.

Abstract: A filter device includes a piezoelectric substrate including a high acoustic velocity material layer and a piezoelectric layer, and series and parallel arm resonators on the piezoelectric substrate. The parallel arm resonator includes a first IDT electrode on the piezoelectric substrate, and the series arm resonator includes a second IDT electrode on the piezoelectric substrate. First and second busbars of the first IDT electrode include opening formation regions, and an occupancy ratio of areas of openings in the first and second busbars of the first IDT electrode is greater than an occupancy ratio of areas of openings in first and second busbars of the second IDT electrode. In the first and second IDT electrodes, low acoustic velocity regions sandwich a central region. A high acoustic velocity region is provided in the opening formation region of each of the first and second busbars in the first IDT electrode.

Abstract: A composite filter device includes a piezoelectric substrate made of LiNbO3, a first filter on the piezoelectric substrate, and including acoustic wave resonators, and a second filter including one end connected in common to one end of the first filter, wherein a pass band of the second filter is in a frequency band higher than a pass band of the first filter, and bulk wave radiation frequencies of all of the first and second resonators of the first filter are higher than the pass band of the second filter.

Abstract: An RF circuit device using modified lattice, lattice, and ladder circuit topologies. The devices can include a plurality of resonator devices and a plurality of resonator devices. In the ladder topology, the resonator devices are connected in series from an input port to an output port while shunt resonator devices are coupled the nodes between the resonator devices. In the lattice topology, a top and a bottom serial configurations each includes a pair of resonator devices that are coupled to differential input and output ports. A pair of shunt resonators is cross-coupled between each pair of a top serial configuration resonator and a bottom serial configuration resonator. The modified lattice topology adds baluns or inductor devices between top and bottom nodes of the top and bottom serial configurations of the lattice configuration. These topologies may be applied using single crystal or polycrystalline bulk acoustic wave (BAW) resonators.

Abstract: In an embodiment, a method for determining the phase shift between a first signal and a second signal includes: delivering the first signal to a first input of a 90° hybrid coupler; delivering the second signal to a second input of the 90° hybrid coupler; determining a first piece of information relating to a power of a first output signal delivered to a first output of the 90° hybrid coupler; determining a second piece of information relating to a power of a second output signal delivered to a second output of the coupler; and adjusting the phase of the second signal until obtaining a calibrated phase for which the first piece of information is substantially equal to the second piece of information, wherein the first and second signals have identical frequencies, and wherein the phase shift between the first signal and the second signal is equal to the calibrated phase.

Abstract: An arithmetic processing apparatus according to the present disclosure includes a digital filter. The arithmetic processing apparatus further includes a dummy data input unit configured to input dummy data to the digital filter when there is no input data input to the digital filter. The arithmetic processing apparatus further includes a cancellation processing unit configured to perform, on output data output from the digital filter, arithmetic processing for canceling an output component caused by the dummy data.

Abstract: A filter circuit includes multiple registers, a switch circuit, multiple multipliers and a summation circuit. Each register is configured to store an input. The switch circuit is coupled to the registers and configured to receive the inputs from the registers as a series of registered inputs and adjust arrangement of the inputs of the series of registered inputs to generate a series of rearranged inputs according to a count value. The count value is accumulated in response to reception of a new input of the filter circuit. The multipliers are coupled to the switch circuit. The inputs of the series of rearranged inputs are sequentially provided to the multipliers. Each multiplier is configured to generate a multiplication result according to the received input and a coefficient. The summation circuit is coupled to the multipliers and configured to sum up the multiplication results to generate an output.

Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a latch unit for latching data of the input terminal and inversely transmitting the data under control of a clock signal; and an output driving unit for inverting and outputting the data received from the latch unit; wherein the latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Abstract: A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

Abstract: An inverted group delay circuit is provided. The inverted group delay circuit can offset a group delay between a pair of signals. In a non-limiting example, the inverted group delay circuit can be configured to offset a group delay (e.g., negative group delay) between a time-variant voltage and a time-variant envelope of an analog signal. More specifically, the inverted group delay circuit can output an inverted time-variant voltage having an opposing phase and time-adjusted relative to the time-variant voltage to thereby offset the group delay between the time-variant voltage and the time-variant envelope. As such, the inverted group delay circuit can be provided in a power management integrated circuit (PMIC) to improve timing alignment between a time-variant voltage(s) and a time-variant analog signal(s) at a power amplifier(s), thus helping to reduce potential amplitude distortion when the analog signal(s) is amplified by the power amplifier(s).

Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.

Abstract: A signal analysis method for analyzing a pulse modulated input signal is described. The signal analysis method includes: receiving the pulse modulated input signal, the input signal including a symbol sequence; recovering a clock signal from the input signal, the clock signal being associated with the input signal; sampling the input signal based on the clock signal, thereby obtaining a set of input signal samples, each of the input signal samples having a certain level being constant over time; determining at least two different levels of input signal samples being associated with different symbols of the symbol sequence; and determining at least one decision threshold based on the at least two different levels determined previously, the decision threshold being associated with a symbol transition of the symbol sequence. Further, a signal analysis apparatus is described.

Abstract: A switching control circuit configured to control a switching device. The switching control circuit includes a detection circuit configured to detect whether a current flowing through the switching device is in an overcurrent state, a first signal output circuit configured to output a first signal indicating whether a time period of the overcurrent state is longer than a first time period, and a driving circuit. The driving circuit turns on the switching device based on a first input signal. The driving circuit turns off the switching device through a first switch based on a second input signal when the time period of the overcurrent state is shorter than the first time period, and through a second switch, having a greater on-resistance than the first switch, based on the second input signal and the first signal when the time period of the overcurrent state is longer than the first time period.

Abstract: A nanosecond pulser may include a plurality of switch modules, a transformer, and an output. Each of the plurality of switch modules may include one or more solid state switches. The transformer may include a core, at least one primary winding wound around at least a portion of the core, each of the plurality of switch modules may be coupled with the primary windings, and a plurality of secondary windings wound at least partially around a portion of the core. The output may output electrical pulses having a peak voltage greater than about 1 kilovolt and having a pulse width of less than about 1000 nanoseconds. The output may output electrical pulses having a peak voltage greater than about 5 kilovolts, a peak power greater than about 100 kilowatts, a pulse width between 10 nanoseconds and 1000 nanoseconds, a rise time less than about 50 nanoseconds, or some combination thereof.

Abstract: A switching arrangement for switching off an electric current with a high slew rate, especially a short-circuit current, includes a main line with a first SCR-arrangement including at least a first SCR and a first reverse conducting diode arranged in parallel to the first SCR, and a first bypass line connected to the main line and arranged in a parallel way to the first SCR-arrangement. The first bypass line includes a second SCR-arrangement comprising at least a second SCR arranged in the same polarity as the first reverse conducting diode. The first bypass line further includes at least one capacitor and a DC-voltage source connected to the capacitor for pre-charging the capacitor.

Abstract: A switch circuit is provided. The switch circuit includes a P-type transistor switch and a first P-type control transistor. The P-type transistor switch includes a first control end, a first output end, and a first input end. The first input end receives a first input signal whose logic level is one. The first P-type control transistor is coupled to the first input end and the first control end. The first P-type control transistor includes a second control end. The second control end receives a second input signal whose logic level is zero to turn on the first P-type control transistor. When the first P-type control transistor is turned on, the first input signal is transmitted to the first control end of the P-type transistor switch to turn off the P-type transistor switch.