Abstract: The present application relates to electronics and in particular to switch drive circuits and more particularly to galvanically isolated switch circuits with power transfer from the switch driver input side to the switch side. More specifically, the present application provides a switch drive circuit using a single transformer to transfer control signals to a secondary side for control of the switch along with power to a secondary side circuit to drive the switch in response to the control signals. By detecting the control signal first before drawing current, the effects of leakage inductance in the transformer are reduced.

Abstract: Disclosed herein is a sensor having an extended sensing distance range beyond conventional proximity sensors. The sensor includes an electrical component structure having a topology in which current is concentrated close to a periphery of the electrical component to produce an extended sensing field. A frequency adjustment circuit can be used to control a frequency of the sensing field to avoid jammers or other interfering signals.

Abstract: Systems or methods described herein may relate to latch-independent clock gating techniques to enable or disable an internal clock of an integrated circuit device. A programmable logic device includes a clock gating circuit that receives a clock signal and is latch independent. The clock gating circuit includes gating signal circuitry that generates a gating signal based on the clock signal and an enable signal. The clock gating circuit also includes a logic gate that generates a control signal based on the gating signal. The clock gating circuit also includes gated clock generation circuitry that generates a gated clock signal based on the clock signal and the control signal.

Abstract: Apparatus and associated methods relate to quasi-adiabatic logic gates in which at least one supply terminal receives a periodic power signal. The quasi-adiabatic logic gate is configured to perform a specific logic function operative upon one or more input signals. When the quasi-adiabatic logic gate switches the output from one logic state to another logic state, the transient switching portion of the output signal substantially tracks the periodic supply signal. Such a periodic supply signal can be one that transitions gradually between low and high voltage levels. Such periodic supply signals results in a transient switching portion of the logic signal having lower frequency components than have traditional CMOS logic gate transients. The quasi-adiabatic logic gate has a periodic clock signal that is not in phase with the periodic power signal.

Abstract: A field-programmable gate array (FPGA) for using a configuration shift chain to implement a multi-bitstream function includes a bitstream control circuit, a multi-bitstream configuration shift chain and a configurable module. The FPGA enables multi-bitstream storage configuration bits to latch configuration bitstreams by adjusting a circuit structure of a multi-bitstream configuration shift chain in a combination of a control logic of a bitstream control circuit for the multi-bitstream configuration shift chain, and outputs one latched configuration bitstream from a configuration output terminal to a configurable module through each multi-bitstream storage configuration bit as required, so that the configurable module implements a logic function corresponding to the configuration bitstream outputted by the multi-bitstream configuration shift chain.

Abstract: Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.

Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

Abstract: A method includes receiving a selection signal from a third-party device and a status signal from the third-party device. A data signal from the third-party device is latched when both the selection signal and the status signal are active. In addition, a second selection signal and a second status signal can be received from a second third-party device and a second data signal latched when both the second selection signal and the second status signal are active.

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Abstract: An integrated circuit device that includes programmable logic circuitry that includes a plurality of regions each configured to operate at different voltage levels. The regions may be separated by level shifters that enable communication between the different voltage level regions. The integrated circuitry may also include software that performs voltage aware placement and routing for a user register-transfer level design, and may direct logic to regions according to voltages defined for the regions.

Abstract: Disclosed is a charge-pump phase-locked loop based on a unipolar thin film transistor, a chip, and a method. The phase-locked loop may include: a phase-frequency detector, configured to detect a phase difference and a frequency difference between a clock Fref and a clock Fn and generate control signals UP and DOWN; a logic control module, configured to output logic state signals; a charge pump, configured to convert the logic state signals into a charging/discharging current signal; a low-pass filter, configured to output a direct-current analog control signal Vctrl; a voltage-controlled oscillator, configured to adjust an output clock frequency Fvco; and a divide-by-four circuit, configured to perform frequency division to obtain the clock Fn.

Abstract: A clock recovery circuit a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation on a test data signal by using a first reference clock signal, the test data signal having a prescribed pattern, and a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation. The second PLL circuit may be configured to perform the fine phase fixing operation on the test data signal by selectively using at least two selection reference clock signals among a plurality of second reference clock signals that are delayed from the first reference clock signal by a unit phase, in a training mode, having a phase difference of N times the unit phase, where N is an integer equal to or greater than 2.

Abstract: An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.

Abstract: A method for removing low frequency offset components from a digital data stream includes receiving, at an input of an analog-to-digital converter (ADC), an analog input signal from one or more analog front end components. The analog input signal has an associated low frequency offset due, at least in part, to the analog front end components. The method also includes generating, at an output of the ADC, a digital data stream representative of the analog input signal. The digital data stream having an associated low frequency offset due, at least in part, to the analog front end components and/or the ADC. One or more low pass infinite impulse response (IIR) filters are applied to the digital data stream to detect the low frequency offset components in the digital data stream, and generate a filtered output signal with only the low frequency offset components present.

Abstract: A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.

Abstract: A signal processor includes a signal receiving circuit, a pre-processing circuit, a period acquisition circuit, and a decoding circuit. The signal receiving circuit is configured to receive an input signal. The pre-processing circuit is configured to generate a square wave signal according to the input signal. The period acquisition circuit is configured to capture several periods of the square wave signal. The several signal periods includes several signal period groups, and each of the several signal period groups includes at least two signal periods of the several signal periods. The at least two signal periods are adjacent to each other. The decoding circuit is coupled to the period acquisition circuit and is configured to perform decoding according to a time length and a number of times of voltage value change of the several signal period groups to obtain a decoding result.

Abstract: A vehicle computing system onboard an autonomous vehicle can include one or more processors and one or more non-transitory computer-readable media that store instructions that, when executed by the one or more processors, cause the computing system to perform operations. The operations can include obtaining sensor data from one or more sensors of the autonomous vehicle; applying lossy compression to the sensor data to generate compressed sensor data; storing data describing the compressed sensor data; decompressing the compressed sensor data to generate decompressed sensor data; and inputting data describing the decompressed sensor data into an autonomy system comprising one or more machine-learned models. The autonomy system can be configured to control operations of the autonomous vehicle based on the decompressed sensor data.

Abstract: A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.

Abstract: The disclosure discloses a method and device in UE and a base station for channel coding. A first node first determines a first bit block and then transmits a first radio signal, wherein bits of the first bit block are used to generate bits of a second bit block, a third bit block comprises bits of the second bit block and the first bit block, and the third bit block is used to generate the first radio signal. The first bit block, the second bit block and the third bit block comprise P1, P2 and P3 bits, respectively.

Abstract: The disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communication. A first node generates a first bit block, performs channel coding and then transmits a first radio signal. The first bit block comprising all bits in a second bit block and all bits in a third bit block is used for an input of the channel coding, and an output of the channel coding is used for generating the first radio signal. A Cyclic Redundancy Check (CRC) bit block of a fourth bit block is used for generating the third bit block. The fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the bits in the fifth bit block are of fixed values, and the fifth bit block is composed of K bits, the K being a positive integer.

Abstract: A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.

Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Abstract: Reduced complexity decoders with improved error correction and related systems, methods, and apparatuses are disclosed. An apparatus includes an input terminal and a processing circuitry. The input terminal is provided at a physical layer device to receive, from a network, a low density parity check (LDPC) frame including bits. The bits correspond to log-likelihood ratio (LLR) messages indicating probabilities that the bits have predetermined logic values. The processing circuitry is to saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude value represented by the LLR messages, and pass the LLR messages between check nodes and message nodes. The message nodes correspond to the bits. The check nodes correspond to parity check equations of a parity check matrix.

Abstract: Reduced complexity encoders and related systems, apparatuses, and methods are disclosed. An apparatus includes a data storage device and a processing circuitry. The data storage device is to store a first data part of a transmit data frame. The transmit data frame is received from one or more higher network layers that are higher than a physical layer. The transmit data frame includes the first data part and a second data part. The second data part includes data bits having known values. The processing circuitry is to retrieve the first data part of the transmit data frame from the data storage device and determine parity vectors for the transmit data frame independently of the second data part responsive to the first data part.

Abstract: Disclosed is a voltage protection circuit for preventing power amplifier burnout in an electronic device. The electronic device includes a power amplifier (PA) configured to amplify a transmission signal, a switch configured to set a path of a signal outputted from the PA, a bias control circuit configured to control the supply of a bias current driving the PA, and a voltage protection circuit configured to provide a main control signal for turning off the PA earlier than turning off the switch based on a battery voltage providing a driving power of the electronic device, and forward the main control signal to the bias control circuit, wherein, in response to receiving the main control signal instructing to turn off the PA from the voltage protection circuit, the bias control unit stops the supply of the bias current driving the PA.

Abstract: A radio-frequency module includes a mounting substrate, a power amplifier, a low-noise amplifier, at least one first transmission filter, and at least one first reception filter. The mounting substrate has a first main surface and a second main surface. The power amplifier is disposed on a side where the first main surface of the mounting substrate is located. The low-noise amplifier is disposed on a side where the second main surface of the mounting substrate is located. The first transmission filter allows a TDD transmission signal to pass therethrough. The first reception filter allows a TDD reception signal to pass therethrough. The first transmission filter is disposed on the side where the first main surface of the mounting substrate is located. The first reception filter is disposed on the side where the second main surface of the mounting substrate is located.

Abstract: A embodiment method, for linearizing a transmission signal resulting from a quadrature amplitude modulation of an analog baseband signal and a radiofrequency amplification, comprises a demodulation of a feedback signal taken from the transmission signal, a comparison between the demodulated feedback signal and the baseband signal, a digital calculation of a predistortion control signal based on the comparison, and an analog predistortion of the analog baseband signal controlled by the predistortion control signal.

Abstract: An example object of the present disclosure is to provide a signal processing apparatus, a communication system, a signal processing method, and a program for accurately compensating for a nonlinear distortion of a signal. A signal processing apparatus 1 according to an example embodiment includes at least one memory configured to store an instruction, and at least one processor configured to execute the instruction, the processor being further configured to compensate for a nonlinear distortion component of at least one input signal containing a nonlinear distortion among a plurality of multiplexed input signals, output the compensated input signal, and generate a plurality of separated signals by separating the plurality of input signals including the output signal.

Abstract: The gain of an amplifier in a receiver operating in a cellular communication system is controlled by determining one or more gain variability metrics, which are then used to produce first and second threshold values. A frequency difference between a current carrier frequency and a target carrier frequency is ascertained and then compared to the threshold values. Target gain setting production is based on comparison results: If the frequency difference is larger than the first threshold, a first automatic gain control algorithm is performed; if the frequency difference is smaller than the first threshold and larger than the second threshold, a second automatic gain control algorithm is performed, wherein the second automatic gain control algorithm uses a current gain setting as a starting point; and if the frequency difference is smaller than both the first and second thresholds, the current gain setting is used as the target gain setting.

Abstract: An apparatus for self-generating power and a wireless switch applying same are provided. The apparatus includes a coil assembly and a permanent magnet assembly. In an initial state, left and right ends of a soft magnetic plate come into contact with a first permanent magnet and a second upper soft magnetic plate respectively to form a first closed magnetic circuit, when the soft magnetic plate is rotated relative to the permanent magnet assembly, the left and the ends of the soft magnetic plate come into contact with a first upper soft magnetic plate and a second permanent magnet respectively to form a second closed magnetic circuit, and a direction of a magnetic line of force passing through the soft magnetic plate in the first closed magnetic circuit is opposite to that of a magnetic line of force passing through the soft magnetic plate in the second closed magnetic circuit.

Abstract: A wearable article, system, and methods may include a structure configured to enclose a human body part. A first antenna, positioned with respect to the structure, is tuned to communicate, while the wearable article is being worn, according to a first wireless communication modality with a first external antenna. A second antenna, positioned with respect to the structure, is tuned to communicate according to a second wireless communication modality with a second external antenna different than the first external antenna, the second communication modality being different than the first communication modality. A transceiver, coupled to at least one of the first antenna and the second antenna, is configured to communicate via one of the first and second antennas based, at least in part, on the one of the first and second antennas coming into wireless communication contact with a corresponding one of the first and second external antennas.

Abstract: A trainable transceiver comprises a transceiver circuit, a user interface, and a control circuit in selective communication with the transceiver circuit. The control circuit is further in communication with and configured to process inputs received at the user interface. The transceiver circuit is configured to, in response to a particular input received at the user interface, transmit an activation signal to a vehicle charging station.

Abstract: Disclosed are covers for a mobile phone including aspects that protect the phone from impact and/or provide shock absorbance characteristics. Covers can include one or more protrusions that reduce the contact surface to the phone and dissipate energy. Advantageously, the one or more protrusions work with intermittent spaces to provide shock absorbing characteristics and reduce the contact surface area between the cover and the phone. In some embodiments, the protrusions can include a soft-side rectangular shape, where the protrusions are placed in an ordered array in the back wall of a cover. In some embodiments, the one or more protrusions can include a row of x-shaped protrusions interspersed with air pockets along the inside wall of the cover.

Abstract: A protective case for a mobile electronic device is disclosed herein. The protective case includes a front portion and a back portion that is configured to slide into a side of the front portion to effectuate the sealing and closure of the case. The front portion is configured to cover the front face and sides of the device and includes rails or protrusions on opposing sides of its internal surface. The back portion is configured to cover the hack side of the device and includes channels on opposing sides that are configured to be slid along the rails on the opposing sides of the internal surface of the front component and thereby open and close the case. The protective case is configured to be reversibly attached to a stand that facilitates multiple viewing/operating positions.

Abstract: Various embodiments relate to spread spectrum communication. A communication system may include a base station and a user equipment. The base station may be configured to: add a cyclic prefix (CP) to each block of a number of blocks of a first direct sequence spread spectrum (DSSS) signal to generate a first cyclic prefix-direct sequence spread spectrum (CP-DSSS) signal; add artificial noise to the first CP-DSSS signal; and transmit, via a channel, the first CP-DSSS signal. The user equipment configured to receive the first CP-DSSS signal. Associated methods and communications systems are also disclosed.

Abstract: Some embodiments of the present inventive concept provide a system for maintaining clock synchronization including an ultra-wideband (UWB) transmitting system and a UWB receiving system. The high precision input clock at the transmitting system produces a high precision clock frequency. A message is sent from the transmitting system including a transmit time of the message in UWB transmitter clock units. The message is received at the UWB receiving system at an arrival time in UWB receiver clock units. A time of flight (ToF) and an oscillator offset is calculated based on the transmit time included in the message and the arrival time. A tuning register uses the calculated oscillator adjustment to adjust the low precision resonator to synchronize the low precision resonator with the high precision input clock at the UWB transmitting system.

Abstract: Systems and methods are provided for synchronizing multiple channels in an access network, where the multiple channels are neighboring channels such that a guard band between them or use of a diplexer to prevent inter-channel interference is not required. Synchronization is achieved by defining channel MAP (media access plan) cycle structures such that all channels work in the same direction (upstream US or downstream DS) at any given time. Moreover, the network controller of channel may send out a beacon to allow new nodes to join. A long MAP cycle (402) may be followed by three consecutive regular MAP cycles (404, 406), and (408). These MAP cycles are repeated between beacon transmissions. Synchronization allows multiple channels to be configured contiguous (without a guard band between neighbouring channels) and without utilizing diplexers. A plurality of customer premises equipment may operate on each of the communications channels.

Abstract: Methods and devices for dynamically designated first and second subsets of a plurality of frequency channels as upstream and downstream channels, respectively, for performing wired communications using virtual segmentation between a network controller and an endpoint device. performing virtual segmentation to service an endpoint device. Communications are performed between the network controller and the endpoint device through a wired communication medium using the upstream and downstream channels. The first subset and second subsets of the plurality of channels are designated as upstream channels and downstream channels, respectively, based at least in part on one or both of upstream and downstream channel demand and channel availability.

Abstract: A method and an apparatus providing common path distortion (CPD) detection from a field instrument, particularly when the source of the common path distortion is at a portion of the network beyond the subscriber's tap.

Abstract: A transmitter device for transmission of data via DC power distribution lines includes a sequence generator arranged for receiving a raw data bit stream to be transmitted over a positive and a negative DC power distribution line and for deriving a switching sequence based on the raw data bit stream, and a circuit including one or more capacitors and a plurality of switches controllable with the switching sequence derived in the sequence generator. The circuit is arranged for injecting in the positive and negative DC power distribution lines symmetric displacement currents resulting from displacing charges on the one or more capacitors when the one or more capacitors are charged or discharged according to the switching sequence. The symmetric displacement currents give rise to changes in voltage of the same magnitude and opposite polarity on the positive and negative DC power distribution lines.

Abstract: In accordance with a first aspect of the present disclosure, a near field communication (NFC) device is provided, comprising: a communication unit configured to be communicatively coupled to an NFC reader; a processing unit configured to use a plurality of emulated cards for executing one or more applications; a profile determination unit configured to determine a polling profile of said NFC reader; and a card selection unit configured to select a specific one of said emulated cards for use by the processing unit in dependence on the polling profile determined by the profile determination unit. In accordance with a second aspect of the present disclosure, a corresponding method of operating a near field communication (NFC) device is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.

Abstract: An electronic device comprising a flexible display and a method of the electronic device are provided. The method includes displaying, based on a sliding of the flexible display, an object related to a wireless charging function or a payment function, in a first region of the flexible display corresponding to a position of a first antenna included in the electronic device, and when the position of the first antenna is changed by the sliding of the flexible display, changing a display position of the object, based on the changed position of the first antenna.

Abstract: A second transmission path coupler has such a size that a signal width of a first signal that is generated by the second transmission path coupler at timings corresponding to a rising edge and a falling edge of an input signal to be input to a first transmission path coupler in a case where the input signal is transmitted to a position at which the first transmission path coupler and the second transmission path coupler perform an electric field and/or magnetic field coupling is substantially equal to or greater than a difference in a transmission delay amount corresponding to a gap of the first transmission path coupler.

Abstract: A magnetic induction communication-based vehicle control apparatus and method are disclosed. The apparatus includes a first coil (1001), a processor (1002), and a communications interface (1003). The first coil (1001) receives a signal of second coils (1004) laid along a lane. There is a preset relative location relationship between the first coil (1001) and the second coils (1004). When a vehicle equipped with the vehicle control apparatus deviates from a predetermined travel direction, the first coil (1001) generates an electromotive force signal based on a change in the relative location relationship between the first coil (1001) and the second coils (1004). The processor (1002) outputs a second signal based on the electromotive force signal, where the second signal is used to indicate the vehicle to adjust a running track to travel along the predetermined travel direction.

Abstract: Aspects described herein relate to communicating a beam report that includes beam measurements performed by one or more antenna panels and an identifier of the one or more antenna panels. The beam report may be used to determine a number of antenna panels supported by a user equipment (UE) transmitting the beam report, which may be used in configuring the UE for communicating with one or more other devices.

Abstract: Aspects of the disclosure relate to channel estimation and tracking in a wireless communication system. A wireless communication entity estimates a received signal utilizing any suitable process. The wireless communication entity applies a Wavelet decomposition filter to the estimated received signal to generate a channel coefficient estimate. The Wavelet decomposition filter may be configured to employ a Haar mother Wavelet. The wireless communication entity generates a prediction of a future channel estimate at a later time, by characterizing the channel according to a first-order autoregressive model of channel aging. Other aspects, embodiments, and features are also claimed and described.

Abstract: A base station performs joint channel estimation for a set of physical uplink shared channels (PUSCHs) with bundled DMRS from a user equipment (UE). The UE receives an indication to transmit the set of PUSCHs, each PUSCH of the set of PUSCHs comprising a corresponding DMRS from the base station. The base station transmits, and the UE receives, a sounding reference signal resource indicator for each PUSCH of the set of PUSCHs. The UE transmits the PUSCHs based on a same sounding reference single resource, the SRI for a first PUSCH of the set of PUSCHs indicating the same SRS resource.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may generate a report indicating a mapping between antenna panels and reference signal beam indications. The UE may transmit the report and apply the mapping to the antenna panels for reference signals. Numerous other aspects are provided.

Abstract: Aspects described herein relate to activating, by a user equipment (UE), or causing activation of, by a base station, one or more antenna panels at the UE. An action time for activating or deactivating the one or more antenna panels may also be used to allow processing time related to activation or deactivation of the antenna panels.

Abstract: A transmission of a sounding reference signal by an electronic device is provided. A method of an electronic device includes transmitting a signal via a first antenna subset including at least one of a plurality of antennas, measuring an emission environment of the plurality of antennas, using the signal, determining at least one antenna to be used for transmitting a sounding reference signal (SRS), based on the emission environment, and transmitting the SRS via the at least one determined antenna. The emission environment includes a strength of a reflected signal that corresponds to the signal and is reflected by the first antenna subset, or a strength of a reception signal that corresponds to the signal and is received by a second antenna subset including at least one remaining antenna.