Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

Abstract: The present disclosure relates to a graphene spin transistor for all-electrical operation at room temperature and a logic gate using the graphene Rashba spin transistor. A graphene spin transistor of the present disclosure provides a graphene spin FET (Field Effect Transistor) for all-electrical operation at room temperature without a magnetic field or a ferromagnetic electrode by utilizing the Rashba-Edelstein effect in the graphene or the spin Hall effect of a TMDC (Transition Metal Dichalcogenide) material in order to replace CMOS transistors and extend Moore's Law, and further provides a logic gate using the graphene Rashba spin transistor.

Abstract: A semiconductor device includes a collector layer, a base layer, and an emitter layer that are disposed above a substrate. An emitter mesa layer is disposed on a partial region of the emitter layer. In a plan view, the base electrode is disposed in or on a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In the plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located in an end portion of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.

Abstract: An ESD protection device may be provided, including: a substrate including a first conductivity region and a second conductivity region arranged therein. The first conductivity region may include a first terminal region and a second terminal region electrically coupled with each other. The second conductivity region may include a third terminal region and a fourth terminal region electrically coupled with each other. The second conductivity region may further include a fifth terminal region electrically coupled with the first and second terminal regions. The fifth terminal region may be arranged laterally between the third terminal region and the fourth terminal region. The first conductivity region, the first terminal region, the third terminal region, and the fifth terminal region may have a first conductivity type. The second conductivity region, the second terminal region, and the fourth terminal region may have a second conductivity type different from the first conductivity type.

Abstract: Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

Abstract: A silicon carbide planar MOSFET includes a junction field-effect transistor (JFET) region that extends up to a top planar surface of the substrate. The JFET region includes a central area, which comprises a portion of the drift region that extends vertically to the top planar surface. First and second sidewall areas are disposed on opposite sides of the central area. The central area has a first lateral width and a first doping concentration. The first and second sidewall areas extend vertically to the top planar surface, with each having a second lateral width. The first and second sidewall areas each have a second doping concentration that is greater than the first doping concentration such that, at a zero bias condition, first and second depletion regions respectively extend only within the first and second sidewall areas of the JFET region.

Abstract: A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

Abstract: A method of manufacturing an insulated gate semiconductor device includes simultaneously forming a gate trench and a contact trench that respectively penetrate form a top of the electrode contact region through a main electrode contact region and a injection control region in a depth direction and respectively reach a charge transport region, the contact trench being disposed at a position laterally separated from the gate trench in a plan view; and embedding a gate electrode inside the gate trench with a gate insulating film interposed therebetween, thereby forming an insulated gate structure, and simultaneously embedding an injection suppression region inside the contact trench, the gate electrode and the injection suppression region being both made of a second semiconductor material having a narrower bandgap than a bandgap of the first semiconductor material of the charge transport region.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are disclosed. One form a semiconductor structure includes: a substrate, comprising a first region used to form a well region and a second region used to form a drift region, wherein the first region is adjacent to the second region; and a fin, protruding out of the substrate, wherein the fins comprise first fins located at a junction of the first region and the second region and second fins located on the second region, and a quantity of the second fins is greater than a quantity of the first fins.

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.

Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.

Abstract: Disclosed are a substrate for a solar cell and a method for manufacturing the same. The method include putting negative and positive electrodes facing away from each other into suspension in which at least two different types of negatively charged cellulose nanofibers are dispersed; applying a voltage across the positive and negative electrodes such that the cellulose fibers are adsorbed onto a surface of the negative electrode; and drying the negative electrode having the cellulose fibers adsorbed thereon.

Abstract: The present invention provides materials, structures, and methods for III-nitride-based devices, including epitaxial and non-epitaxial structures useful for III-nitride devices including light emitting devices, laser diodes, transistors, detectors, sensors, and the like. In some embodiments, the present invention provides metallo-semiconductor and/or metallo-dielectric devices, structures, materials and methods of forming metallo-semiconductor and/or metallo-dielectric material structures for use in semiconductor devices, and more particularly for use in III-nitride based semiconductor devices. In some embodiments, the present invention includes materials, structures, and methods for improving the crystal quality of epitaxial materials grown on non-native substrates.

Abstract: The present disclosure is a photoelectric conversion element including: a photoelectric conversion layer 5 including a first quantum dot 4a and a second quantum dot 4b, a ratio X of the number of heavy metal atoms to the number of oxygen group atoms is less than 2 on a surface of the nanoparticle of the first quantum dot 4a, the ratio X is greater than or equal to 2 on a surface of the nanoparticle of the second quantum dot 4b, and Equation (1) is satisfied: 0.3<N??(1), where N denotes a ratio of the number of second quantum dots to the number of first quantum dots.

Abstract: Thin-film solar cell modules and serial cell-to-cell interconnect structures and methods of fabrication are described. In an embodiment, a solar cell interconnect includes a bypass diode between adjacent solar cells to allow the flow of current around a single solar cell.

Abstract: A solar module assembly includes a frame having an upper portion encompassing an area and a mid portion disposed below the upper portion. A plurality of solar panels is arranged in a string, sandwiched between two transparent panes forming a single string panel. The solar panels occupy less than the area of the upper portion. Each of the plurality of solar panels has a pair of opposing edges. A reflector is mounted on the mid portion to reflect light selectively.

Abstract: A back surface electrode type solar cell in which a p-type region having a p-conductive type, and an n-type region which has an n-conductive type and in which maximum concentration of additive impurities for providing the n-conductive type in a substrate width direction is equal to or higher than 5×1018 atoms/cm3 are disposed on a first main surface of a crystal silicon substrate, a first passivation film is disposed so as to cover the p-type region and the n-type region, and a second passivation film is disposed on a second main surface which is a surface opposite to the first main surface so as to cover the second main surface, the first passivation film and the second passivation film being formed with a compound containing oxide aluminum.

Abstract: Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

Abstract: A method of manufacturing display device is disclosed. A substrate includes a basal layer and metal contacts on the top surface. An insulation layer is disposed on the top surface and includes a first mounting surface and a bottom surface. Multiple grooves are formed on the insulation layer and each extends from the first mounting surface to the bottom surface. The grooves respectively correspond to the metal contacts and expose respective metal contacts. An electromagnetic force is provided with a direction from the basal layer toward the insulation layer. A droplet containing multiple micro components is provided on the first mounting surface. A configuration of an electrode of the micro component corresponds to a configuration of one of the grooves. The electrode is attracted to the corresponding groove by the electromagnetic force so as to electrically contact the metal contact.

Abstract: A method for etching a semiconductor structure (110) is provided, the semiconductor structure comprising a sub-surface quantum structure (30) of a first III-V semiconductor material,beneath a surface layer (31) of a second III-V semiconductor material having a charge carrier density of less than 5×1017 cm?3. The sub-surface quantum structure may comprise, for example, a quantum well, or a quantum wire, or a quantum dot. The method comprises the steps of exposing the surface layer to an electrolyte (130), and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically etch the sub-surface quantum structure (30) to form a plurality of nanostructures, while the surface layer (31) is not etched. A semiconductor structure, uses thereof, and devices incorporating such semiconductor structures are further provided.

Abstract: In an embodiment a radiation-emitting semiconductor chip includes a semiconductor body having an active region configured to generate radiation, a first contact layer having a first contact area for external electrical contacting the radiation-emitting semiconductor chip and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area for external electrical contacting the radiation-emitting semiconductor chip and a second contact finger structure connected to the second contact area, wherein the first contact finger structure and the second contact finger structure overlap in places in plan view of the radiation-emitting semiconductor chip, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer containing a dielectric material, wherein the insulation layer is arranged in p

Abstract: Disclosed herein is an apparatus including a first three-dimensional (3-D) structure, a second 3-D structure, and a conductive layer. The first 3D structure includes a first-type doped semiconductor material having a semi-polar facet. The second 3-D structure forms a light-emitting diode (LED) and includes a second-type doped semiconductor material, an active layer, and the first-type doped semiconductor material. The conductive layer at least partially overlays and is in ohmic contact with the semi-polar facet. The conductive layer is configured to carry current that flows between the semi-polar facet and the active layer. In some embodiments, the first-type doped semiconductor material may include an N-type doped semiconductor material, and the second-type doped semiconductor material may include a P-type doped semiconductor material. The first-type doped semiconductor material of both 3-D structures may be etched from a common first-type doped semiconductor epitaxial layer.

Abstract: A group III-nitride laminated substrate includes a sapphire substrate, a first layer that is formed on the sapphire substrate and is made of aluminum nitride, a second layer that is formed on the first layer and serves as an n-type layer made of gallium nitride and doped with an n-type dopant, a third layer that is formed on the second layer and serves as a light-emitting layer made of a group III-nitride, and a fourth layer that is formed on the third layer and serves as a p-type layer made of a group III-nitride and doped with a p-type dopant. The second layer has a thickness of 7 ?m or less. A half-value width of (0002) diffraction determined through X-ray rocking curve analysis is 100 seconds or less, and a half-value width of (10-12) diffraction determined through X-ray rocking curve analysis is 200 seconds or less.

Abstract: An LED array comprises a first mesa comprising a top surface, at least a first LED including a first p-type layer, a first n-type layer and a first color active region and a tunnel junction on the first LED, a second n-type layer on the tunnel junction, the second n-type layer comprising at least one n-type III-nitride layer with >10% Al mole fraction and at least one n-type III-nitride layer with <10% Al mole fraction. The LED array further comprises an adjacent mesa comprising a top surface, the first LED, a second LED including the second n-type layer, a second p-type layer and a second color active region. A first trench separates the first mesa and the adjacent mesa, cathode metallization in the first trench and in electrical contact with the first and the second color active regions of the adjacent mesa, and anode metallization contacts on the n-type layer of the first mesa and on the anode layer of the adjacent mesa.

Abstract: In one embodiment, the optoelectronic semiconductor chip comprises a semiconductor layer sequence with an active zone for generating a radiation. The semiconductor layer sequence is based on AlInGaP and/or on AlInGaAs. A metal mirror for the radiation is located on a rear side of the semiconductor layer sequence opposite a light extraction side. A protective metallization is applied directly to a side of the metal mirror facing away from the semiconductor layer sequence. An adhesion promoting layer is located directly on a side of the metal mirror facing the semiconductor layer sequence. The adhesion promoting layer is an encapsulation layer for the metal mirror, so that the metal mirror is encapsulated at least at one outer edge by the adhesion promoting layer together with the protective metallization.

Abstract: A light-emitting diode structure for improving bonding yield is provided, which includes a light-emitting diode, a plurality of contact electrodes, an insulating layer structure, and a plurality of bonding electrodes. One surface of the light-emitting diode includes a mesa structure. The contact electrodes are on the mesa structure. The bonding electrodes are on the insulating layer structure and respectively cover at least one contact electrode. A surface of one of the bonding electrodes facing away from the light-emitting diode has a first platform and a second platform. The second platform is on the first platform. A surface area of a vertical projection of the second platform on the light-emitting diode is smaller than that of the first platform on the light-emitting diode, and said vertical projection of the second platform is within that of the first platform.

Abstract: A light emitting device includes a base including a support having a support surface. A light emitting element includes a semiconductor layer and a sapphire substrate provided on the semiconductor layer opposite to the support surface. A reflecting film provided on the sapphire substrate. A light-transmissive covering member is provided on the support surface. A height of the light-transmissive covering member viewed in a direction in which a width of the light-transmissive covering member appears smallest is 0.5 times or less of the width of the light-transmissive covering member. A light reflecting layer is provided on a first region of the base such that a first reflectivity in the first region of the base being higher than a second reflectivity in a second region of the base, the second region overlapping with the light emitting element and being surrounded by the first region as viewed in the height direction.

Abstract: The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus. The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the light emitting device 10, and the second resin molding 50 which contains YAG fluorescent material and covers the light emitting device 10. The first resin molding 40 has the recess 40c comprising the bottom surface 40a and the side surface 40b formed therein, and the second resin molding 50 is placed in the recess 40c.

Abstract: A semiconductor light-emitting device includes: a package substrate having a mounting surface on which a first circuit pattern and a second circuit pattern are disposed; a semiconductor LED chip mounted on the mounting surface, having a first surface which faces the mounting surface and on which a first electrode and a second electrode are disposed, a second surface opposing the first surface, and side surfaces located between the first surface and the second surface, the first electrode and the second electrode being connected to the first circuit pattern and the second circuit pattern, respectively; a wavelength conversion film disposed on the second surface; and a side surface inclined portion disposed on the side surfaces of the semiconductor LED chip, providing inclined surfaces, and including a light-transmitting resin containing a wavelength conversion material.

Abstract: A light emitting device includes a Chip Scale Packaged (CSP) LED, the CSP LED including an LED chip that generates blue excitation light; and a photoluminescence layer that covers a light emitting face of the LED chip, wherein the photoluminescence layer comprises from 75 wt % to 100 wt % of a manganese-activated fluoride photoluminescence material of the total photoluminescence material content of the layer. The device/CSP LED can further include a further photoluminescence layer that covers the first photoluminescence and that includes a photoluminescence material that generates light with a peak emission wavelength from 500 nm to 650 nm.

Abstract: A light-emitting housing including a housing body, a conductive structure, and a light-emitting element is provided. The housing body has an outer surface and an inner surface. The conductive structure is embedded in the housing body and penetrates the outer surface and the inner surface. A decorative film is attached to the outer surface of the housing body. The light-emitting element is disposed on the outer surface of the housing body. The light-emitting element has two wires coupled to the conductive structure. The electric structure is adapted to transmit a current to the two wires, so that the light-emitting element emits light.

Abstract: A thermoelectric material of the present invention includes copper, tin, and sulfur, wherein a ratio A/B of the number A of copper atoms to the number B of tin atoms is 0.5 to 2.5 and a content of a metal element other than copper and tin is 5 mol % or less with respect to total metal elements. Additionally, the thermoelectric material of the present invention has a thermal conductivity less than 1.0 W/(m·K) at 200 to 400° C.

Abstract: Composite nanoparticle compositions and associated nanoparticle assemblies are described herein which, in some embodiments, exhibit enhancements to one or more thermoelectric properties including increases in electrical conductivity and/or Seebeck coefficient and/or decreases in thermal conductivity. In one aspect, a composite nanoparticle composition comprises a semiconductor nanoparticle including a front face and a back face and sidewalls extending between the front and back faces. Metallic nanoparticles are bonded to at least one of the sidewalls establishing a metal-semiconductor junction.

Abstract: Operations for integrating thermoelectric devices in Fin FET technology may be implemented in a semiconductor device having a thermoelectric device. The thermoelectric device includes a substrate and a fin structure disposed on the substrate. The thermoelectric device includes a first connecting layer and a second connecting layer disposed on opposing ends of the fin structure. The thermoelectric device includes a first thermal conductive structure thermally and a second thermal conductive structure thermally coupled to the opposing ends of the fin structure. The fin structure may be configured to transfer heat from one of the first thermal conductive structure or the second thermal conductive structure to the other thermal conductive structure based on a direction of current flow through the fin structure. In this regard, the current flow may be adjusted by a power circuit electrically coupled to the thermoelectric device.

Abstract: A buffer layer can be used to smooth the surface roughness of a galvanic contact layer (e.g., of niobium) in an electronic device, the buffer layer being made of a stack of at least four (e.g., six) layers of a face-centered cubic (FCC) crystal structure material, such as copper, the at least four FCC material layers alternating with at least three layers of a body-centered cubic (BCC) crystal structure material, such as niobium, wherein each of the FCC material layers and BCC material layers is between about five and about ten angstroms thick. The buffer layer can provide the smoothing while still maintaining desirable transport properties of a device in which the buffer layer is used, such as a magnetic Josephson junction, and magnetics of an overlying magnetic layer in the device, thereby permitting for improved magnetic Josephson junctions (MJJs) and thus improved superconducting memory arrays and other devices.

Abstract: The method of bonding an interposer and an integrated circuit chip includes preparing an interposer including an insulator and conductive lines each having one end exposed to a first surface of the insulator and another end exposed to a second surface opposite to the first surface; placing a bonding mask on the interposer; forming through-holes on the bonding mask before or after the placing of the bonding mask on the interposer; filling the plurality with a conductive material; and bonding an integrated circuit chip to the bonding mask.

Abstract: An elastic wave device includes a piezoelectric body including a main surface, an IDT electrode provided on the main surface of the piezoelectric body, and a wiring electrode provided on the main surface of the piezoelectric body and electrically connected to the IDT electrode, in which the wiring electrode includes a portion that extends to an edge of the main surface of the piezoelectric body, and a width of the wiring electrode on the edge is narrower than a width of the wiring electrode in a portion not on the edge.

Abstract: In a non-limiting embodiment, a device may include a substrate, and a hybrid active structure disposed over the substrate. The hybrid active structure may include an anchor region and a free region. The hybrid active structure may be connected to the substrate at least at the anchor region. The anchor region may include at least a segment of a piezoelectric stack portion. The piezoelectric stack portion may include a first electrode layer, a piezoelectric layer over the first electrode layer, and a second electrode layer over the piezoelectric layer. The free region may include at least a segment of a mechanical portion. The piezoelectric stack portion may overlap the mechanical portion at edges of the piezoelectric stack portion.

Abstract: A multilayer piezoelectric ceramic is constituted by: piezoelectric ceramic layers which do not contain lead as a constituent element, have a perovskite compound expressed by the composition formula LixNayK1?x?yNbO3 (where 0.02<x?0.1, 0.02<x+y?1) as the primary component, and contain 0.2 to 3.0 mol of Li relative to 100 mol of the primary component; and internal electrode layers which are constituted by a metal that contains silver by 80 percent by mass or more; wherein the multilayer piezoelectric ceramic is such that Li compounds other than the primary component are localized therein. The multilayer piezoelectric element can offer excellent insulating property.

Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

Abstract: A perpendicular magnetization type three-terminal SOT-MRAM that does not need an external magnetic field is provided. A magnetoresistance effect element where a first magnetic layer/nonmagnetic spacer layer/recording layer are disposed in order, and the first magnetic layer and the nonmagnetic spacer layer are provided to a channel layer.

Abstract: A method for forming a semiconductor device includes the steps of providing a substrate having a memory region and a logic region, forming a memory stack structure on the memory region, forming a passivation layer covering a top surface and sidewalls of the memory stack structure, forming a first interlayer dielectric layer on the passivation layer, performing a post-polishing etching back process to remove a portion of the first interlayer dielectric layer and a portion of the passivation layer on the top surface of the memory stack structure, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the passivation layer, and forming an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure to contact the memory stack structure.