Abstract: According to one embodiment, a light receiving device, includes pixel regions, each comprising a photoelectric transducer. Each photoelectric transducer is connected to a quenching resistor. A deep trench isolation structure surrounds and separates each pixel region. A plurality of shallow trench isolation portions is in the light receiving device. Each shallow trench isolation portion is below a quenching resistor and on a portion the deep trench isolation structure.

Abstract: An imaging device including: a photoelectric converter that generates a signal charge by photoelectric conversion of light; a semiconductor substrate; a charge accumulation region that is an impurity region of a first conductivity type in the semiconductor substrate, the charge accumulation region being configured to receive the signal charge; a first transistor that includes, as a source or a drain, a first impurity region of the first conductivity type in the semiconductor substrate; and a blocking structure that is located between the charge accumulation region and the first transistor. The blocking structure includes a second impurity region of a second conductivity type in the semiconductor substrate, the second conductivity type being different from the first conductivity type, and a first electrode that is located above the semiconductor substrate, the first electrode being configured to be applied with a first voltage.

Abstract: The structure of an imaging device is simplified. An imaging device capable of imaging without a lens or an image processing method is provided. Image data which is out of focus is sharpened. An image processing method of image data in which a plurality of pixels are arranged is provided. Adjacent two pixels are each divided into a first region showing the same pixel value between the adjacent two pixels and a second region other than the first region, an initial value is supplied to the second region of an endmost pixel of the image data, and the pixel values of the first regions and the second regions of the plurality of arranged pixels are determined inductively and sequentially on the basis of the initial value.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a plurality of photoelectric conversion elements. The solid-state image sensor also includes a first color filter layer disposed above the photoelectric conversion elements and having a plurality of first color filter segments. The solid-state image sensor further includes a second color filter layer disposed adjacent to the first color filter layer and having a plurality of second color filter segments. The solid-state image sensor includes a first grid structure disposed between the first color filter layer and the second color filter layer. The first grid structure has a first grid height. The solid-state image sensor also includes a second grid structure disposed between the first color filter segments and between the second color filter segments. The second grid structure has a second grid height that is lower than or equal to the first grid height.

Abstract: Image sensors are provided. The image sensors may include a plurality of unit pixels and a color filter array on the plurality of unit pixels. The color filter array may include a color filter unit including four color filters that are arranged in a two-by-two array, and the color filter unit may include two yellow color filters, a cyan color filter, and one of a red color filter or a green color filter.

Abstract: An image sensor comprises an upper chip including pixels; and a lower chip placed below the upper chip, wherein a pixel of the pixels includes an optical conversion element configured that light is incident on the optical conversion element, a first storage gate or a first storage node which is electrically connected to the optical conversion element and configured to store electric charge transferred from the optical conversion element during a first time interval, and a second storage gate or a second storage node which is electrically connected to the optical conversion element and configured to store the electric charge transferred from the optical conversion element during a second time interval different from the first time interval, the pixel is configured to generate a first pixel signal on the basis of the electric charge stored in the first storage gate, the lower chip includes a frame buffer.

Abstract: A photoelectric conversion device including an effective pixel region including a plurality of effective pixels and a peripheral region provided outside the effective pixel region, the photoelectric conversion device comprising: a wiring layer; an upper electrode; and a photoelectric conversion film provided extensively over the effective pixel region and the peripheral region, wherein each of the plurality of effective pixels includes a pixel electrode disposed between the wiring layer and the photoelectric conversion film in a depth direction, the peripheral region includes a conductive layer disposed between the wiring layer and the photoelectric conversion film in the depth direction, and the upper electrode and the conductive layer are at a same potential.

Abstract: In an information compression unit 311, in an image capturing unit 121 (221), among a plurality of pixel output units that receives object light that enters without passing through any of an image capturing lens and a pinhole, pixel outputs of at least two of the pixel output units have incident angle directivity modulated into different incident angle directivity according to an incident angle of the object light. The information compression unit 311 performs compression processing to reduce an amount of data of pixel output information generated by the image capturing unit 121 (221).

Abstract: A light emitting device for a display including a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and having a side surface exposing the active layer, in which a portion of the second conductivity type semiconductor layer and the active layer along an edge of the light emitting structure is insulative in a thickness direction to define an insulation region, and the insulation region includes implanted ions.

Abstract: A lighting device is disclosed that includes a plurality of light emitting diodes arranged in an array, a plurality of trenches disposed between and optically isolating the light emitting diodes, and a patterned converter layer disposed over an array surface formed by light emitting surfaces of the light emitting diodes and upper surfaces of the trenches, the patterned converter layers including a first region having a first converter and a second region having a second converter different from the first converter, the first region and second region disposed over different areas of the array surface.

Abstract: A memory device includes a cross-point array of spin-torque transfer MRAM cells. First rail structures laterally extend along a first horizontal direction. Each of the first rail structures includes a vertical stack including, from bottom to top, a first electrically conductive line, a reference layer having a fixed magnetization direction, and a tunnel barrier layer. Second rail structures laterally extend along a second horizontal direction. Each of the second rail structures includes a second electrically conductive line that overlies the first rail structures. A two-dimensional array of pillar structures is located between a respective one of the first rail structures and a respective one of the second rail structures. Each of the pillar structures includes a free layer having energetically stable magnetization orientations that are parallel or antiparallel to the fixed magnetization direction.

Abstract: A memory cell is disclosed. The memory cell includes a storage component that includes a chalcogenide stack that includes a plurality of layers of material and a selector component that includes a Schottky diode.

Abstract: A vertical nonvolatile memory device including memory cell strings using a resistance change material is provided. Each of the memory cell strings of the nonvolatile memory device includes a semiconductor layer extending in a first direction; a plurality of gates and a plurality of insulators alternately arranged in the first direction; a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer; and a resistance change layer extending in the first direction on a surface of the semiconductor layer. The resistance change layer includes a metal-semiconductor oxide including a mixture of a semiconductor material of the semiconductor layer and a transition metal oxide.

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

Abstract: Provided is a structure 1 including an infrared light photoelectric conversion element 300 including an infrared light photoelectric conversion layer including a photoelectric conversion material that has a maximum absorption wavelength in an infrared range and generates a charge depending on absorbed light in the infrared range; a visible light photoelectric conversion element 200 that absorbs a light beam having a wavelength in a visible range and generates a charge depending on absorbed light; and an optical filter 400 that blocks and transmits a light beam of a predetermined wavelength, in which the infrared light photoelectric conversion element 300, the visible light photoelectric conversion element 200, and the optical filter 400 are provided on the same optical path, and each of the infrared light photoelectric conversion element 300 and the visible light photoelectric conversion element 200 is provided on an emission side of light from the optical filter 400.

Abstract: An organic light emitting display device includes a plurality of pixels including a first pixel and a second pixel. Each of the first pixel and the second pixel includes at least one red sub pixel, a plurality of green sub pixels, and at least one blue sub pixel. The red sub pixels and the blue sub pixels are aligned in a first direction, and the plurality of green sub pixels is disposed between the at least one red sub pixel and at least one blue sub pixel of each pixel. The red sub pixel, the plurality of green sub pixels, and the blue sub pixel of the first pixel form a first group, and the red sub pixel, the plurality of green sub pixels, and the blue sub pixel of the second pixel form a second group.

Abstract: A display device includes a first light emitting element on a first substrate and overlapping a first effective pixel area; test light emitting elements on the first substrate and overlapping the test pixel area; a first color filter on a second substrate and overlapping the first light emitting element; a first wavelength conversion pattern on the first color filter and overlapping the first color filter and the first light emitting element; a first test color filter on the second substrate and overlapping one of the test light emitting elements; and a first test wavelength conversion pattern on the second substrate and overlapping another one of the test light emitting elements. The first test wavelength conversion pattern and the first wavelength conversion pattern include a same first wavelength conversion material, and the first test color filter and the first color filter include a same first color colorant.

Abstract: One or more embodiments include a display apparatus including an opening, an apparatus for manufacturing the display apparatus, and a method of manufacturing the display apparatus capable of reducing generation of gas or foreign matter.

Abstract: An electroluminescent display device includes a substrate on which a display area and a non-display area are defined, sub-pixels disposed in the display area on the substrate and arranged along first and second directions, a light-emitting diode disposed at each sub-pixel and including a first electrode, a light-emitting layer and a second electrode, a first bank disposed between adjacent sub-pixels along the second direction and overlapping edges of the first electrode, and a second bank disposed between adjacent sub-pixels along the first direction and having an opening corresponding to a column of the sub-pixels arranged along the second direction, wherein the opening includes a first portion corresponding to the display area and a second portion corresponding to the non-display area, and a bottom surface of the light-emitting layer in the second portion has unevenness, and wherein an uneven pattern is provided under the light-emitting layer in the non-display area.

Abstract: The present disclosure provided an organic light-emitting display device comprising: a substrate where a first direction and a second direction intersecting each other are defined, the substrate on which sub-pixels arranged along the first direction and the second direction; first electrodes of organic light-emitting diodes allocated respectively to the sub-pixels; a first bank having first openings exposing the first electrodes; and a second bank having second openings exposing the first electrode on the first bank, wherein in at least one region, the second opening simultaneously exposes at least two first electrodes neighboring in the third direction.

Abstract: A display panel includes a substrate, a transistor on the substrate, a storage capacitor on the substrate and electrically connected to the transistor, a metal layer between the substrate and the transistor, a first insulating layer on the metal layer and having a first contact hole, and a wiring connected to the metal layer through the first contact hole, wherein the first insulating layer having a first hole apart from the transistor.

Abstract: A thin-film transistor substrate includes a semiconductor layer disposed on a substrate, a gate insulating layer disposed on the semiconductor layer, a first electrode that at least partly overlaps the semiconductor layer, wherein the gate insulating layer is disposed between the first electrode and the semiconductor layer, a plurality of thin-film layers disposed on the first electrode, and a second electrode that at least partly overlaps the first electrode, wherein the plurality of thin-film layers are disposed between the second electrode and the first electrode, wherein at least one of the plurality of thin-film layers includes amorphous silicon.

Abstract: An array substrate structure is provided, which includes a substrate with a first surface and a second surface opposite to the first surface. A first TFT is on the first surface of the substrate, and a second TFT is on the second surface of the substrate. A through via passes through the substrate, and the first TFT is electrically connected to the second TFT through the through via.

Abstract: A display device includes: a substrate including a display area, a peripheral area outside the display area, and a pad area in the peripheral area; a data line in the display area; and a first connection line in the display area and connected to the data line to transmit, to the data line, a signal from the pad area, wherein the first connection line includes a first portion in a first direction and a second portion bent from the first portion and in a second direction.

Abstract: A display apparatus includes a substrate including a display area, a peripheral area surrounding the display area, a function-adding area, of which at least a portion is surrounded by the display area, and a detour area disposed between tine display area and the function-adding area. The display apparatus includes a plurality of pixel circuits disposed in the display area. A plurality of driving lines are electrically connected to the pixel circuits and extend in a direction in the display area. A first detour line is disposed in the detour area and is electrically connected to a first driving line. A second detour line is disposed in the detour area. The second detour line is electrically connected to a second driving line and is disposed in a different layer from the first detour line.

Abstract: In a display device including a notch portion of a non-emission region, the display device includes: a plurality of pixels; a plurality of scan lines connected to the plurality of pixels; and a load adjusting portion connected to the scan lines on both sides of the notch portion and adjacent to an upper end portion of the notch portion, wherein the load adjusting portion includes: a load adjusting wiring connected to the scan lines on both sides of the notch portion; a first load adjusting electrode in a different layer from the load adjusting wiring and overlapping the load adjusting wiring; and a second load adjusting electrode in a different layer from the load adjusting wiring and the first load adjusting electrode and overlapping the load adjusting wiring.

Abstract: A flexible display apparatus includes a panel that includes a display area that displays images and a fan-out portion in which a plurality of wirings connected to the display area are located, and a driving chip connected to the fan-out portion and connected to the display area via the plurality of wirings. The plurality of wirings arranged in the fan-out portion may include first wirings at a first layer on the panel and second wirings at a second layer that is different from the first layer. The first wirings and the second wirings may be in an overlapping relationship above and below each other.

Abstract: A display device includes a display panel having a display area and a non-display area, signal wires disposed in the display area, connection wires disposed in the display area and electrically connected to the signal wires, and touch electrodes disposed on the connection wires. The connection wires include diagonal portions extending in a diagonal direction, and first protrusion patterns protruding from the diagonal portions of the connection wires. Parts of the first protrusion patterns overlap the touch electrodes.

Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

Abstract: The present application discloses a semiconductor device with the flowable layer. The semiconductor device includes a substrate, a first isolation layer positioned in the substrate, a first treated flowable layer positioned between the first isolation layer and the substrate, a second isolation layer positioned in the substrate, and a second treated flowable layer positioned between the second isolation layer and the substrate. A width of the first isolation layer is greater than a width of the second isolation layer, and a depth of the first isolation layer is less than a depth of the second isolation layer.

Abstract: A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.

Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate, a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate, and a third semiconductor stack having a third threshold voltage and comprising a third insulating stack positioned on the substrate. The first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other, a thickness of the first insulating stack is different from a thickness of the second insulating stack and a thickness of the third insulating stack, and the thickness of the second insulating stack is different from the thickness of the third insulating stack.

Abstract: A method for producing a transistor includes producing on a substrate provided with a semiconductor surface layer in which an active area can be formed, a gate block arranged on the active area. Lateral protection areas are formed against lateral faces of the gate block. Source and drain regions based on a metal material-semiconductor material compound are formed on either side of the gate and in the continuation of a portion located facing the gate block. Insulating spacers are formed on either side of the gate resting on the regions based on a metal material-semiconductor material compound.

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. A ring is around individual of the channel-material strings in at least one of a lowest of the conductive tiers or a lowest of the insulative tiers. Individual of the rings have a top that is below all of the memory cells. Other embodiments are disclosed.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: A semiconductor structure and a method for forming the same are provided in embodiments of the present disclosure. The forming method includes: providing a base; forming a trench in the base, and forming a first dielectric layer on the bottom surface and side walls of the trench; forming a conductor layer, the conductor layer covering the first dielectric layer on the bottom surface of the trench; forming a second dielectric layer in the trench on the conductor layer; and forming a drift region on a side, provided with the trench, of the base. The forming method can improve the breakdown voltage of an LDMOS device and also reduce the Ron of the LDMOS device, thereby improving the performance of the LDMOS device.

Abstract: A semiconductor structure and a forming method of a semiconductor structure are provided.

Abstract: Disclosed are a semiconductor structure and a forming method thereof.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.

Abstract: The present application provides a method for preparing a semiconductor device with an air gate spacer for reducing parasitic capacitance. The method includes forming a stacking structure on a semiconductor substrate; forming a first sidewall spacer, a second sidewall spacer and a sacrificial sidewall spacer on a sidewall of the stacking structure; and removing the sacrificial sidewall spacer to form an air gap between the first and second sidewall spacers. The sacrificial sidewall spacer is located between the first and second sidewall spacers, and the first and second sidewall spacers have an etching selectivity with respect to the sacrificial sidewall spacer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a side of the dummy gate. The dummy gate is replaced with a gate structure, such that that first gate spacer is on a side of the gate structure. The gate structure is etched back. After etching back the gate structure, a top portion of the first gate spacer is removed. A second gate spacer is formed over a remaining portion of the first gate spacer. After forming the second gate spacer, a dielectric cap is formed over the gate structure.

Abstract: A method includes: forming a gate over a semiconductor substrate; forming doped regions in the semiconductor substrate; depositing a dielectric layer on sidewalls of the gate, the dielectric layer including vertical portions laterally surrounding a sidewall of the gate; depositing a spacer laterally surrounding the dielectric layer, the spacer including a carbon-free portion laterally surrounding the vertical portions of the dielectric layer and a carbon-containing portion laterally surrounding the carbon-free portion; forming source/drain regions in the semiconductor substrate; performing an etching operation to remove the gate and vertical portions of the dielectric layer using the carbon-free portion as an etching stop layer to thereby expose the carbon-free portion and form a recess; and forming a gate dielectric layer and a conductive layer in the recess, wherein the gate dielectric layer extends in at least a portion of an area where the vertical portions of the dielectric layer are etched.

Abstract: A method of manufacturing a semiconductor device includes steps of (i) forming a buffer layer of an insulating material on a substrate, (ii) forming a seed layer of catalyst material containing Ni on the buffer layer, (iii) forming, on the buffer layer, an amorphous intrinsic silicon layer for forming a channel, (iv) forming, on the amorphous intrinsic silicon layer, a non-intrinsic silicon layer for forming a source and/or drain, (v) forming a metal layer on the non-intrinsic silicon layer, and (vi) performing metal induced crystallization (MIC) process for crystallization of the amorphous intrinsic silicon layer and the amorphous non-intrinsic silicon layer, and activation of the amorphous non-intrinsic silicon layer to form a conductive area.

Abstract: A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi2 contact layer located between the source and the source electrode and between the drain and the drain electrode.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Abstract: A method includes forming an active fin using a hard mask as an etching mask, wherein the active fin comprises a source region, a drain region, and a channel region, the hard mask remains over the active fin after etching the semiconductive substrate, and the hard mask has a first portion vertically overlapping the source region of the active fin, a second portion vertically overlapping the channel region of the active fin, and a third portion vertically overlapping the drain region of the active fin. A sacrificial gate is formed over the second portion of the hard mask and the channel region of the active fin. The first and third portions of the hard mask are etched. After etching the first and third portions of the hard mask, a gate spacer is formed extending along sidewalls of the sacrificial gate, and the sacrificial gate is replaced with a replacement gate.

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.