Patents Issued in April 18, 2023
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Patent number: 11631604Abstract: The present disclosure provides a load port device, a gas gate and a gas-providing method. The load port device includes a gas-providing nozzle and the gas gate. The gas-providing nozzle is used for providing gas to a wafer container. The gas gate includes a plurality of gas inlet ports, a gas-providing port and a controller. Each gas inlet port connects to a gas source. The gas-providing port connects to the gas-providing nozzle. The controller is configured to: select one of the plurality of gas inlet ports; and connect the selected gas inlet port to the gas-providing port.Type: GrantFiled: July 17, 2020Date of Patent: April 18, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Jih-Cheng Huang, Sun-Fu Chou
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Patent number: 11631605Abstract: A semiconductor processing system includes a first component and a second component. The first component forms a first chamber with a first sealed environment at a first state within the first chamber. The second component is coupled to the first component. The second component forms a second chamber with a second sealed environment at a second state within the second chamber. A third component is to change the first state of the first sealed environment within the first chamber to cause the first state to be substantially similar to the second state of the second sealed environment within the second chamber. The second sealed environment is at the second state prior to changing of the first state of the first sealed environment to be substantially similar to the second state.Type: GrantFiled: December 17, 2019Date of Patent: April 18, 2023Assignee: Applied Materials, Inc.Inventors: Michael Robert Rice, Jeffrey C. Hudgens
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Patent number: 11631606Abstract: Provided are a substrate storage apparatus and a substrate processing apparatus using the substrate storage apparatus. The substrate storage apparatus includes a housing having a loading/unloading port for loading/unloading of a substrate and configured to provide a loading space for a loaded substrate, a separation membrane coupled to the housing to divide the loading space into a plurality of separation spaces isolated from each other, a gas supplier configured to supply a purge gas into the loading space to clean the substrate, a gas discharger configured to discharge the purge gas accommodated in the loading space, and a controller configured to control supply and discharge of the purge gas for each of the plurality of separation spaces.Type: GrantFiled: August 12, 2019Date of Patent: April 18, 2023Assignee: Semes Co., Ltd.Inventors: Duk Hyun Son, Je Ho Kim
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Patent number: 11631607Abstract: A carrier includes a jig and a case. The jig is configured to hold at least one consumable to be loaded into or unloaded from a container. The case is configured to store the jig and the consumable held by the jig.Type: GrantFiled: February 5, 2020Date of Patent: April 18, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Toshiaki Toyomaki, Seiichi Kaise
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Patent number: 11631608Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.Type: GrantFiled: October 1, 2020Date of Patent: April 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kunsil Lee, Seung Hwan Lee
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Patent number: 11631609Abstract: A method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, the device having active components formed in active areas of the substrate separated by isolation trenches and which are delimited by first sidewalls, the isolation trenches being filled, at least partially, with a first dielectric material, includes a step of chemically attacking a passive section of the first bottom of the isolation trenches configured to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm. The method also includes a step of forming a passive component covering the first dielectric material and directly above the passive section.Type: GrantFiled: July 21, 2021Date of Patent: April 18, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Heimanu Niebojewski, François Andrieu, Claire Fenouillet-Beranger
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Patent number: 11631610Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.Type: GrantFiled: April 22, 2019Date of Patent: April 18, 2023Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Michael Carroll
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Patent number: 11631611Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.Type: GrantFiled: June 14, 2021Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Der-Chyang Yeh
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Patent number: 11631612Abstract: In a method of manufacturing a semiconductor device, a source/drain structure is formed over a substrate, a first interlayer dielectric (ILD) layer including one or more dielectric layers is formed over the source/drain structure, a first opening is formed in the first ILD layer to at least partially expose the source/drain structure, a sacrificial layer is formed on an inner wall of the first opening, a first insulating layer is formed on the sacrificial layer, a conductive layer is formed on the first insulating layer so as to form a source/drain contact in contact with the source/drain structure, the sacrificial layer is removed to form a space between the first insulating layer and the first ILD layer, and a second insulating layer is formed over the source/drain contact and the first ILD layer to cap an upper opening of the space, thereby forming an air gap.Type: GrantFiled: March 10, 2021Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Hua Cheng, Ya-Wen Chiu, Yi Che Chan, Lun-Kuang Tan
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Patent number: 11631613Abstract: Provided is a semiconductor device, including a substrate including a pixel region, a gate structure on the substrate in the pixel region, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer on the gate dielectric layer; a dielectric layer located over the substrate and the gate structure; and a contact located in the dielectric layer and electrically connected to the gate conductive layer. The contact includes a doped polysilicon layer in contact with the gate conductive layer; a metal layer located on the doped polysilicon layer, wherein a part of the metal layer is embedded in the doped polysilicon layer; a barrier layer located between the metal layer and the doped polysilicon layer; and a metal silicide layer located between the barrier layer and the doped polysilicon layer.Type: GrantFiled: February 25, 2021Date of Patent: April 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
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Patent number: 11631614Abstract: Certain aspects of the present disclosure are generally directed to techniques and apparatus for adjusting capacitance in one or more metal-insulator-metal (MIM) capacitors in an effort to reduce capacitance variation between semiconductor devices and improve yield during fabrication. One example method for fabricating a semiconductor device generally includes measuring a capacitance value of a MIM capacitor of the semiconductor device, determining the measured capacitance value of the MIM capacitor is above a target capacitance value for the MIM capacitor, and selectively rupturing a set of connections in the MIM capacitor based on the measured capacitance value. Selectively rupturing the set of connections in the MIM capacitor may reduce the capacitance value of the MIM capacitor to a value approximately that of the target capacitance value.Type: GrantFiled: November 29, 2021Date of Patent: April 18, 2023Assignee: QUALCOMM IncorporatedInventors: Jonghae Kim, Jin-Su Ko, Beomsup Kim, Periannan Chidambaram
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Patent number: 11631615Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, another stack structure vertically overlying the stack structure and comprising alternating levels of other conductive structures and other insulative structures, the other stack structure comprising pillars vertically overlying the strings of memory cells, each pillar comprising an other channel material in electrical communication with the channel material of the strings of memory cells, and conductive contact structures vertically overlying the other stack structure, each conductive contact structure comprising an electrically conductive contact at least partially extending into the pillars andType: GrantFiled: May 18, 2020Date of Patent: April 18, 2023Assignee: Micron Technology, Inc.Inventors: Yi Hu, Kar Wui Thong
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Patent number: 11631616Abstract: Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping.Type: GrantFiled: July 8, 2021Date of Patent: April 18, 2023Assignee: KEY FOUNDRY CO., LTD.Inventors: Young Bae Kim, Kwang Il Kim
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Patent number: 11631617Abstract: Scalable device designs for FINFET technology are provided. In one aspect, a method of forming a FINFET device includes: patterning fins in a substrate which include a first fin(s) corresponding to a first FINFET device and a second fin(s) corresponding to a second FINFET device; depositing a conformal gate dielectric over the fins; depositing a conformal sacrificial layer over the gate dielectric; depositing a sacrificial gate material over the sacrificial layer; replacing the sacrificial layer with a first workfunction-setting metal(s) over the first fin(s) and a second workfunction-setting metal(s) over the second fin(s); removing the sacrificial gate material; forming dielectric gates over the first workfunction-setting metal(s), the second workfunction-setting metal(s) and the gate dielectric forming gate stacks; and forming source and drains in the fins between the gate stacks, wherein the source and drains are separated from the gate stacks by inner spacers. A FINFET device is also provided.Type: GrantFiled: October 14, 2021Date of Patent: April 18, 2023Assignee: International Business Machines CorporationInventors: Ruilong Xie, Kangguo Cheng, Juntao Li, Chanro Park
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Patent number: 11631618Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.Type: GrantFiled: January 6, 2021Date of Patent: April 18, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
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Patent number: 11631619Abstract: Embodiments of the present disclosure provide an array substrate comprising a base substrate, a buffer layer disposed on the base substrate, an interlayer dielectric layer disposed on the buffer layer, and a protection layer disposed on the interlayer dielectric layer, where the array substrate further comprises a plurality of first test units and a plurality of test leads. The plurality of test leads are connected to the plurality of first test units in a one-to-one correspondence, and the plurality of test leads are disposed in at least two different layers. A method for manufacturing an array substrate, a display panel, and a display device are further provided.Type: GrantFiled: November 25, 2019Date of Patent: April 18, 2023Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Haitao Wang, Guangyao Li, Jun Wang, Qinghe Wang, Dongfang Wang
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Patent number: 11631620Abstract: Provided is a semiconductor device that allows reduction of a measurement time of a PCMTEG and improvement of productivity in an IC manufacturing process. A PCMTEG region 100 formed on a surface of a semiconductor substrate is divided into a main PCMTEG region 101 and a sub-PCMTEG region 102, and TEGs having specifications for their electrical characteristic values are all collectively arranged in the sub-PCMTEG region 102.Type: GrantFiled: July 8, 2020Date of Patent: April 18, 2023Assignee: ABLIC INC.Inventors: Hiroaki Takasu, Yoko Serizawa, Hiroya Suzuki, Sumitaka Goto
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Patent number: 11631621Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first magnetic element and a second magnetic element over the semiconductor substrate. The semiconductor device structure also includes a first conductive line extending exceeding an edge of the first magnetic element. The semiconductor device structure further includes a second conductive line extending exceeding an edge of the second magnetic element. The second conductive line is electrically connected to the first conductive line.Type: GrantFiled: May 24, 2021Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mill-Jer Wang, Tang-Jung Chiu, Chi-Chang Lai, Chia-Heng Tsai, Mirng-Ji Lii, Weii Liao
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Patent number: 11631622Abstract: A semiconductor device, including a substrate having an insulating plate and a conductive plate formed on the insulating plate, a semiconductor chip formed on the conductive plate, a contact part arranged on the conductive plate with a bonding member therebetween, a rod-shaped external connection terminal having a lower end portion thereof fitted into the contact part, and a lid plate having a front surface and a back surface facing the substrate. An insertion hole pierces the lid plate, forming an entrance and exit respectively on the back and front surfaces of the lid plate. The external connection terminal is inserted in the insertion hole. The semiconductor device has at least one of a guide portion with an inclined surface, fixed to a portion of the external connection terminal located in the insertion hole, or an inclined inner wall of the insertion hole.Type: GrantFiled: June 23, 2020Date of Patent: April 18, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventor: Makoto Isozaki
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Patent number: 11631623Abstract: A lead member includes a plurality of lead terminals, and the lead terminals extend from the inside to the outside of a mold resin. Each of the lead terminals has a base portion and a tip end portion on the outside of the mold resin. The base portion is disposed on a region side having a semiconductor element and extends in a direction protruding from the mold resin. The tip end portion extends in a direction different from the base portion and is disposed on the opposite side to a region having the semiconductor element as viewed from the base portion. The length by which the base portion extends differs between a pair of lead terminals adjacent to each other, among the lead terminals. At least a surface of the base portion of each of the lead terminals is covered with a coating resin.Type: GrantFiled: September 4, 2019Date of Patent: April 18, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Takamasa Iwai, Junji Fujino, Hiroshi Kawashima
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Patent number: 11631624Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a package substrate that has a first edge and a second edge opposite to the first edge. A semiconductor chip is mounted on the package substrate. A thermal interface material is positioned on the semiconductor chip. A lid is positioned over the thermal interface material. A spring biasing mechanism is included that is operable to bias the lid away from the package substrate so that the lid, when subjected to a compressive force, can translate toward the package substrate and impart a compressive force on the thermal interface material.Type: GrantFiled: December 11, 2018Date of Patent: April 18, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Kaushik Mysore Srinivasa Setty, William J. Maxwell
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Patent number: 11631625Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. The waveguide is mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency performance of the waveguide.Type: GrantFiled: August 17, 2022Date of Patent: April 18, 2023Assignee: NXP USA, INC.Inventors: Michael B. Vincent, Antonius Johannes Matheus de Graauw, Giorgio Carluccio, Waqas Hassan Syed, Maristella Spella
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Patent number: 11631626Abstract: A package structure includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive lead, and a molding compound. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board. The conductive lead contacts at least one of the second circuit layer and the third circuit layer. The conductive lead has a vertical height, and the vertical height is greater than a vertical distance between the second circuit layer and the third circuit layer. The molding compound covers the first circuit board, the second circuit board, the electronic component, and the conductive lead. The molding compound exposes the first circuit layer and the fourth circuit layer, and the conductive lead extends outside the molding compound.Type: GrantFiled: March 18, 2021Date of Patent: April 18, 2023Assignee: Unimicron Technology Corp.Inventors: Ra-Min Tain, Po-Hsiang Wang, Chi-Chun Po
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Patent number: 11631627Abstract: Provided is a method of manufacturing a semiconductor having a double-sided substrate including preparing a first substrate on which a specific pattern is formed to enable electrical connection, preparing at least one semiconductor chip bonded to a metal post, bonding the at least one semiconductor chip to the first substrate, bonding a second substrate to the metal post, forming a package housing by packaging the first substrate and the second substrate to expose a lead frame, and forming terminal leads toward the outside of the package housing. Accordingly, the semiconductor chip and the metal post are previously joined to each other and are respectively bonded to the first substrate and the second substrate so that damage generated while bonding the semiconductor chip may be minimized and electrical properties and reliability of the semiconductor chip may be improved.Type: GrantFiled: April 22, 2021Date of Patent: April 18, 2023Assignee: JMJ Korea Co., Ltd.Inventor: Yun Hwa Choi
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Patent number: 11631628Abstract: A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.Type: GrantFiled: February 26, 2021Date of Patent: April 18, 2023Assignee: Infineon Technologies AGInventors: Christian Neugirg, Peter Scherl
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Patent number: 11631629Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.Type: GrantFiled: April 28, 2022Date of Patent: April 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
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Patent number: 11631630Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.Type: GrantFiled: February 12, 2021Date of Patent: April 18, 2023Assignee: Micron Technology, Inc.Inventors: Anilkumar Chandolu, Wayne H. Huang, Sameer S. Vadhavkar
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Patent number: 11631631Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, a conductive structure and at least one via structure. The conductive structure is disposed on an upper surface of the semiconductor substrate. The at least one via structure is disposed in the semiconductor substrate. A portion of the at least one via structure extends beyond the conductive structure.Type: GrantFiled: May 28, 2021Date of Patent: April 18, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Chin-Cheng Kuo
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Patent number: 11631632Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.Type: GrantFiled: December 28, 2020Date of Patent: April 18, 2023Assignee: Texas Instruments IncorporatedInventors: Christopher Daniel Manack, Sreenivasan Kalyani Koduri
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Patent number: 11631633Abstract: A substrate structure and a semiconductor package structure including the same are provided. The substrate structure includes a circuit layer and a dielectric structure. The circuit layer has a bottom surface and a top surface opposite to the bottom surface. The dielectric structure around the circuit layer. The dielectric structure covers a first part of the bottom surface of the circuit layer, and exposes a second part of the bottom surface and the top surface of the circuit layer. The dielectric structure exposes the top surface of the circuit layer. In addition, a method of manufacturing a semiconductor package structure is also provided.Type: GrantFiled: March 17, 2021Date of Patent: April 18, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Kuang-Hsiung Chen, Bernd Karl Appelt
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Patent number: 11631634Abstract: This disclosure relates to a leadless packaged semiconductor device including a top and a bottom opposing major surfaces and sidewalls extending between the top and bottom surfaces, the leadless packaged semiconductor device further includes a lead frame structure including an array of two or more lead frame sub-structures each having a semiconductor die arranged thereon, and terminals and a track extended across the bottom surface of the semiconductor device. The track provides a region for interconnecting the semiconductor die and terminals, and the track is filled by an insulating material to isolate the lead frame sub-structures.Type: GrantFiled: March 3, 2021Date of Patent: April 18, 2023Assignee: Nexperia B.V.Inventors: On Lok Chau, Fei Wong, Ringo Cheung, Billie Bi
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Patent number: 11631635Abstract: A method includes attaching an integrated circuit chip module substrate to a printed circuit board (PCB). First region(s) of a bottom surface of the module include electrical contacts to the board, and second region(s) of the bottom surface of the module lack such contacts. Mechanical structures are assembled into the second regions. These structures allow lateral motion of the module relative to the board, and are sized and placed to inhibit bending of the second regions of the module towards the board under application of a vertical force on a top surface of the module. A package for an integrated circuit may be assembled using the method.Type: GrantFiled: January 9, 2020Date of Patent: April 18, 2023Assignee: International Business Machines CorporationInventors: Shurong Tian, Todd Edward Takken
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Patent number: 11631636Abstract: The invention relates to a module (1) in which voltages greater than 1,000 V and currents greater than 100 A are applied via supply lines, with an electrically insulating carrier (2), with a connection means (3) which has a material thickness greater than 0.3 mm and is connected to the carrier (2) via a metallization area (4) which is delimited by a first end (23) and a second end (24), with electronic components (19, 20) which are connected to the connection means (3) as required, and with cooling means (14). In order that the power is supplied from the outside via the connection means (3) directly to the module and thus the bonding processes that are customary in the prior art are omitted and parasitic inductances on the power supply are avoided, the invention proposes that the connection means (3) protrudes beyond one end (23, 24) of the metallization area (4) at least at one point, is not fixed to the carrier (2) in this area (9) and has contact means (22).Type: GrantFiled: June 7, 2021Date of Patent: April 18, 2023Assignee: CERAMTEC GMBHInventors: Alfred Thimm, Harald Kress
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Patent number: 11631637Abstract: The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of tType: GrantFiled: May 24, 2022Date of Patent: April 18, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11631638Abstract: A semiconductor structure includes first and second source/drain (S/D) features, one or more channel layers connecting the first and the second S/D features, a high-k metal gate engaging the one or more channel layers, an isolation structure, a power rail under the isolation structure, and a via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail. At least a portion of the isolation structure is under the first and the second S/D features. In a cross-section that extends through the first S/D feature and perpendicular to a direction from the first S/D feature to the second S/D feature along the one or more channel layers, the via structure extends into a gap vertically between the first S/D feature and the isolation structure.Type: GrantFiled: January 24, 2022Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
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Patent number: 11631639Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.Type: GrantFiled: February 14, 2022Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
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Patent number: 11631640Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.Type: GrantFiled: February 18, 2022Date of Patent: April 18, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Yu Chen, Chung-Liang Cheng
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Patent number: 11631641Abstract: Provided is a semiconductor device including: a circuit board; a wiring pattern; a first semiconductor chip and a second semiconductor chip; a first lead frame; and a second lead frame; wherein the first lead frame and the second lead frame each comprises: a chip joining portion provided above at least a part of the semiconductor chip; a wiring joining portion provided above at least a part of the wiring pattern; and a bridging portion for connecting the chip joining portion and the wiring joining portion; and in the first direction, a space between the bridging portion of the first lead frame and the bridging portion of the second lead frame is smaller than a space between the chip joining portion of the first lead frame and the chip joining portion of the second lead frame.Type: GrantFiled: September 28, 2020Date of Patent: April 18, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tomoya Nakayama, Akihiro Osawa
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Patent number: 11631642Abstract: A method for manufacturing a semiconductor device includes forming contacts disposed in a dielectric layer. The method of forming the contacts includes forming contact holes and then filling with a conductive material. The method of forming the contact holes includes steps of forming openings in the dielectric layer to expose active regions, introducing a first oxygen plasma and a first fluorine plasma to remove by-products and oxidize inner surfaces of the openings, introducing a second oxygen plasma and a second fluorine plasma to remove the oxidized inner surfaces and repair the active regions, introducing a third oxygen plasma to oxidize inner surfaces again to form an oxide layer, and removing the oxide layer. The cross-sectional structure of two adjacent contact holes includes a capital, a base, and a shaft between the capital and the base, wherein the shaft has a smaller width than the base and the capital.Type: GrantFiled: November 30, 2021Date of Patent: April 18, 2023Assignee: Winbond Electronics Corp.Inventors: Shu-Ming Li, Chia-Hung Liu, Tzu-Ming Ou Yang
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Patent number: 11631643Abstract: A substrate embedded electronic component package includes a core member having a cavity in which a metal layer is disposed on a bottom surface thereof, an electronic component disposed in the cavity, an encapsulant filling at least a portion of the cavity and covering at least a portion of each of the core member and the electronic component, and a connection structure disposed on the encapsulant and including a first wiring layer connected to the electronic component. A wall surface of the cavity has at least one groove portion protruding outwardly from a center of the cavity, and the groove portion extends to a same depth in the core member as a depth of the cavity.Type: GrantFiled: March 10, 2020Date of Patent: April 18, 2023Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Jung Byun, Chang Hwa Park, Sang Ho Jeong, Je Sang Park, Mi Sun Hwang, Yong Duk Lee, Jin Won Lee, Yeo Il Park
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Patent number: 11631644Abstract: A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.Type: GrantFiled: April 2, 2021Date of Patent: April 18, 2023Assignee: Micron Technology, Inc.Inventors: Owen R. Fay, Kyle K. Kirby, Akshay N. Singh
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Patent number: 11631645Abstract: A circuit module (101) includes a circuit board (1) having a main surface (1u), an electronic component (3) mounted on the main surface (1u), and a sealing resin (4) covering at least part of the electronic component (3) on the main surface (1u). A recess (7) is formed on at least part of a side surface (11) of the sealing resin (4). At least the recess (7) is covered with an electrically conductive film (6).Type: GrantFiled: October 24, 2019Date of Patent: April 18, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takahiro Okada, Kazushige Sato, Takafumi Kanno, Nobumitsu Amachi
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Patent number: 11631646Abstract: A method for producing a plurality of chips each comprising an individualisation region, each chip comprising at least: a first and a second level of the electrical tracks, and an interconnections level comprising vias. The method includes producing on the dielectric layer covering the first level a mask having openings located in line with the electrical tracks and making the dielectric layer accessible. The method includes producing, in a region of the chip comprising the individualisation region, patterns conformed so that: first openings of the hard mask are not masked by the patterns, and second openings of the hard mask are masked by the patterns. The method includes producing via openings in the dielectric layer in line solely with the first openings. The method further includes filling in the via openings with an electrically conductive material, and producing the second level of the electrical tracks on the vias.Type: GrantFiled: March 30, 2021Date of Patent: April 18, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Stefan Landis, Michaël May
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Patent number: 11631647Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.Type: GrantFiled: June 30, 2020Date of Patent: April 18, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventor: Belgacem Haba
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Patent number: 11631648Abstract: The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.Type: GrantFiled: October 21, 2020Date of Patent: April 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
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Patent number: 11631649Abstract: A bonded body includes: a first base body including a first wiring, a first electrode made of an electroplating film and including a first surface having a first region covering a periphery of an end portion of the first wiring and a second region covering the end portion of the first wiring, and a first passivation layer made of an insulating material and covering a periphery of the first electrode; a second base body including a second electrode; and solder disposed between the first region of the first electrode and the second electrode.Type: GrantFiled: June 11, 2021Date of Patent: April 18, 2023Assignee: OLYMPUS CORPORATIONInventor: Hiroshi Kobayashi
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Patent number: 11631650Abstract: An approach for transferring solder to a laminate structure in IC (integrated circuit) packaging is disclosed. The approach comprises of a device and method of applying the device. The device comprises of a substrate, a laser ablation layer and solder layer. The device is made by depositing a laser ablation layer onto a glass/silicon substrate and plenty of solder powder/solder pillar is further deposited onto the laser ablation layer. The laminate packaging substrate includes pads with a pad surface finishing layer made from gold. The solder layer of the device is bonded to the laminate packaging substrate. Once bonded, using laser to irradiate the laser ablation layer, the substrate is removed from the laminate.Type: GrantFiled: June 15, 2021Date of Patent: April 18, 2023Assignee: International Business Machines CorporationInventor: Katsuyuki Sakuma
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Patent number: 11631651Abstract: A semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes a signal bump land and an anchoring bump land, and the semiconductor chip includes a signal bump and an anchoring bump. The signal bump is bonded to the signal bump land, the anchoring bump is disposed to be adjacent to the anchoring bump land, and a bottom surface of the anchoring bump is located at a level which is lower than a top surface of the anchoring bump land with respect to a surface of the package substrate.Type: GrantFiled: August 13, 2019Date of Patent: April 18, 2023Assignee: SK hynix Inc.Inventor: Min Soo Park
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Patent number: 11631652Abstract: A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.Type: GrantFiled: October 25, 2019Date of Patent: April 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Ying-Jui Huang, Ching-Hua Hsieh, Chien-Ling Hwang, Chia-Sheng Huang
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Patent number: 11631653Abstract: An ultrasonic bonding apparatus includes an ultrasonic bonding machine having an ultrasonic tool for applying an ultrasonic wave to a bonding target member mounted on a fixed object fixed to a jig, while pressing a bonding member against the bonding target member; and a bonding inspection apparatus for inspecting a bonding quality of the bonding target member and the bonding member. The bonding inspection apparatus includes: a bonded-state measuring device for detecting a vibration in the jig or a housing of the ultrasonic bonding machine equipped with the jig, to thereby output a detection signal; and a bonded-state determination device for determining, in a bonding process for the bonding target member and the bonding member, a bonded state between the bonding target member and the bonding member on the basis of the detection signal outputted by the bonded-state measuring device.Type: GrantFiled: February 2, 2018Date of Patent: April 18, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Minoru Egusa, Shingo Sudo, Kazuyuki Hashimoto, Erubi Suzuki