Abstract: Vacuum electron devices (VEDs) having a plurality of two-dimensional layers of various materials are bonded together to form one or more VEDs simultaneously. The two-dimensional material layers are machined to include features needed for device operation so that when assembled and bonded into a three-dimensional structure, three-dimensional features are formed. The two-dimensional layers are bonded together into a sandwich-like structure. The manufacturing process enables incorporation of metallic, magnetic, ceramic materials, and other materials required for VED fabrication while maintaining required positional accuracy and multiple devices per batch capability.

Abstract: A component part in a vacuum area of an X-ray tube with an opening through which an electron beam is guided. The component part includes a base body made of a first material, wherein the first material is a metal. Arranged on a surface forming the opening is a second material having an atomic number which is smaller than an atomic number of the first material. A target support is attached to an end of the component part. The target support supports a target which is aligned with a lens diaphragm formed at the end of the component part. The target support has a base body made of a first material which is a metal, and a second material formed on a surface of the base body that is selectively exposed to the electron beam and which extends between the target and the lens diaphragm.

Abstract: The invention provides an electron beam apparatus that reduces a time required for an electron gun chamber to which a sputter ion pump and a non-evaporable getter pump are connected to reach an extreme high vacuum state. The electron beam apparatus includes an electron gun configured to emit an electron beam and the electron gun chamber to which the sputter ion pump and the non-evaporable getter pump are connected. The electron beam apparatus further includes a gas supply unit configured to supply at least one of hydrogen, oxygen, carbon monoxide, and carbon dioxide to the electron gun chamber.

Abstract: Embodiments of systems, devices, and methods relate to an electrode standoff isolator. An example electrode standoff isolator includes a plurality of adjacent insulative segments positioned between a proximal end and a distal end of the electrode standoff isolator. A geometry of the adjacent insulative is configured to guard a surface area of the electrode standoff isolator against deposition of a conductive layer of gaseous phase materials from a filament of an ion source.

Abstract: An ion milling device capable of high-speed milling is realized even for a specimen containing a material having an imide bond. Therefore, the ion milling device includes: a vacuum chamber 6 configured to hold a specimen 3 in a vacuum atmosphere; an ion gun 1 configured to irradiate the specimen with a non-focused ion beam 2; a vaporization container 17 configured to store a mixed solution 13 of a water-soluble ionic liquid and water; and nozzles 11, 12 configured to supply water vapor obtained by vaporizing the mixed solution to a vicinity of a surface of the specimen processed by the ion beam.

Abstract: Embodiments may include methods, systems, and apparatuses for correcting a response function of an electron beam tool. The correcting may include modulating an electron beam parameter having a frequency; emitting an electron beam based on the electron beam parameter towards a specimen, thereby scattering electrons, wherein the electron beam is described by a source wave function having a source phase and a landing angle; detecting a portion of the scattered electrons at an electron detector, thereby yielding electron data including an electron wave function having an electron phase and an electron landing angle; determining, using a processor, a phase delay between the source phase and the electron phase, thereby yielding a latency; and correcting, using the processor, the response function of the electron beam tool using the latency and a difference between the source wave function and the electron wave function.

Abstract: A method for structuring a decorative or technical pattern in the thickness of an object made of an at least partially transparent amorphous, semi-crystalline or crystalline material, wherein the object is made of an at least partially transparent material including a top surface and a bottom surface which extends away from the top surface. The top or bottom surfaces is provided with a mask defining an opening whose outline corresponds to the profile of the pattern to be structured, the mask covering the top or bottom surface at the positions which are not to be structured. The pattern is structured with a mono- or multicharged ion beam through the opening of the mask, wherein the mechanical properties of the mask are sufficient to prevent the ions of the ion beam from etching the top or bottom surface at the positions where this top or bottom surface is covered by the mask.

Abstract: Aspects of the disclosure provide a method of preparing a focused ion beam (FIB) sample and analyzing the sample in an electron microscope system. The method can include forming, over a substrate, a target film having a thickness of less than a threshold corresponding to a limit for FIB requirements, and forming a supporting film over the target film. The method can also include obtaining a FIB sample that includes a portion of the target film and a portion of the supporting film and. The method can further include analyzing the obtained portion of the target film in an electron microscope system.

Abstract: A method of reducing reflected Radio Frequency (RF) power in substrate processing chambers may include accessing input parameters for a processing chamber that are derived from a recipe to perform a process on a substrate. The input parameters may be provided to a model that has been trained using previous input parameters and corresponding sensor measurements for the chamber. A predicted amount of reflected RF power may be received from the model and it may be determined whether the predicted reflected RF power is optimized. The input parameters may be repeatedly adjusted and processed by the model until input parameter values are found that optimize the reflected RF power. Optimized input parameters may then be provided to the chamber to process the substrate.

Abstract: There is provision of an electrostatic chuck for supporting a substrate and an edge ring including a first region, a second region, an electrode provided in the second region, and an elastic member. The first region includes a first top surface and is configured to hold the substrate that is placed on the first top surface. The second region extends in a circumferential direction of the first region so as to surround the first region. The second region includes a second top surface, and is configured to support the edge ring placed on the second top surface. The first top surface and the second top surface extend along a single flat plane. A part of the edge ring is accommodated in a space provided between the first region and the second region, and the elastic member is disposed between the part of the edge ring and the electrostatic chuck.

Abstract: The inventive concept relates to an apparatus and a method for processing a substrate. In an embodiment, the apparatus includes a process chamber having a processing space inside, a support unit that supports the substrate in the processing space, a gas supply unit that supplies a process gas into the processing space, and a plasma source that generates plasma from the process gas. The support unit includes a support on which the substrate is placed, an edge ring around the substrate placed on the support, an impedance adjustment member provided below the edge ring, and a temperature adjustment member that variably adjusts temperature of the impedance adjustment member.

Abstract: Methods and systems for processing substrates are provided. The system can include: a processing chamber configured to process a substrate based on a recipe; a plurality of sub-systems in operable communication with the processing chamber for controlling corresponding parameters associated with processing the substrate; and a controller in operable communication with the processing chamber and each of the plurality of sub-systems and configured to control each of the plurality of sub-systems and the processing chamber using information included in the recipe and feedback provided by at least one of the plurality of sub-systems. The controller is configured to compare information included in the recipe and feedback provided by at least one of the plurality of sub-systems with stored empirical information relating to the recipe and each of the plurality of sub-systems, and adjust at least one of the corresponding parameters associated with processing the substrate based on a determined comparison.

Abstract: Provided is a sputtering target, comprising: from 0.001 mol % to 0.5 mol % of Bi; from 45 mol % or less of Cr; 45 mol % or less of Pt; 60 mol % or less of Ru; and a total of 1 mol % to 35 mol % of at least one metal oxide, the balance being Co and inevitable impurities.

Abstract: A film forming apparatus for forming a film on a substrate by using a magnetron sputtering method. The film forming apparatus includes: a substrate holder configured to hold a substrate; a target holder configured to hold a target made of a ferromagnetic material to face the substrate holder; a magnet provided on a surface of the target holder opposite to the substrate holder, and configured to leak a magnetic field to a front surface of the target held by the target holder that is a surface close to the substrate holder; and a magnetic field strength measurement device configured to measure a strength of the magnetic field.

Abstract: A photoelectric tube includes a housing including a light transmitting portion, an electron emitting portion held by a recess provided in the housing, the electron emitting portion including a concave photoelectric surface facing a light transmitting portion side inside the housing, and an electron capturing portion disposed between the light transmitting portion and the photoelectric surface inside the housing. At least a part of the electron capturing portion is located inside a region on an inside of the photoelectric surface.

Abstract: Provided is a high voltage driving device including a housing and a cathode, an anode, and an insulation structure, which are disposed in the housing. Here, the cathode and the anode are spaced apart from each other with the insulation structure therebetween. Also, the insulation structure includes a first solid insulator disposed adjacent to the cathode and a second solid insulator disposed adjacent to the anode. Also, the first solid insulator has first volumetric resistivity less than second volumetric resistivity of the second solid insulator, and the first solid insulator contacts the cathode.

Abstract: Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a BOW value of ?2.0 to 2.0 ?m, as measured with the back surface of the indium phosphide substrate facing upward.

Abstract: A fabrication method of a semiconductor device comprises the steps of: providing a substrate, which is divided into several chip areas; forming a protective layer on the substrate, the protective layer covers the scribe lines and the chip areas; exposing and developing the protective layer to form a plurality of grooves in the protective layer over the chip areas, and the depth of the grooves is smaller than the initial thickness of the protective layer.

Abstract: Disclosed are methods and systems for providing silicon carbide films. A layer of silicon carbide can be provided under process conditions that employ one or more silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors may also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the silicon carbide film. The one or more radical species can be formed in a remote plasma source.

Abstract: Exemplary methods of semiconductor processing may include forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber. The methods may include depositing a carbon-containing material on a substrate housed in the processing region of the semiconductor processing chamber. The methods may include halting a flow of the carbon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include contacting the carbon-containing material with plasma effluents of an oxidizing material. The methods may include forming volatile materials from a surface of the carbon-containing material.

Abstract: A laser annealing apparatus according to an embodiment includes a laser light source, an annealing optical system, a linear irradiation region along a Y-direction, a moving mechanism configured to change a relative position of the irradiation region with respect to the substrate along an X-direction, an illumination light source configured to generate illumination light for illuminating the substrate along a third direction, and a detector configured to detect detection light reflected, in a fourth direction, on the substrate illuminated by the illumination light so as to photograph an annealed part of the substrate in a linear field of view along the Y-direction. In a YZ-plane view, the third direction is inclined from the vertical direction and the fourth direction is inclined from the vertical direction.

Abstract: Methods to manufacture integrated circuits are described. Nanocrystalline diamond is used as a hard mask in place of amorphous carbon. Provided is a method of processing a substrate in which nanocrystalline diamond is used as a hard mask, wherein processing methods result in a smooth surface. The method involves two processing parts. Two separate nanocrystalline diamond recipes are combined—the first and second recipes are cycled to achieve a nanocrystalline diamond hard mask having high hardness, high modulus, and a smooth surface. In other embodiments, the first recipe is followed by an inert gas plasma smoothening process and then the first recipe is cycled to achieve a high hardness, a high modulus, and a smooth surface.

Abstract: Semiconductor structures and fabrication methods thereof are provided. The method may include providing a to-be-etched layer; forming a plurality of core layers on the to-be-etched layer, wherein a first opening and a second opening are formed between different adjacent core layers and a width of the first opening is smaller than a width of the second opening; forming a first sacrificial material layer on the to-be-etched layer and the plurality of core layers; forming a second sacrificial layer on a portion of the first sacrificial material layer in the first opening to form a sacrificial structure in the first opening; removing the plurality of core layers after forming the sacrificial structure; forming sidewall spacers on sidewall surfaces of the sacrificial structure after removing the plurality of core layers; and removing the sacrificial structure after forming the sidewall spacers.

Abstract: Methods for adjusting a work function of a structure in a substrate leverage near surface doping. In some embodiments, a method for adjusting a work function of a structure in a substrate may include coating surfaces of the structure to form a doping layer in a non-solid phase that contains dopants on the surfaces of the structure and performing a dopant diffusion process using an oxidation process to drive the dopants through the surfaces the structure to embed the dopants in the structure to adjust the work function of the structure near the surfaces to form an abrupt junction profile and form an oxidation layer on the surfaces of the structure. The coating of the surfaces of the structure may be performed using a gas-phase or liquid-phase process.

Abstract: Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200° C. by using an organic platinum group metal precursor.

Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.

Abstract: A semiconductor manufacturing device including a polishing head that is capable of retaining a semiconductor substrate; a polishing pad having a processing surface to be abutted to the semiconductor substrate retained by the polishing head, the processing surface including a groove; a platen that is capable of rotating about a rotary shaft running along a direction intersecting the processing surface, in a state in which the polishing pad is retained by the platen; a measuring section that outputs a measurement value indicating a height of the processing surface at a predetermined location along a circumference of a circle centered about the rotary shaft of the platen; and a derivation section that derives a depth of the groove from the measurement value of the measuring section.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Abstract: There is provide a technique that includes: etching a base on a surface of a substrate by performing a cycle a predetermined number of times, the cycle including: (a) forming a layer on a surface of the base by supplying a modifying agent to the base; and (b) causing a reaction between a halogen-containing radical and the base by supplying a halogen-containing gas to the layer such that the layer reacts with the halogen-containing gas to generate the halogen-containing radical.

Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, a molding member on the package substrate to cover at least a portion of the semiconductor chip, and a mechanical reinforcing member provided around the semiconductor chip within the molding member and extending in at least one direction.

Abstract: A wafer system-level fan-out packaging structure and a manufacturing method. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and an opposite second surface; providing a patch element, and bonding the patch element to the second surface; providing a die having a bump disposed on a front side, and bonding the front side of the die to the second surface of the redistribution layer through the bump; and forming a plastic packaging layer on the second surface of the redistribution layer, where the plastic packaging layer covers the patch element, back side and side surfaces of the die. In the wafer system-level fan-out packaging structure and the manufacturing method of the present disclosure, the die and the patch element are packaged in a plastic packaging layer, and the die and the patch element are connected and let out by the redistribution layer.

Abstract: A cleaning member mounting mechanism has: a cleaning member holding part, to which a cleaning member assembly having a cleaning member for cleaning a substrate W can be mounted; a member rotation part for rotating the cleaning member assembly held by the cleaning member holding part; and a moving part which moves the cleaning member holding part along an axial direction when the cleaning member assembly is removed, thereby to bring the cleaning member holding part into a rotation fixed position to restrict a rotation of the cleaning member holding part.

Abstract: Implementations of a packaging system may include a wafer; and a curvature adjustment structure coupled thereto where the curvature adjustment structure may be configured to alter a curvature of a largest planar surface of the wafer.

Abstract: A bonding apparatus includes a first holder, a second holder, an attracting pressure generator and a lift pin. The first holder is configured to hold a first substrate. The second holder, disposed at a position facing the first holder, has an attraction surface configured to attract a second substrate to be bonded to the first substrate. The attracting pressure generator is configured to generate an attracting pressure in the attraction surface. The lift pin is configured to space the second substrate on the attraction surface apart from the second holder. The second holder is provided with a space including an opening through which the lift pin passes, and the space is controlled to have a pressure lower than an atmospheric pressure.

Abstract: The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases.

Abstract: A protective member attaching apparatus includes a pressure reduction chamber having an upper housing and a lower housing, a support table that is provided inside the lower housing and on which a substrate is mounted, a sheet fixing section for fixing the sheet in such a manner as to partition the inside space of the pressure reduction chamber into a first space and a second space, a heating unit that heats the sheet to soften the sheet, and a control unit. The sheet fixing section has an outer periphery fixing section that fixes an outer periphery of the sheet, and a temporary fixing section that temporarily fixes a central portion of the sheet to the substrate mounted on a support table through a gap between the sheet and the substrate.

Abstract: A control device controls an operation of a processing apparatus for performing a processing in a processing container that accommodates a substrate. The control device includes: a temperature acquisition unit configured to acquire a temperature inside the processing container; a storage unit configured to store relationship information indicating a relationship between the temperature inside the processing container and an etching rate, and film thickness information including a cumulative film thickness of a deposited film inside the processing container; a rate calculator configured to calculate an etching rate of the deposited film based on the temperature acquired by the temperature acquisition unit and the relationship information stored in the storage unit; and a time calculator configured to calculate an etching time for removing the deposited film based on the etching rate calculated by the rate calculator and the film thickness information stored in the storage unit.

Abstract: A plasma discharge detection system detects undesirable plasma discharge events within a semiconductor process chamber. The plasma discharge detection system includes one or more cameras positioned around the semiconductor process chamber. The cameras capture images from within the semiconductor process chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharge within the semiconductor process chamber based on the images. The control system can adjust a semiconductor process in real time responsive to detecting the plasma discharge.

Abstract: Embodiments herein relate to a transport system and a substrate processing and transfer (SPT) system. The SPT system includes a transport system that connects two processing tools. The transport system includes a vacuum tunnel that is configured to transport substrates between the processing tools. The vacuum tunnel includes a substrate transport carriage to move the substrate through the vacuum tunnel. The SPT system has a variety of configurations that allow the user to add or remove processing chambers, depending on the process chambers required for a desired substrate processing procedure.

Abstract: A transfer apparatus including a frame, multiple arms connected to the frame, each arm having an end effector and an independent drive axis for extension and retraction of the respective arm with respect to other ones of the multiple arms, a linear rail defining a degree of freedom for the independent drive axis for extension and retraction of at least one arm, and a common drive axis shared by each arm and configured to pivot the multiple arms about a common pivot axis, wherein at least one of the multiple arms having another drive axis defining an independent degree of freedom with respect to other ones of the multiple arms.

Abstract: A semiconductor wafer transport apparatus having a transport arm and at least one end effector. An optical edge detection sensor is coupled to the transport arm and is configured so as to register and effect edge detection of a wafer supported by the end effector. An illumination source illuminates a surface of the wafer and is disposed with respect to the optical edge detection sensor so that the surface directs reflected surface illumination, from the illumination source, toward the optical edge detection sensor, and optically blanks, at the peripheral edge of the wafer, background reflection light of a background, viewed by the optical edge detection sensor coincident with linear traverse of the wafer supported by the at least one end effector. The peripheral edge of the wafer is defined in relief in image contrast to effect edge detection coincident with traverse of the wafer supported by the end effector.

Abstract: A substrate support includes an electrostatic chuck having an upper surface, and a cover positioned on the electrostatic chuck to cover the upper surface thereof. The cover includes a first face adjacent the upper surface of the electrostatic chuck, a second face for supporting a substrate, and one or more conduits extending through the cover to permit a cooling gas to flow from the second face to the first face. The cover is made from a dielectric material.

Abstract: Embodiments of a process kit are provided herein. In some embodiments, a process kit for use in a substrate processing chamber includes: a ceramic ring having an upper surface and a lower surface, wherein the ceramic ring includes a chucking electrode disposed in the ceramic ring and a heating element disposed in the ceramic ring; and an edge ring disposed on the ceramic ring.

Abstract: A substrate holding mechanism includes: a mounting stage on which a substrate is mounted; a plurality of holding sections each of which includes an upper surface that holds a lower surface of a peripheral section of the substrate and includes a lower surface that pushes down an upper surface of the peripheral section of the substrate mounted on the mounting stage; a protrusion that is provided on the plurality of holding sections and that contacts an end surface of the substrate mounted on the mounting stage to correct a position of the substrate; a lifting and lowering mechanism configured to lift and lower the plurality of holding sections; and a horizontal moving mechanism configured to horizontally move the plurality of holding sections.

Abstract: Apparatus and methods to process one or more wafers are described. A plurality of process stations are arranged in a circular configuration around a rotational axis. A support assembly with a rotatable center base defining a rotational axis, at least two support arms extending from the center base and heaters on each of the support arms is positioned adjacent the processing stations so that the heaters can be moved amongst the various process stations to perform one or more process condition.

Abstract: There is provided a semiconductor device including: an anode electrode that is provided on a front surface side of a semiconductor substrate; a drift region of a first conductivity type that is provided in the semiconductor substrate; a first anode region of a first conductivity type that is in Schottky contact with the anode electrode; and a second anode region of a second conductivity type that is different from the first conductivity type, in which the first anode region has a doping concentration lower than or equal to a doping concentration of the second anode region, and is spaced from the drift region by the second anode region.