Patents Issued in February 6, 2024
  • Patent number: 11894359
    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Mark T. Bohr, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. McCullough
  • Patent number: 11894360
    Abstract: A semiconductor device includes a slit pattern and a trench pattern disposed to extend substantially in parallel with each other in a first direction and channel plugs between the slit pattern and the trench pattern. The channel plugs include a first channel plug adjacent to the slit pattern. A top surface shape of the first channel plug is an elliptical shape. A long axis direction of the first channel plug and the first direction form an acute angle.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: February 6, 2024
    Assignee: SK hynix Inc.
    Inventor: Jang Won Kim
  • Patent number: 11894361
    Abstract: A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 6, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Sagarika Mukesh, Anthony I. Chou, Andrew M. Greene, Ruilong Xie, Veeraraghavan S. Basker, Junli Wang, Effendi Leobandung, Jingyun Zhang, Nicolas Loubet
  • Patent number: 11894362
    Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jing-Ying Chen
  • Patent number: 11894363
    Abstract: A semiconductor device includes: a doped well region of a first conductive type; M semiconductor components, the M semiconductor components being provided in the doped well region of the first conductive type and being arranged in the doped well region of the first conductive type in a first direction, M being a positive integer, each semiconductor component including a first doped region of a second conductive type and a doped region of a first conductive type, and the doped region of the first conductive type surrounding the first doped region of the second conductive type; and second doped regions of a second conductive type, the second doped regions of the second conductive type being provided on at least one side of the M semiconductor components in the first direction.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Patent number: 11894364
    Abstract: A semiconductor device has an off transistor (10) in which a gate electrode (3) and a source region (6) of an N-type MOS transistor are connected to a ground terminal and a drain region (5) is connected to an external signal terminal (100b). In the off transistor (10), the gate electrode (3) is extensively provided over a portion or entirety of the drain region (5) in addition to a channel region. A capacitance (C2) formed between the gate electrode (3) and the drain region (5) may be greater than a capacitance (C1) generated between the gate electrode (3) and a ground potential.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: February 6, 2024
    Assignee: ABLIC Inc.
    Inventor: Hiroaki Takasu
  • Patent number: 11894365
    Abstract: Multiple bipolar transistors are disposed side by side in the first direction on a substrate. Multiple first capacitance devices are provided corresponding to the respective base electrodes of the bipolar transistors. A radio frequency signal is supplied to the bipolar transistors through the first capacitance devices. Resistive devices are provided corresponding to the respective base electrodes of the bipolar transistors. A base bias is supplied to the bipolar transistors through the resistive devices. The first capacitance devices are disposed on the same side relative to the second direction orthogonal to the first direction, when viewed from the bipolar transistors. At least one of the first capacitance devices is disposed so as to overlap another first capacitance device partially when viewed in the second direction from the bipolar transistors.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 6, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shaojun Ma, Yasunari Umemoto, Kenji Sasaki
  • Patent number: 11894366
    Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: February 6, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Jonghae Kim, Milind Shah, Periannan Chidambaram
  • Patent number: 11894367
    Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11894368
    Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Sudipto Naskar, Biswajeet Guha, William Hsu, Bruce Beattie, Tahir Ghani
  • Patent number: 11894369
    Abstract: A semiconductor device including a substrate; gate structures spaced apart from each other on the substrate, each gate structure including a gate electrode and a gate capping pattern; source/drain patterns on opposite sides of the gate structures; first isolation patterns that respectively penetrate adjacent gate structures; and a second isolation pattern that extends between adjacent source/drain patterns, and penetrates at least one gate structure, wherein each first isolation pattern separates the gate structures such that the gate structures are spaced apart from each other, the first isolation patterns are aligned with each other, and top surfaces of the first and second isolation patterns are each located at a level the same as or higher than a level of a top surface of the gate capping pattern.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jun Kim, Hyungjin Park
  • Patent number: 11894370
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 11894371
    Abstract: Provided is an integrated circuit device including: a plurality of fin-type active regions protruding from a top surface of a substrate and extending in a first horizontal direction; at least one semiconductor layer, each including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions, wherein the lower semiconductor layer includes a same material as a material of the upper semiconductor layer, and wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongchan Suh, Dahye Kim
  • Patent number: 11894372
    Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron Lilak, Patrick Morrow, Anh Phan, Ehren Mannebach, Jack T. Kavalieros
  • Patent number: 11894373
    Abstract: A semiconductor device includes a substrate, a first transistor and a second transistor disposed on the substrate, and a first contact structure. The first transistor includes first semiconductor channel layers stacked and separated from one another, and a first source/drain structure and a second source/drain structure disposed at two opposite sides of and connected with each first semiconductor channel layer. The second transistor includes second semiconductor channel layers disposed above the first semiconductor channel layers, stacked, and separated from one another, and a third source/drain structure and a fourth source/drain structure disposed at two opposite sides of and connected with each second semiconductor channel layer. The first contact structure penetrates through the third source/drain structure.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: February 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11894374
    Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, an NMOS transistor, and a PMOS transistor. The NMOS transistor includes a first dielectric layer, a first work function layer, and a first conductive layer that are stacked in sequence. The PMOS transistor includes a second dielectric layer, a second work function layer, and a second conductive layer that are stacked in sequence.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Wenli Zhao, Jie Bai
  • Patent number: 11894375
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate includes an upper portion and a lower portion, and the first conductive line crosses the first gate between the upper portion and the lower portion.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11894376
    Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Won Ha, Byoung-Hak Hong
  • Patent number: 11894378
    Abstract: A semiconductor device includes a plurality of nano-channel field-effect transistor stacks positioned adjacent to each other such that source-drain regions are shared between adjacent nano-channel field-effect transistor stacks, each nano-channel field-effect transistor stack including at least two nano-channel field-effect transistors and corresponding source/drain regions vertically separated from each other.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: February 6, 2024
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Patent number: 11894379
    Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: February 6, 2024
    Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
  • Patent number: 11894380
    Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 6, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11894381
    Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Jung Chen, Tsung-Lin Lee, Chung-Ming Lin, Wen-Chih Chiang, Cheng-Hung Wang
  • Patent number: 11894382
    Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: February 6, 2024
    Assignees: STMicroelectronics France, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Weber, Christophe Lecocq
  • Patent number: 11894383
    Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pochun Wang, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11894384
    Abstract: A display apparatus can include a driving circuit on a device substrate, the driving circuit including a first thin film transistor and a second thin film transistor, a first insulating layer on the first thin film transistor and the second thin film transistor of the driving circuit, a second insulating layer on the first insulating layer, and a light-emitting device on the second insulating layer, the light-emitting device being electrically connected to the second thin film transistor of the driving circuit. Each of the first thin film transistor and the second thin film transistor includes an oxide semiconductor pattern and a gate electrode overlapping a portion of the oxide semiconductor pattern. The gate electrode has a stacked structure of a first hydrogen barrier layer and a low-resistance electrode.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: February 6, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Ki-Tae Kim, So-Young Noh, Ui-Jin Chung, Kyeong-Ju Moon, Hyuk Ji
  • Patent number: 11894385
    Abstract: An electronic device includes a flexible substrate and a driving component. In the flexible substrate, a first side region, a second side region and a first cutting structure are disposed in a peripheral region, wherein a display region and the first side region are separated by a first edge of the display region, the display region and the second side region are separated by a second edge of the display region, the first edge and the second edge are respectively parallel to a first direction and a second direction perpendicular to the first direction, the first cutting structure has a first endpoint and two edges separated by the first endpoint and respectively belonging to the first side region and the second side region. The driving component overlaps the flexible substrate in a top view direction perpendicular to the first direction and the second direction.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: February 6, 2024
    Assignees: HannStar Display (Nanjing) Corporation, HANNSTAR DISPLAY CORPORATION
    Inventor: Yen-Chung Chen
  • Patent number: 11894386
    Abstract: An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate includes an active layer, a metal contact layer, a gate insulating layer, a gate layer, a source/drain layer, and a pixel electrode, which are sequentially disposed on a substrate. An insulating area of the metal contact layer corresponds to a channel area of the active layer, and a conductive area of the metal contact layer is disposed at two sides of the insulating area. A source and a drain of the source/drain layer are individually connected to the conductive area. Therefore, a problem of relatively high electrical resistance of a conductorized IGZO area in conventional TFT devices can be solved.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 6, 2024
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Peng Zhang
  • Patent number: 11894387
    Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 6, 2024
    Assignee: Japan Display Inc.
    Inventors: Hajime Watakabe, Toshihide Jinnai, Ryo Onodera, Akihiro Hanada
  • Patent number: 11894388
    Abstract: The application discloses a method adapted to manufacture an array substrate and a display panel. The method includes: forming a photoresist layer, a source and a drain; post-baking the photoresist layer, so that the photoresist layer flows to the position of a channel; etching a semiconductor layer to obtain a preset pattern; and peeling off the photoresist layer.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: February 6, 2024
    Assignee: HKC CORPORATION LIMITED
    Inventor: Bei Zhou Huang
  • Patent number: 11894389
    Abstract: Provided is a display substrate, a method for preparing the same, and a display device. The display substrate includes a pad bending region. In the pad bending region, the display substrate includes a base, and an inorganic insulating layer and a metal layer laminated on the base. The metal layer includes a plurality of discrete metal wires. The inorganic insulating layer includes a plurality of discrete first inorganic insulating layers, each of which is arranged between each of the plurality of discrete metal wires and the base.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: February 6, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Wang, Zhifeng Zhan, Yanxin Wang, Shuquan Yang, Jiafan Shi, Peng Huang
  • Patent number: 11894390
    Abstract: A display substrate and a manufacturing method thereof and a display panel are disclosed. The display substrate includes a base substrate, a connection electrode, a conductive sealant, a plurality of via-holes respectively in different layers and a bridge electrode. The connection electrode is on the base substrate; the conductive sealant is at a side, away from the base substrate, of the connection electrode and is electrically connected with the connection electrode via the plurality of via-holes respectively in different layers; the bridge electrode is at least partially in at least one via-hole of the plurality of via-holes, and is electrically connected with the connection electrode and the conductive sealant; in a direction perpendicular to the base substrate, the plurality of via-holes are at least partially not overlapped with each other.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 6, 2024
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yutong Yang, Zhonghao Huang, Zhiyong Ning, Kai Wang, Rui Wang
  • Patent number: 11894391
    Abstract: A contact resistance monitoring device, a manufacturing method thereof, and a display panel are provided. The contact resistance monitoring device includes a substrate, a gate metal layer disposed on the substrate, an interlayer dielectric layer disposed on the substrate, a source and drain metal layers disposed in the recessed hole of the interlayer dielectric layer, and a pixel electrode layer disposed on the interlayer dielectric layer and the source and drain metal layer.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: February 6, 2024
    Inventor: Xiaohui Nie
  • Patent number: 11894392
    Abstract: A transparent display device is disclosed, which may have high light transmittance in a non-display area as well as a display area, and may increase or maximize a light emission area in a non-transmissive area. The transparent display device comprises a substrate provided with a display area, in which a plurality of subpixels are disposed, and a non-display area adjacent to the display area, anode electrodes provided in each of the plurality of subpixels over the substrate, a light emitting layer provided over the anode electrodes, a cathode electrode provided over the light emitting layer, a pixel power line provided over the substrate and extended in the display area in a first direction, and a common power line provided over the substrate and extended in the display area in the first direction. The display area includes a non-transmissive area provided with the common power line and the pixel power line, and a transmissive area provided between the common power line and the pixel power line.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: February 6, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: EuiTae Kim, KiSeob Shin
  • Patent number: 11894393
    Abstract: An embodiment of the present invention provides a display device including a substrate and a transistor on the substrate. The transistor includes: a lower layer having conductivity and including a body portion and a plurality of protrusions; an oxide semiconductor layer including a channel region, a first conductive region disposed at a first side of the channel region, and a second conductive region disposed at a second side of the channel region, where the second side is opposite the first side; a gate electrode overlapping the channel region in a plan view; a first electrode electrically connected to the first conductive region; and a second electrode electrically connected to the second conductive region. The plurality of protrusions protrudes from the body portion, and the body portion overlaps the channel region in the plan view.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: February 6, 2024
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
    Inventors: Hye Lim Choi, Saeroonter Oh, Kihwan Kim, Joon Seok Park, Ji Hwan Lee, Jun Hyung Lim
  • Patent number: 11894394
    Abstract: An array substrate, a method for preparing the array substrate, and a backlight module are disclosed. Before electroplating a first metal layer on a pattern of a seed layer, the method further includes: forming a pattern of a compensation electrode wire electrically connected with a lead electrode on a side, where the lead electrode is formed, of a base substrate. The compensation electrode wire is at least on a second side of a wiring region, the pattern of the lead electrode is formed at a first side of the wiring region, and the first side and the second side are different sides. In the electroplating process, the lead electrode is connected with a negative pole of a power supply, the compensation electrode wire is electrically connected with the lead electrode, thus an area of an electroplating negative pole generating electric field lines is increased by utilizing the compensation electrode wire.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: February 6, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zhanfeng Cao, Yingwei Liu, Ke Wang, Guocai Zhang, Jianguo Wang, Zhiwei Liang, Haixu Li, Muxin Di
  • Patent number: 11894395
    Abstract: A display device includes a substrate including a display area and a non-display area driving circuits disposed in the non-display area; first voltage wirings and second voltage wirings extending from the display area to the non-display area; and a first auxiliary wiring electrically connected to the first voltage wirings and a second auxiliary wiring electrically connected to the second voltage wirings, the first auxiliary wiring and the second auxiliary wiring being electrically connected to the driving circuit, wherein the first voltage wirings electrically connected to an odd-numbered driving circuit among the driving circuits are electrically connected to the first auxiliary wiring through a first connection wiring, and the second voltage wirings electrically connected to an even-numbered driving circuit among the driving circuits are electrically connected to the second auxiliary wiring through a second connection wiring.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Yeon Kyung Kim
  • Patent number: 11894396
    Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 6, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai
  • Patent number: 11894397
    Abstract: A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: February 6, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuichi Sato, Hitoshi Nakayama
  • Patent number: 11894398
    Abstract: A photodetector, includes a photosensitive layer, a thin film transistor, and a sensing electrode, the sensing electrode connected to one of source/drain electrodes of the thin film transistor to transmit a signal generated by the photosensitive layer to the thin film transistor; wherein the photodetector further is a hydrogen barrier layer which is disposed between the photosensitive layer and the thin film transistor and is configured to inhibit hydrogen of the photosensitive layer from entering the thin film transistor. A method of manufacturing a photodetector is further provided.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: February 6, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Jiangbo Chen, Fanli Meng, Fan Li, Shuo Zhang, Da Li, Zeyuan Li, Yanzhao Li
  • Patent number: 11894399
    Abstract: Hyperspectral resonant cavity imaging spectrometers and imaging systems incorporating the resonant cavity spectrometers are provided. The spectrometers include an array of photodetectors based on photosensitive semiconductor nanomembranes disposed between two dielectric spacers, each of the dielectric spacers having a thickness gradient along a lateral direction, such that the resonant cavity height differs for different photodetectors in the array.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: February 6, 2024
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Zhenyang Xia, Ming Zhou, Qiaoqiang Gan, Zongfu Yu
  • Patent number: 11894400
    Abstract: An imaging system includes an illumination unit and a sensor unit disposed on a printed circuit board. The illumination unit includes a diode laser source inside an illumination housing. The sensor unit includes an image sensor having a pixel array and a lens barrel mounted on the image sensor with an adhesive, and an optical fiber coupled between the illumination housing and image sensor. The optical fiber is configured to collect a portion of light from the interior of the illumination housing that is emitted by the diode laser source and direct the portion of light to a corner of the pixel array of the image sensor that is located outside the lens barrel.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: February 6, 2024
    Assignee: Magic Leap, Inc.
    Inventors: Erez Tadmor, David Cohen, Giora Yahav
  • Patent number: 11894401
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an image sensor, the method includes forming a first photodetector and a second photodetector in a substrate. An isolation structure is formed in the substrate between the first photodetector and the second photodetector. A readout transistor is formed over the isolation structure. The readout transistor includes a first sidewall directly over the first photodetector and a second sidewall directly over the second photodetector. A height of the readout transistor from the first sidewall to the second sidewall is constant.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Seiji Takahashi
  • Patent number: 11894402
    Abstract: An imaging device according to the embodiments of the present disclosure has a display including a wiring layer; a camera located at a back side of the display, the camera including an optical lens and an imaging sensor to sense the light through the display to create an image; an optical element between the display and the camera, wherein the optical element filters the light through the display and passes the filtered light to the camera, and the optical element reduces a diffraction due to the wiring layer.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: February 6, 2024
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Hirotake Cho
  • Patent number: 11894403
    Abstract: A semiconductor package including a semiconductor chip on a package substrate, a transparent substrate on the semiconductor chip, an attachment dam between the semiconductor chip and the transparent substrate, the attachment dam extending along an edge of the semiconductor chip, a first molding layer on the package substrate and surrounding a side surface of the semiconductor chip and including a first epoxy resin, and a second molding layer on the package substrate and filling a space between the semiconductor chip and the first molding layer and including a second epoxy resin. The first epoxy resin includes a first filler containing at least one of silica or alumina. The second epoxy resin includes a second filler containing at least one of silica or alumina. The content of the second filler in the second epoxy resin is greater than a content of the first filler in the first epoxy resin.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: February 6, 2024
    Inventor: Dong Kwan Kim
  • Patent number: 11894404
    Abstract: The present disclosure provides an optical structure and a method for fabricating an optical structure, the method includes forming a light detection region in a substrate, forming an isolation structure at surrounding the light detection region, and forming a primary grid over the isolation structure, including forming a metal layer over the isolation structure, forming a first dielectric layer over the metal layer, and partially removing the metal layer and the first dielectric layer with a first mask by patterning, and forming a secondary grid at least partially surrounded by the primary grid laterally.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yun-Hao Chen, Kuo-Yu Wu, Tse-Hua Lu
  • Patent number: 11894405
    Abstract: An image sensor package includes a package substrate; an image sensor chip disposed on the package substrate; a dam structure disposed on the image sensor chip and including a dam main body having an opening and a first light absorption layer disposed on an inner wall of the dam main body; a transparent substrate on the dam structure; and an encapsulant contacting the image sensor chip and an outer wall of the dam main body.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyongsoon Cho
  • Patent number: 11894406
    Abstract: A solid-state imaging device includes a semiconductor layer on which a plurality of pixels are arranged along a light-receiving surface being a main surface of the semiconductor layer, photoelectric conversion units provided for the respective pixels in the semiconductor layer, and a trench element isolation area formed by providing an insulating layer in a trench pattern formed on a light-receiving surface side of the semiconductor layer, the trench element isolation area being provided at a position displaced from a pixel boundary between the pixels.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: February 6, 2024
    Assignee: Sony Group Corporation
    Inventor: Hiromi Okazaki
  • Patent number: 11894407
    Abstract: Provided are an imaging apparatus and an electronic device in which even if an image sensor is mounted on a wiring board, the wiring board on which the image sensor is mounted can be assembled to a housing with high accuracy. Provided is an imaging apparatus including a sensor chip and a wiring board having a glass base material. The imaging apparatus is joined to at least one of the sensor chip or the wiring board via a bump unit including a plurality of bumps, and each of the plurality of bumps is formed by conductive members having substantially the same composition.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 6, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Susumu Hogyoku
  • Patent number: 11894408
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • Patent number: 11894409
    Abstract: In some example embodiments, a back side illumination (BSI) image sensor may include a pixel configured to generate electrical signals in response to light incident on a back side of a substrate. In some example embodiments, the pixel includes, a photodiode, a device isolation film adjacent to the photodiode, a dark current suppression layer above the photodiode, a light shield grid above the photodiode and including an opening area of 1 to 15% of an area of the pixel, a light shielding filter layer above the light shield grid, a planarization layer above the light shielding filter layer, a lens above the planarization layer, and/or an anti-reflective film between the photodiode and the lens.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: February 6, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun Ki Lee, Jong Hoon Park, Jun Sung Park