Abstract: Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.

Abstract: A method includes forming a plurality of openings extending into a substrate from a front surface of the substrate. The substrate includes a first semiconductor material. Each of the plurality of openings has a curve-based bottom surface. The method includes filling the plurality of openings with a second semiconductor material. The second semiconductor material is different from the first semiconductor material. The method includes forming a plurality of pixels that are configured to sense light in the plurality of openings, respectively, using the second semiconductor material.

Abstract: A display device includes a substrate having an emission area and a non-emission area, a first electrode and a second electrode spaced from each other on the substrate in the emission area, a first insulating layer on the substrate in the emission area and the non-emission area and covering at least a portion of the first electrode and the second electrode, a light-emitting element between the first electrode and the second electrode, a first contact electrode on the first electrode and in contact with one end portion of the light-emitting element, and a second contact electrode on the second electrode and in contact with the other end portion of the light-emitting element, a first active material layer on the first insulating layer in the non-emission area and electrically connected to the first contact electrode, and a gate insulating layer on the first active material layer.

Abstract: A method for manufacturing an optoelectronic device including the steps of forming a substrate having a support face; forming a first series of first areas adapted to the formation of all or part of light-emitting diodes, forming a second series of second areas on the support face, adapted to the formation of light confinement wall elements capable of forming a light confinement wall, the second areas defining therebetween sub-pixel areas; forming, from the first areas, light-emitting diodes; forming, by the same technique as in the previous step, from the second areas, light confinement wall elements, concomitantly with all or part of the light-emitting diodes which are formed in the previous step.

Abstract: A display device may include a substrate including pixels; a first bank that defines an emission area of the pixels; a first electrode and a second electrode spaced apart from each other in the emission area; a first insulating layer disposed on the first electrode and the second electrode; light emitting elements disposed on the first insulating layer between the first electrode and the second electrode; a second insulating layer disposed on the first bank; a first opening passing through the first insulating layer; and a second opening passing through the second insulating layer. The first opening and the second opening may overlap the first bank.

Abstract: A display device is provided. The display device includes a first electrode including a first electrode surface extending in a first direction and a second electrode surface connected to one end of the first electrode surface and extending in a second direction that is different from the first direction, a second electrode including a third electrode surface extending in the first direction and spaced apart from the first electrode surface and facing the first electrode surface, and a fourth electrode surface extending in the second direction and spaced apart from the second electrode surface and facing the second electrode surface, and at least one light emitting element between the first electrode and the second electrode and including a first light emitting element between the first electrode surface and the third electrode surface and a second light emitting element between the second electrode surface and the fourth electrode surface.

Abstract: A display device includes a substrate includes a first emitter and a second emitter thereon. The first emitter includes a first lower active quantum well (QW) region that has a first emission spectrum spanning a first spectral range. The second emitter includes (i) an upper active QW region that has a second emission spectrum spanning a second spectral range that is distinct from the first spectral range, (ii) a second lower active QW region having the first emission spectrum and being located between the upper active QW region and the substrate, and (iii) a barrier layer between the second lower active QW region and the upper active QW region for suppressing emission of the second lower active QW region.

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Abstract: A semiconductor structure, a preparation method of the same, and a semiconductor device are provided. The semiconductor structure includes a substrate, including an active area. A first electrode layer is arranged on the substrate and electrically connected to the active area. The first electrode layer extends in a direction perpendicular to the substrate. A dielectric layer is arranged on a surface of the first electrode layer. A second electrode layer is arranged on a surface of the dielectric layer. Each of the surface of the first electrode layer and the surface of the dielectric layer are provided with an uneven structure.

Abstract: The present application relates to a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.

Abstract: A memory formation method includes: providing a substrate; forming a first mask layer on the substrate, in the first mask layer there being formed a plurality of parallel-arranged strip-shaped patterns positioned above the array area, and an end of each of the strip-shaped patterns being connected to the first mask layer on the peripheral area of the substrate; forming a second mask layer on the first mask layer, in the second mask layer there being formed a plurality of first patterns; and etching layer by layer by using the second mask layer and the first mask layer as masks to transfer the strip-shaped patterns and the first patterns into the substrate to form the discrete active areas arranged in an array.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: A gate-controlled diode includes a substrate, a gate stacked on the substrate, a gate insulation layer, a first two-dimensional semiconductor layer, a second two-dimensional semiconductor layer, a source, and a drain disposed separately from the source. The gate is embedded in a surface of the substrate, and the gate insulation layer covers the surface of the substrate in which the gate is disposed. The first two-dimensional semiconductor layer is stacked on the gate insulation layer, a portion of the second two-dimensional semiconductor layer is stacked on the gate insulation layer, another portion is stacked on the first two-dimensional semiconductor layer. The another portion of the second two-dimensional semiconductor layer stacked on the first two-dimensional semiconductor layer forms a heterojunction. An orthographic projection of the heterojunction onto the substrate is in an orthographic projection of the gate onto the substrate.

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

Abstract: Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: Provided is a semiconductor device including: a semiconductor substrate including a bulk donor; and a first buffer region of a first conductivity type, the first buffer region being provided on a lower surface side of the semiconductor substrate and having one or more doping concentration peaks and one or more hydrogen concentration peaks in a depth direction of the semiconductor substrate, in which a doping concentration at a shallowest concentration peak, out of the doping concentration peaks of the first buffer region, closest to the lower surface of the semiconductor substrate is 50 times as high as a concentration of the bulk donor of the semiconductor substrate or lower. The doping concentration at the shallowest concentration peak may be lower than a reference carrier concentration obtained when current that is 1/10 of rated current flows between an upper surface and the lower surface of the semiconductor substrate.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a surface. The surface has a first portion and a second portion protruding from the first portion. The semiconductor device also includes a dielectric layer disposed on the second portion and a gate conductive layer disposed on the dielectric layer.

Abstract: The present invention relates to a silicon carbide semiconductor device that includes a Schottky barrier diode in a field-effect transistor and includes a first trench provided through first and second semiconductor regions in a thickness direction and reaches inside a semiconductor layer, a second trench provided through the second semiconductor region in the thickness direction and reaches inside the semiconductor layer, a gate electrode embedded in the first trench via a gate insulating film, a Schottky barrier diode electrode embedded in the second trench, a first low-resistance layer having contact with a trench side wall of the first trench, and a second low-resistance layer having contact with a trench side wall of the second trench. The second low-resistance layer has an impurity concentration that is higher than the impurity concentration in the semiconductor layer and lower than the impurity concentration in the first low-resistance layer.

Abstract: Methods for producing the amorphous metal oxide semiconductor layer where amorphous metal oxide semiconductor layer is formed by use of a precursor composition containing a metal salt, a primary amide, and a water-based solution. The methodology for producing the amorphous metal oxide semiconductor layer includes applying the precursor composition onto a substrate to form a precursor film, and firing the film at a temperature of 150° C. or higher and lower than 300° C.

Abstract: A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.

Abstract: The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.

Abstract: Various embodiments provide a vertical-conduction semiconductor device that includes: a silicon substrate having a front face and a rear face; a front-side structure arranged on the front face of the substrate, having at least one current-conduction region at the front face; and a back side metal structure, arranged on the rear face of the substrate, in electrical contact with the substrate and constituted by a stack of metal layers. The back side metal structure is formed by: a first metal layer; a silicide region, interposed between the rear face of the substrate and the first metal layer and in electrical contact with the aforesaid rear face; and a second metal layer arranged on the first metal layer.

Abstract: A stacked semiconductor device comprising a lower source/drain epi located on top of a bottom dielectric layer. An isolation layer located on top of the lower source/drain epi and an upper source/drain epi located on top of the isolation layer. A lower electrical contact that is connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi.

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer. The first electrode is a conformal layer covers the semiconductor barrier layer and the dielectric layer.

Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.

Abstract: A CFET (complementary field effect transistor) structure including a substrate, a first CFET formed above the substrate, and a second CFET formed above the substrate. The first CFET includes a top FET and a bottom FET. The top FET and bottom FET of the first CFET include at least one nanosheet channel. A gate affiliated with the first CFET and the second CFET devices includes a continuous horizontal dielectric over the entire length of the gate. The top FET of each CFET has a first polarity. The bottom FET of each a CFET comprises a second polarity. The top FET of the first CFET includes a first work function metal, and the top FET of the second CFET includes a second work function metal.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

Abstract: Disclosed a silicon carbide MOSFET device and manufacturing method thereof. The method includes: forming a patterned first barrier layer on an upper surface of the substrate; forming a base region of a second doping type extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask; forming a source region of the first doping type in the substrate; forming a contact region of the second doping type in the substrate; and forming a gate structure, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer. The method of the present disclosure not only reduces one photoetching process and saves cost, but also realizes a short channel and reduces an on-resistance of the device.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

Abstract: Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

Abstract: A method of making a semiconductor device includes depositing a TiN layer over a substrate. The method further includes doping a first portion of the TiN layer using an oxygen-containing plasma treatment. The method further includes doping a second portion of the TiN layer using a nitrogen-containing plasma treatment, wherein the second portion of the TiN layer directly contacts the first portion of the TiN layer. The method further includes forming a first metal gate electrode over the first portion of the TiN layer. The method further includes forming a second metal gate electrode over the second portion of the TiN layer, wherein the first metal gate electrode has a different work function from the second metal gate electrode, and the second metal gate electrode directly contacts the first metal gate electrode.

Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.

Abstract: A method for manufacturing a semiconductor device includes: implanting a P-type impurity from a region where the first conductor film is formed toward an inside of the semiconductor substrate with a first acceleration energy; forming a nitride film provided with a first opening on the first conductor film; forming an insulating film with a second opening from which the first conductor film is exposed; forming a second conductor film to fill the second opening of the insulating film; removing the nitride film and a portion of the first conductor film positioned below the nitride film to expose the oxide film in a peripheral area of a formation region of the insulating film; and implanting the P-type impurity from a region from which the oxide film is exposed toward an inside of the semiconductor substrate with a second acceleration energy smaller than the first acceleration energy.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: Heterostructures include a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions.

Abstract: A disclosed structure includes a bipolar junction transistor (BJT) and a method of forming the structure. The structure includes a semiconductor layer on an insulator layer. The BJT includes a base region positioned laterally between emitter and collector regions. The emitter region includes an emitter portion of the semiconductor layer and an emitter semiconductor layer, which is within an emitter cavity in the insulator layer, which extends through an emitter opening in the emitter portion, and which covers the top of the emitter portion. The collector region includes a collector portion of the semiconductor layer and a collector semiconductor layer, which is within a collector cavity in the insulator layer, which extends through a collector opening in the collector portion, and which covers the top of the collector portion. Optionally, the structure also includes air pockets within the emitter and collector cavities.

Abstract: A semiconductor device includes first and second source/drain regions, a core channel region, a barrier layer, a shell, and a gate stack. The core channel region is between the first and second source/drain regions and is doped with first dopants. The barrier layer is between the core channel region and the second source/drain region and is doped with second dopants. The shell is over the core channel region and the barrier layer. The gate stack is over the shell.

Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer; an insulating layer; a first region disposed between the nitride semiconductor layer and the insulating layer and containing at least one element of hydrogen and deuterium; and a second region disposed in the nitride semiconductor layer, adjacent to the first region, and containing fluorine.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a gate dielectric layer on the barrier layer; forming a work function metal layer on the gate dielectric layer; patterning the work function metal layer and the gate dielectric layer; forming a gate electrode on the work function metal layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: In a general aspect, a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) can include a substrate of a first conductivity type, a drift region of the first conductivity type disposed on the substrate, a spreading layer of the first conductivity type disposed in the drift region, a body region of a second conductivity type disposed in the spreading layer, and a source region of the first conductivity type disposed in the body region. The SiC MOSFET can also include a gate structure that includes a gate oxide layer, an aluminum nitride layer disposed on the gate oxide layer, and a gallium nitride layer of the second conductivity disposed on the aluminum nitride layer.

Abstract: A precursor for a vertical semiconductor device is provided with a substrate, a drift region over the substrate, and an upper precursor region over the drift region. The top surface of the precursor is substantially planar, and the substrate and the drift region are doped with a first dopant of a first polarity. In a first embodiment, a series of implants with a second dopant is provided in the upper precursor region via the top surface to form each of at least two gate regions such that each implant of the series of implants is provided at a different depth below the top surface. In a second embodiment, a series of implants with the first dopant is provided in the upper precursor region via the top surface to form a channel region that has at least a portion between two gate regions.

Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

Abstract: Disclosed is a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a drift region on a substrate, a well region on the drift region, a source-end doped region in the well region, a drain-end doped region on the drift region, and a gate structure which is located between a source end and a drain end, located at a position of the well region, and forms a channel region in the well region. The source-end doped region comprises a first doped region and a second doped region with opposite doping types, the channel region connects the first doped region and the drift region. The first doped region and the second doped region of the source end are equivalently close to the gate structure, a distance between the second doped region and a PN junction surface formed by the drift region and the well region is reduced.

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.