Patents Issued in February 6, 2024
  • Patent number: 11894460
    Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11894461
    Abstract: A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Pi Chang, Yen-Tien Tung, Dawei Heh, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Tzer-Min Shen, Huang-Lin Chao
  • Patent number: 11894462
    Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 6, 2024
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
  • Patent number: 11894463
    Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungmin Song, Bongseok Suh, Junggil Yang, Soojin Jeong
  • Patent number: 11894464
    Abstract: A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 11894465
    Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: February 6, 2024
    Assignee: Google LLC
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 11894466
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, and a conductive layer; the first insulating layer, the metal oxide layer, and the conductive layer are stacked in this order over the semiconductor layer; an end portion of the first insulating layer is located inward from an end portion of the semiconductor layer; an end portion of the metal oxide layer is located inward from the end portion of the first insulating layer; and an end portion of the conductive layer is located inward from the end portion of the metal oxide layer. The second insulating layer is preferably provided to cover the semiconductor layer, the first insulating layer, the metal oxide layer, and the conductive layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 6, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Rai Sato, Masami Jintyou, Masayoshi Dobashi, Takashi Shiraishi, Satoru Saito, Yasutaka Nakazawa
  • Patent number: 11894467
    Abstract: The present application discloses a doped metal oxide semiconductor which is an indium tin oxide or indium tin zinc oxide semiconductor doped with a rare earth oxide. Even at a small doping amount, the oxygen vacancies could be suppressed as well as the mobility be maintained; critically, the thin-films made thereof can avoid the influence of light on I-V characteristics and stability, which results in great improvement of the stability under illumination of metal oxide semiconductor devices. The present application also discloses the thin-film transistors made thereof the doped metal oxide semiconductor and its application.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 6, 2024
    Assignee: South China University of Technology
    Inventors: Miao Xu, Hua Xu, Weijing Wu, Weifeng Chen, Lei Wang, Junbiao Peng
  • Patent number: 11894468
    Abstract: Described herein are the design and fabrication of Group III trioxides, such as ?-Ga2O3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the requirements unique to Group III trioxides, such as ?-Ga2O3.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 6, 2024
    Assignee: Cornell University
    Inventors: Wenshen Li, Zongyang Hu, Kazuki Nomoto, Debdeep Jena, Huili Grace Xing
  • Patent number: 11894469
    Abstract: A resonant tunneling device includes a first two-dimensional semiconductor layer including a first two-dimensional semiconductor material, a first insulating layer on the first two-dimensional semiconductor layer; and a second two-dimensional semiconductor layer on the first insulating layer and including a second two-dimensional semiconductor material of a same kind as the first two-dimensional semiconductor material.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: February 6, 2024
    Assignees: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghyun Jo, Heejun Yang, Hyeonjin Shin, Shoujun Zheng
  • Patent number: 11894470
    Abstract: An optical sensor includes a substrate, a photoelectric element disposed on the substrate and that includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a barrier layer disposed on the second electrode, an insulating layer that covers the photoelectric element and the barrier layer, and a bias electrode disposed on the insulating layer and electrically connected to the second electrode. The barrier layer is spaced apart from the first electrode.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki June Lee, Jung Ha Son, Tae Sung Kim, Jae Ik Lim, Hyun Min Cho
  • Patent number: 11894471
    Abstract: Provided are a photoelectric chip, a manufacturing method and an installation method, which relate to the field of optical communication and transmission technologies. The chip is provided with a light-splitting groove (3), and the light-splitting groove (3) runs through an absorption layer (2) of the chip; the back of the chip is a light-entering side; the light-splitting groove (3) is configured to transmit and split out part (151) of incident light (15), and the other part (152) of the incident light (15) enters the absorption layer (2) for photovoltaic conversion. The photoelectric chip can split light and monitor optical power of the incident light.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: February 6, 2024
    Assignee: PHOGRAIN TECHNOLOGY (SHENZHEN) CO., LTD.
    Inventors: Yanwei Yang, Ying Li, Hongliang Liu, Ge Liu, Yan Zou
  • Patent number: 11894472
    Abstract: Approaches for fabricating foil-based metallization of solar cells based on a leave-in etch mask, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a back surface and an opposing light-receiving surface. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the back surface of the substrate. A conductive contact structure is disposed on the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes metal foil portions in alignment with corresponding ones of the alternating N-type and P-type semiconductor regions. A patterned wet etchant-resistant polymer layer is disposed on the conductive contact structure. Portions of the patterned wet etchant-resistant polymer layer are disposed on and in alignment with the metal foil portions.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 6, 2024
    Assignee: Maxeon Solar Pte. Ltd.
    Inventors: Richard Hamilton Sewell, David Fredric Joel Kavulak, Taeseok Kim, Gabriel Harley
  • Patent number: 11894473
    Abstract: The invention relates to a sensing module and a manufacturing method thereof, which firstly provides a transparent substrate, and then a sensor, a colloid, and an optical cover body disposed on a first surface of the transparent substrate. The colloid is surrounded the encrypted chip and is connected with the transparent substrate and the optical cover. Finally, a light source irradiates the colloid through a second surface of the transparent substrate to cure the colloid for obtaining the sensing module.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: February 6, 2024
    Inventors: Ruei Chi Chen, Chih Lin Yang
  • Patent number: 11894474
    Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment the optoelectronic system comprises a board, and a carrier attached to the board. In an embodiment, a first die is on the carrier. In an embodiment, the first die is a photonics die, and a surface of the first die is covered by an optically transparent layer.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Priyanka Dobriyal, Ankur Agrawal, Susheel Jadhav, Quan Tran, Raghuram Narayan, Raiyomand Aspandiar, Kenneth Brown, John Heck
  • Patent number: 11894475
    Abstract: Embodiments of the present disclosure provide a spin-qubit quantum magnetometer and radar apparatus, entirely implemented in silicon and with full electrical control. By default, each detection element of the silicon-based spin-qubit quantum magnetometer and radar apparatus with full electrical control of the invention is built around a Field Effect Transistor (FET) on silicon over insulator with a back-gate as well as two front gates, which can be adjacent to one another along the Drain-Source FET channel or alternatively placed across that same channel and facing each other as corner gates.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: February 6, 2024
    Inventor: Pierre Gandolfo
  • Patent number: 11894476
    Abstract: There is provided a transparent semiconductor substrate and a method for manufacturing same includes a semiconductor substrate including a first surface and a second surface opposite to the first surface; and a through-hole penetrating the semiconductor substrate, wherein the through-hole includes an inclined portion inclined with respect to the first surface and second surface.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 6, 2024
    Assignee: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Kwan Yong Seo, Kang Min Lee
  • Patent number: 11894477
    Abstract: An electrical device includes a substrate with a compressive layer, a neutral stress buffer layer and a tensile stress compensation layer. The stress buffer layer and the stress compensation layer may each be formed with aluminum nitride using different processing parameters to provide a different intrinsic stress value for each layer. The aluminum nitride tensile layer is configured to counteract stresses from the compressive layer in the device to thereby control an amount of substrate bow in the device. This is useful for protecting fragile materials in the device, such as mercury cadmium telluride. The aluminum nitride stress compensation layer also can compensate for forces, such as due to CTE mismatches, to protect the fragile layer. The device may include temperature-sensitive materials, and the aluminum nitride stress compensation layer or stress buffer layer may be formed at a temperature below the thermal degradation temperature of the temperature-sensitive material.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: February 6, 2024
    Assignee: Raytheon Company
    Inventors: Andrew Clarke, Emily Thomson, Michael Rondon
  • Patent number: 11894478
    Abstract: A flexible assembly with a stainless steel mesh packaging structure includes a flexible back plate, a first hot melt adhesive, a solar cell string, a stainless steel mesh, a second hot melt adhesive, and a flexible front plate. The flexible back plate and the flexible front plate are respectively arranged on the outer surface of the first hot melt adhesive and the outer surface of the second hot melt adhesive, and the solar cell string and the stainless steel mesh are arranged between the first hot melt adhesive and the second hot melt adhesive. The stainless steel mesh is arranged at partial or all positions around the outer edge of the solar cell string and is continuously distributed or separately distributed. The stainless steel mesh is arranged around the solar cell string to further strengthen the strength of the flexible assembly and improve the tearing resistance of the flexible assembly.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: February 6, 2024
    Assignee: GOLDEN SOLAR (QUANZHOU) NEW ENERGY TECHNOLOGY CO., LTD.
    Inventor: Hsin-Wang Chiu
  • Patent number: 11894479
    Abstract: The present invention provides a photosensitive element, and a preparation method and a display device thereof. The photosensitive element includes a substrate; a first electrode arranged on the substrate; an N-type doped silicon layer arranged on the first electrode; an undoped silicon layer arranged on the N-type doped silicon layer; a molybdenum oxide layer arranged on the undoped silicon layer; an insulating layer arranged on the molybdenum oxide layer and the substrate, wherein a first opening is arranged on the insulating layer to expose the molybdenum oxide layer; and a second electrode arranged on the insulating layer and the molybdenum oxide layer, wherein the second electrode contacts the molybdenum oxide layer through the first opening.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: February 6, 2024
    Inventor: Guangshuo Cai
  • Patent number: 11894480
    Abstract: Germanium (Ge)-Silicon (Si) structures, optoelectronic devices and method for forming same. A structure comprises a Si substrate, a Ge seed layer and a Ge epitaxial layer separated by respective interfaces that share a common plane normal, wherein the Si substrate and the Ge seed layer have a same first doping type with a first doping level, and a locally doped region formed in the Si layer adjacent to the Ge seed layer and having a second doping type with a second doping level, wherein the locally doped region is designed to reduce leakage currents between the Si substrate and the Ge epitaxial layer when an electrical bias is applied to the structure.
    Type: Grant
    Filed: May 4, 2019
    Date of Patent: February 6, 2024
    Assignee: TriEye Ltd.
    Inventors: Eran Katzir, Vincent Immer, Omer Kapach, Avraham Bakal, Uriel Levy
  • Patent number: 11894481
    Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body having a topmost surface; a first light-emitting device disposed on the carrier body and having a light-emitting surface; and a light-receiving device comprising a group III-V semiconductor material disposed on the carrier body and having a light-receiving surface. The light-emitting surface is separated from the topmost surface by first distant H1, the light-receiving surface is separated from the topmost surface by a second distance H2, and H1 is different from H2.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 6, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Yi-Chieh Lin, Shiuan-Leh Lin, Yung-Fu Chang, Shih-Chang Lee, Chia-Liang Hsu, Yi Hsiao, Wen-Luh Liao, Hong-Chi Shih, Mei-Chun Liu
  • Patent number: 11894482
    Abstract: A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: February 6, 2024
    Assignee: Dual Helios Semiconductor Equipment Company, Inc.
    Inventor: Lawrence Chung-Lai Lei
  • Patent number: 11894483
    Abstract: The invention provides a laser rapid fabrication method for flexible gallium nitride (GaN) photodetector which comprises the following steps: (1) bonding a flexible substrate to a GaN epitaxial wafer; (2) adjusting the focal plane position of a light beam, and ensuring that the light beam is incident from the side of a GaN epitaxial wafer substrate; (3) enabling the light beam to perform scanning irradiation from the edge of a sample structure obtained in the step (1); (4) adjusting the process parameters, and scanning irradiation in the reverse direction along the path in the step (3); (5) remove the original rigid transparent substrate of the epitaxial wafer to obtain a Ga metal nanoparticle/GaN film/flexible substrate structure; and (6) preparing interdigital electrodes on the surfaces of the Ga metal nanoparticles obtained in the step (5).
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: February 6, 2024
    Assignee: BEIJING UNIVERSITY OF TECHNOLOGY
    Inventors: Lingfei Ji, Weigao Sun
  • Patent number: 11894484
    Abstract: A solar cell chip arrangement machine includes a feeding mechanism and a slicing mechanism. The feeding mechanism includes a whole battery piece. A push block is connected to the back of the whole battery piece, and a pressing plate is arranged above the front of the whole battery piece. The slicing mechanism is arranged on the pressing plate above the front of the whole battery piece. The slicing mechanism includes a vacuum sucker, a guide plate, a guide plate slide rail, a positioning block, a positioning block slide rail, a cylinder, a fixed plate, and a vacuum generator. The positioning block is arranged on the positioning block slide rail, a pulley is arranged on the positioning block, and the guide plate is provided with a limit slot corresponding to the pulley. The vacuum sucker is arranged on the positioning block, and the vacuum sucker is connected to the vacuum generator.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: February 6, 2024
    Assignee: GOLDEN SOLAR (QUANZHOU) NEW ENERGY TECHNOLOGY CO., LTD.
    Inventor: Hsin-wang Chiu
  • Patent number: 11894485
    Abstract: A wire bonding system attaches wires to a solar cell wafer. The wire bonding system includes a feed tube through which a wire is drawn. Rollers contact the wire through openings in the feed tube to facilitate movement of the wire. The wire bonding system includes a soldering heater tip and a wire cutter. The solar cell wafer is placed on a platform, which moves the solar cell wafer. The system has multiple lanes for attaching multiple wires to the solar cell wafer at the same time in parallel operations.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: February 6, 2024
    Assignee: Maxeon Solar Pte. Ltd
    Inventors: Vergil R. Sandoval, Emmanuel C. Abas, Yafu Lin
  • Patent number: 11894486
    Abstract: Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: February 6, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Miyuki Hosoba, Suzunosuke Hiraishi
  • Patent number: 11894487
    Abstract: A light-emitting device comprises a substrate; a first semiconductor layer formed on the substrate; a first patterned layer formed on the first semiconductor layer; and a second semiconductor layer formed on the first semiconductor layer, wherein the second semiconductor layer comprises a core layer comprising a group III or transition metal material formed along the first patterned layer.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: February 6, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-Kuo Lai, Li-Shen Tang
  • Patent number: 11894488
    Abstract: LED chips and related fabrication methods are disclosed. A LED chip includes an active layer arranged on or over a light-transmissive substrate having a light extraction surface. The light extraction surface comprises a microtextured etched surface having a non-repeating, irregular textural pattern (e.g., with an average feature depth in a range of from 120 nm to 400 nm, and preferably free of any plurality of equally sized, shaped, and spaced textural features). The microtextured etched surface may be formed by applying a micromask having first and second solid materials of different etching rates over the light extraction surface, and exposing the micromask to an etchant (e.g., via reactive ion etching) to form a microtextured etched surface having a non-repeating, irregular textural pattern. Lumiphoric material may be applied over the microtextured surface.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: February 6, 2024
    Assignee: CreeLED, Inc.
    Inventor: Peter Scott Andrews
  • Patent number: 11894489
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a first semiconductor layer, an active region, a p-type or n-type layer, and a first metal element-containing structure. The first semiconductor layer has a surface including a first portion and a second portion. The active region is located on the first portion and includes AlGaInAs, InGaAsP, AlGaAsP or AlGaInP. The p-type or n-type layer includes an oxygen element (O) and a metal element, and is located on the second portion. The first metal element-containing structure is located on the p-type or n-type layer. The p-type or n-type layer physically contacts the first metal element-containing structure and the first semiconductor layer.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: February 6, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Yu-Tsu Lee, Wei-Jen Hsueh
  • Patent number: 11894490
    Abstract: A spherical flip-chip micro-LED, a method for manufacturing the spherical flip-chip micro-LED, and a display panel are provided. The spherical flip-chip micro-LED includes a light-emitting body, a supporting body, a first electrode, a second electrode, and an insulating protective layer. The supporting body is transparent. The first electrode and the second electrode are electrically coupled with the light-emitting body. The insulating protective layer covers the light-emitting body. The light-emitting body, the supporting body, and the insulating protective layer form a spherical structure.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 6, 2024
    Assignee: CHONGQING KONKA PHOTOELECTRIC TECHNOLOGY RESEARCH INSTITUTE CO., LTD
    Inventors: Biao Tang, Haiping Liu, Zhongshan Feng
  • Patent number: 11894491
    Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: February 6, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Tsung-Hsun Chiang, Bo-Jiun Hu, Wen-Hung Chuang, Yu-Ling Lin
  • Patent number: 11894492
    Abstract: A light emitting element includes: a substrate; a mesa portion formed on the substrate and including an active layer, a first semiconductor layer, and a second semiconductor layer; a metal layer including a first metal part disposed on a top surface of the mesa portion and connected to the second semiconductor layer and a second metal part formed integrally with the first metal part and extending along a side surface of the mesa portion; an insulating layer formed on the side surface; and a resin layer formed on the insulating layer. The first metal part includes an opening region formed with a light passage opening and a connection region for external connection. The second metal part is formed on the side surface via the insulating layer and the resin layer and overlaps the active layer when viewed in a direction perpendicular to a thickness direction of the substrate.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: February 6, 2024
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Shota Someya, Takayuki Hoshino, Shunji Suzuki
  • Patent number: 11894493
    Abstract: A radiation-emitting semiconductor chip may include a semiconductor body, a reflector, at least one cavity, and a seal. The semiconductor body may include an active region configured to generate electronic radiation. The reflector may be configured to reflect a portion of the electromagnetic radiation. The cavity may be filled with a material having a refractive index not exceeding 1.1. The seal may be impermeable to the material. The cavity may be arranged between the reflector and the semiconductor body, and the seal may cover the underside of the reflector.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: February 6, 2024
    Assignee: OSRAM OLED GMBH
    Inventors: Korbinian Perzlmaier, Stefan Illek
  • Patent number: 11894494
    Abstract: A terahertz device includes a terahertz element, a sealing resin, a wiring layer and a frame-shaped member. The terahertz element that performs conversion between terahertz waves and electric energy. The terahertz element has an element front surface and an element back surface spaced apart from each other in a first direction. The sealing resin covers the terahertz element. The wiring layer is electrically connected to the terahertz element. A frame-shaped member is made of a conductive material and arranged around the terahertz element as viewed in the first direction. The frame-shaped member has a reflective surface capable of reflecting the terahertz waves.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 6, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Kazuisao Tsuruda, Jaeyoung Kim, Hideaki Yanagida, Toshikazu Mukai
  • Patent number: 11894495
    Abstract: A micro LED structure includes a first micro LED chip having opposite first and second sides, a second micro LED chip adjacent to the first side of the second micro LED chip, a third micro LED chip adjacent to the first side of the first micro LED chip, and optical structures respectively over the first micro LED chip, the second micro LED chip and the third micro LED chip. Each of the first, second and third micro LED chip includes a semiconductor stack, a metal pad and a reflective coating layer. The semiconductor stack includes a first semiconductor layer, an active layer in contact with the first semiconductor layer, and a second semiconductor layer in contact with the active layer. The metal pad is in contact with the first semiconductor layer, and the reflective coating layer is disposed around sidewalls of the semiconductor stack.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: February 6, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Kai-Hung Cheng, Fu-Han Ho
  • Patent number: 11894496
    Abstract: A light emitting device includes a LED having a light emitting first surface and a light emitting second surface that define a corner. A support layer is disposed to receive light emitted by the light emitting second surface and is disposed adjacent the corner. A luminophoric medium layer at least partially covers the light emitting first surface and the light emitting second surface where the luminophoric medium layer is at least partially supported by the support layer to prevent a narrowing of the luminophoric medium layer.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: February 6, 2024
    Assignee: CreeLED, Inc.
    Inventors: Robert Wilcox, Sarah Trinkle, Derek Miller, Peter Andrews, Colin Blakely
  • Patent number: 11894497
    Abstract: A method of manufacturing a covering member includes: providing a first light-reflective member comprising a through-hole, the through-hole having first and second openings; arranging a light-transmissive resin containing a wavelength-conversion material within the through-hole; distributing the wavelength-conversion material predominantly on a side of the first opening of the through-hole within the light-transmissive resin; and after the step of distributing the wavelength-conversion material, removing a portion of the light-transmissive resin from a side of the second opening of the through-hole.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 6, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Tadao Hayashi, Teruhito Azuma, Suguru Beppu, Kunihiro Izuno, Tsuyoshi Okahisa
  • Patent number: 11894498
    Abstract: A light emitting device including a first light emitting element that includes a first electrode having a first polarity and a second electrode having a second polarity that is different from the first polarity. The device has a circuit element that includes a main body, and first and second terminals electrically connected with one another via the main body. The device includes a first wiring having the first polarity connecting the first electrode of the first light emitting element and the first terminal, and a second wiring having the second polarity located in a layer common with a layer of the first wiring and including a portion elongated between the first terminal and the second terminal in a bottom view. An upper surface of the main body is positioned at a distance below an interface between a lower surface of the first wiring and the first electrode.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: February 6, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Rie Maeda, Masaaki Katsumata
  • Patent number: 11894499
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and lens arrangements for packaged LED devices are disclosed. An LED package may include one or more LED chips on a submount with a lens positioned on the submount to form a cavity. The one or more LED chips may reside in the cavity without direct encapsulation materials that would otherwise contact the one or more LED chips and any corresponding wirebonds. In this manner, the one or more LED chips may be driven with higher drive currents while reducing degradation and mechanical strain effects related to differences in coefficients of thermal expansion with typical encapsulant materials. LED packages may also be configured with one or more apertures that allow air flow between an interior volume of a cavity and an ambient environment outside the LED package to promote heat dissipation at higher drive currents.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: February 6, 2024
    Assignee: CreeLED, Inc.
    Inventors: Robert Wilcox, Derek Miller, Kyle Damborsky, Aaron Francis, Colin Blakely
  • Patent number: 11894500
    Abstract: A lighting device disclosed in an embodiment of the invention includes a substrate; a plurality of light sources spaced apart from each other at predetermined intervals on the substrate; a resin layer disposed on the substrate; a phosphor layer disposed on the resin layer and having a pattern layer including a concave portion and a convex portion formed on a surface facing the resin layer; and a diffusion layer disposed between the resin layer and the phosphor layer, wherein a thickness of the diffusion layer may be 10% or more and less than 50% of the maximum thickness of the phosphor layer.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: February 6, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Hoon Park, Sarum Han
  • Patent number: 11894501
    Abstract: The present disclosure provides a lighting device and a manufacturing method thereof. The lighting device includes a substrate, a light emitting unit, a light adjusting layer and at least one electrode connecting element. The light emitting unit is disposed on the substrate and includes a light output surface and a plurality of top electrodes. The light adjusting layer is disposed on the light emitting unit, and the light adjusting layer includes a first portion and a second portion connected to the first portion. Wherein the top electrodes are electrically connected to each other through the electrode connecting element, the first portion only partially covers the light output surface, and the second portion does not cover the light output surface.
    Type: Grant
    Filed: October 30, 2022
    Date of Patent: February 6, 2024
    Assignee: InnoLux Corporation
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee, Yuan-Lin Wu
  • Patent number: 11894502
    Abstract: A method of manufacturing a semiconductor optical device of this disclosure includes the steps of forming an etch stop layer on an InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and forming a semiconductor laminate on the etch stop layer by stacking a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P. Further, an intermediate article of a semiconductor optical device of the present disclosure includes an InP growth substrate; an etch stop layer formed on the InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and a semiconductor laminate formed on the etch stop layer, including a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P stacked one another.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 6, 2024
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Yuta Koshika, Yoshitaka Kadowaki, Tetsuya Ikuta
  • Patent number: 11894503
    Abstract: A light emitting diode device includes a substrate, a frame, an LED die and a transparent layer. The frame is located on the substrate. The frame and the substrate collectively define a concave portion. The frame has a light reflectivity ranging from 20% to 40%. The LED die is located on the substrate and within the concave portion. The transparent layer is filled into the concave portion and covering the LED die, wherein the LED die has a side-emitting surface and a top-emitting surface, the side-emitting surface has a luminous intensity greater than that of the top-emitting surface.
    Type: Grant
    Filed: November 24, 2022
    Date of Patent: February 6, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Shu-Wei Chen, Ching-Huai Ni, Kuo-Wei Huang, Jia-Jhang Kuo
  • Patent number: 11894504
    Abstract: A display apparatus is provided. The display apparatus can include a substrate hole penetrating a device substrate, light-emitting devices spaced away from the substrate hole, and at least one separating device between the substrate hole and the light-emitting devices. Each of the light-emitting devices can include a light-emitting layer between a first electrode and a second electrode. The separating device can surround the substrate hole. The separating device can include at least one under-cut structure. The under-cut structure can include a depth and a length, which are larger than a thickness of the light-emitting layer. Thus, in the display apparatus, the damage of the light-emitting devices due to external moisture permeating through the substrate hole can be prevented.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 6, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventors: So-Young Noh, So-Yeon Je, Ki-Tae Kim, Kyeong-Ju Moon, Hyuk Ji
  • Patent number: 11894505
    Abstract: The present disclosure provides a display device and a manufacturing method thereof. The display device includes: a substrate; a conductive layer disposed on the substrate; and a reflective layer disposed on the conductive layer; wherein a plurality of flask-shaped holes are disposed in the reflective layer and part of the conductive layer, and a depth of each of the flask-shaped holes is greater than a thickness of the reflective layer.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: February 6, 2024
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Junling Liu
  • Patent number: 11894506
    Abstract: A display apparatus is provided. The display apparatus includes a pad spaced away from an encapsulating element. The pad can have a stacked structure of a pad electrode layer and a pad cover layer. A side surface of the pad electrode layer can be covered by the pad cover layer. Thus, in the display apparatus, damage of the pad electrode layer due to a subsequent process can be prevented and as such, the reliability of an external signal transmitted through the pad can be improved.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: February 6, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sun-Mi Lee, Chang-Hoon Oh
  • Patent number: 11894507
    Abstract: This disclosure discloses a method of manufacturing a light-emitting device includes steps of providing a first substrate with a plurality of first light-emitting elements and adhesive units arranged thereon, providing a second substrate with a first group of second light-emitting elements and a second group of second light-emitting elements arranged thereon, and connecting the a second group of second light-emitting elements and the adhesive units. The first light-emitting elements and the first group of second light-emitting elements are partially or wholly overlapped with each other during connecting the second group of second light-emitting elements and the adhesive units.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: February 6, 2024
    Assignee: EPISTAR CORPORATION
    Inventor: Min-Hsun Hsieh
  • Patent number: 11894508
    Abstract: A second-generation high temperature superconducting (HTS) strip and a preparation method thereof are provided. The second-generation HTS strip includes a superconducting strip body and a stabilizing layer arranged thereon. The stabilizing layer is a copper-graphene composite film with a total thickness of 2-30 microns on one side. The superconducting strip may be obtained by the preparation method of: (1) putting a superconducting strip body into a magnetron sputtering reaction chamber, followed by pumping to a high-level vacuum and filling with a working gas; (2) using copper and graphene as targets, and performing a sputter coating by controlling a magnetron sputtering power, to deposit the targets onto at least one surface of the superconducting strip body.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: February 6, 2024
    Assignees: Shanghai Superconductor Technology Co., Ltd., Shanghai Jiao Tong University
    Inventors: Yue Zhao, Donghong Wu, Guangyu Jiang, Chunsheng Cheng, Jiamin Zhu, Wei Wu, Yijun Ding, Zhijian Jin
  • Patent number: 11894509
    Abstract: Provided are a winding device and a winding apparatus. An inner shaft of the winding device is configured to clamp an electrode assembly; and an outer shaft of the winding device is configured to wind the electrode assembly. The winding device includes: a first slider and a first pusher, where the first slider may reciprocate in a first sliding slot in the first pusher in a first direction, and an extension direction of the first sliding slot is inclined from the first direction such that the first pusher drives a first inner shaft to reciprocate in a second direction, the second direction being perpendicular to the first direction; and a second slider and a second pusher, where the second slider may reciprocate in a second sliding slot in the second pusher in a third direction, and an extension direction of the second sliding slot is inclined from the third direction.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: February 6, 2024
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Wei Zhang, Xiaowei Zhang, Xiang Wu, Yuqian Wen