Abstract: A system for performing a bevel cleaning process on a substrate includes a substrate support including an electrode and a plurality of plasma needles arranged around a perimeter of the substrate support. The plasma needles are in fluid communication with a gas delivery system and are configured to supply reactive gases from the gas delivery system to a bevel region of the substrate when the substrate is arranged on the substrate support and electrically couple to the electrode of the substrate support and generate plasma around the bevel region of the substrate.

Abstract: Embodiments disclosed herein include a method for cleaning a bevel area of a substrate support disposed within a plasma processing chamber. In one example the method begins by placing a cover substrate on a substrate support disposed in an interior volume of a processing chamber. A cleaning gas is provided into the interior volume of the processing chamber. A plasma is struck in the interior volume of the processing chamber. A cleaning gas is provided through the substrate support to a bevel edge area defined between an outer diameter of the cover substrate and an edge ring disposed on the substrate support.

Abstract: Methods and systems for forming a forming a nitrogen-containing carbon film and structures formed using the methods or systems are disclosed. Exemplary methods include providing a precursor with carbon-terminated carbon-nitrogen bonds. The methods can further include providing a reactant to the reaction chamber.

Abstract: Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly <100> surfaces with reduced or negligible growth on <110> surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.

Abstract: Methods for selectively depositing silicon oxycarbide (SiOC) thin films on a dielectric surface of a substrate relative to a metal surface without generating significant overhangs of SiOC on the metal surface are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor, a first Ar and H2 plasma, a second Ar plasma and an etchant.

Abstract: A method of manufacturing a semiconductor device includes forming a first lower overlay key including first and second patterns in a lower layer, forming a first upper overlay key including third and fourth patterns in an upper layer vertically disposed on the lower layer, irradiating a first measurement light to a first region of interest (ROI) over first portions of the first and second patterns to detect a first overlay error and irradiating a second measurement light to a second ROI over second portions of the first and second patterns, the second ROI being different from the first ROI, to detect a second overlay error.

Abstract: Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.

Abstract: Methods and apparatus for laser patterning leverage mask trench debris removal techniques to form etch singulation trenches. In some embodiments, the method includes forming a mask layer on the wafer, forming a pattern in the mask layer using a laser of a laser assembly where the pattern allows singulation of the wafer by deep etching and forms a trench in the mask layer with a laser beam which has a process point at a bottom of the trench, directing gas nozzles that flow a pressurized gas at the process point in the trench as the pattern is formed with a gas flow angle relative to the process point and evacuating debris from the trench using an area of negative pressure where the gas flow from gas nozzles and the area of negative pressure are in fluid contact and are confined within a cylindrical housing.

Abstract: A method for manufacturing a semiconductor structure, comprising: forming a first mask layer, a first buffer layer, a second mask layer and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer; forming a first mask pattern on a side wall of a first pattern, the first mask pattern extending in a first direction; removing the second buffer layer and the second mask layer; forming a third mask layer, a third buffer layer, a fourth mask layer and a fourth buffer layer sequentially stacked form bottom to top; patterning the fourth buffer layer and the fourth mask layer; forming a second mask pattern on a side wall of a second pattern, the second mask pattern extending in a second direction; removing the fourth buffer layer and the fourth mask layer.

Abstract: In an example, the present invention provides a method of forming a semiconductor device on a gallium and nitrogen containing material. The method includes providing a substrate member comprising a surface region, the substrate member comprising a gallium and nitrogen bearing material. The method includes causing an implanted species to electrically activate the implant profile while removing one or more crystalline damage from the epitaxial material to change the amorphous state to a single crystalline state, and thereby creating a substantially electrically activated crystalline material.

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

Abstract: A method for forming a semiconductor structure in provided. The method includes providing a substrate, forming a gate electrode layer on the substrate, and performing a defluorination treatment on the gate electrode layer. The method also includes, after performing the defluorination treatment, forming a barrier layer on a portion of a surface of the gate electrode layer. The barrier layer is made of a material including titanium element.

Abstract: Vapor deposition processes are provided for bottom up filling of trenches and other structures with metal nitrides such as vanadium nitride and titanium nitride. In some embodiments, VCl4 can be used as an etchant source in the deposition processes. The reaction conditions are selected such that some Cl2 forms in the reaction space and preferentially etches deposited metal nitride at the upper surfaces of a trench or other three-dimensional feature on a substrate. The self-etching during the deposition process facilitates a bottom up filling of the feature and may reduce or eliminate the formation of seams or voids.

Abstract: There is provided a method for manufacturing a semiconductor device, including: attracting a semiconductor device wafer by a chuck mechanism and rotating the semiconductor device wafer horizontally; rotating a rotary blade horizontally by a vertical spindle to which ultrasonic waves are applied; trimming an outer peripheral end portion of the semiconductor device wafer that is horizontally rotating by the rotary blade that is horizontally rotating, to form a groove in the outer peripheral end portion; correcting a tip shape of the rotary blade that is horizontally rotating by a blade-forming grinding wheel during the trimming; and grinding one main surface of the semiconductor device wafer that is horizontally rotating by a cup grinding wheel that is horizontally rotating after the trimming.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a fixing layer, coupling a third substrate different from the first substrate and the second substrate to the fixing layer, separating the semiconductor thin film layer from the first substrate by moving the third substrate away from the base material substrate with the third substrate coupled to the coupling region, and bonding the semiconductor thin film layer to the second substrate after separation from the base material substrate, wherein the forming the fixing layer forms the fixing layer having a thickness such that a crack is generated between the fixing layer formed on the first substrate and the fixing layer formed on a side surface of the semiconductor thin film layer by a force for moving the third substrate.

Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

Abstract: A method includes forming an etching mask to cover a mandrel, a first spacer, and a second spacer, and the first spacer and the second spacer are in contact with opposing sidewalls of the mandrel. The etching mask is then patterned, and includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has first sidewalls. A first etching process is performed on the mandrel using the etching mask to define pattern, and after the first etching process, the mandrel includes a second bridge portion having second sidewalls vertically aligned to corresponding ones of the first sidewalls. After the mandrel is etched-through, a second etching process is performed to laterally recess the second bridge portion of the mandrel.

Abstract: A semiconductor processing tool includes a cleaning chamber configured to perform a post-chemical mechanical polishing/planarization (post-CMP) cleaning operation in an oxygen-free (or in a near oxygen-free) manner. An inert gas may be provided into the cleaning chamber to remove oxygen from the cleaning chamber such that the post-CMP cleaning operation may be performed in an oxygen-free (or in a near oxygen-free) environment. In this way, the post-CMP cleaning operation may be performed in an environment that may reduce oxygen-causing corrosion of metallization layers and/or metallization structures on and/or in the semiconductor wafer, which may increase semiconductor processing yield, may decrease semiconductor processing defects, and/or may increase semiconductor processing quality, among other examples.

Abstract: Embodiments disclosed herein include methods of developing a metal oxo photoresist. In an embodiment, the method comprises providing a substrate with the metal oxo photoresist into a vacuum chamber, where the metal oxo photoresist comprises exposed regions and unexposed regions. In an embodiment, the unexposed regions comprise a higher carbon concentration than the exposed regions. The method may further comprise vaporizing a halogenating agent into the vacuum chamber, where the halogenating agent reacts with either the unexposed regions or the exposed regions to produce a volatile byproduct. In an embodiment, the method may further comprise purging the vacuum chamber.

Abstract: A method for etching an oxide semiconductor film includes: providing a substrate including a mask of a silicon-containing film on an oxide semiconductor film containing at least indium (In), gallium (Ga), and zinc (Zn); supplying a processing gas containing a bromine (Br)-containing gas or an iodine (I)-containing gas; and etching the oxide semiconductor film by plasma generated from the processing gas.

Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Abstract: In one embodiment a power semiconductor module includes a substrate having a first substrate side for carrying an electric circuit and having a second substrate side being located opposite to the first substrate side. The second substrate side has a flat surface and is adapted for coming in contact with a cooler. A cooling area that is surrounded by a connecting area is located at the second substrate side. A first casing component of the cooler is connected to the second substrate side at the connecting area and a second casing component is connected to the first casing component such that a cooling channel for providing the cooling area with cooling fluid is provided between the first casing component and the second casing component. A cooling structure can be welded to the cooling area at the second substrate side.

Abstract: A substrate processing method includes: generating a mixture liquid by mixing a phosphoric acid aqueous solution with an additive that suppresses precipitation of silicon oxide in a tank and circulating the mixture liquid through a circulation path that exits and returns to the tank, the circulation path including a back pressure valve; sending the mixture liquid to a processing bath through a liquid path diverging from the circulation path and positioned upstream from the back pressure valve; and supplying a silicon-containing compound aqueous solution to the mixture liquid generated in the generating. The back pressure valve is fully open in the generating and throttled in the sending. A substrate processing apparatus includes a processing bath, a mixing device, a liquid path, and a silicon solution supply.

Abstract: An apparatus for forming a solder bump on a substrate including a supporter configured to support the substrate to be provided thereon, a housing surrounding the supporter, a cover defining a manufacturing space in combination with the housing and including an edge heating zone along a perimeter thereof, the manufacturing space surrounding the supporter, and an oxide remover supply nozzle configured to supply an oxide remover to the manufacturing space may be provided.

Abstract: Apparatus, systems, and methods for processing workpieces are provided. In one example, such a method for performing a spike anneal rapid thermal process may include controlling a heat source to begin heating a workpiece supported on a workpiece support in a processing chamber. The method may further include receiving data indicative of a temperature of the workpiece. Furthermore, the method may include monitoring the temperature of the workpiece relative to a temperature setpoint. Moreover, the method may include controlling the heat source to stop heating the workpiece based at least in part on the workpiece reaching the temperature setpoint. Additionally, the method may include controlling a cooling system to begin flowing a cooling gas at a rate of about 300 slm or greater over the workpiece based at least in part on the workpiece reaching the temperature setpoint to reduce a t50 peak width of the workpiece.

Abstract: A chip transfer apparatus includes: a chip storage module in which a plurality of micro-semiconductor chips and a suspension including impurities are stored; a chip filtration module separating a first suspension including the plurality of micro-semiconductor chips and a second suspension including the impurities in the suspension; and a chip supply module configured to supply the first suspension onto the transfer substrate such that the first suspension is introduced from the chip filtration module and the plurality of micro-semiconductor chips are flowable on the transfer substrate.

Abstract: In an embodiment, a system includes: a wafer support configured to secure a wafer; a nozzle configured to dispense a liquid or a gas on the wafer when the nozzle is in an active state of dispensing; a shutter configured to catch the liquid from the nozzle when the shutter is in a first position below the nozzle; and a shutter actuator configured to: move the shutter to the first position in response to the nozzle not being in an inactive state; move the shutter to a second position away from the first position in response to the nozzle being in the active state.

Abstract: Embodiments herein provide methods of monitoring temperatures of fluid delivery conduits for delivering fluids to, and other components external to, a processing volume of a processing chamber used in electronic device fabrication manufacturing, and monitoring systems related thereto. In one embodiment, a method of monitoring a processing system includes receiving, through a data acquisition device, temperature information from one or more temperature sensors and receiving context information from a system controller coupled to a processing system comprising the processing chamber. Here, the one or more temperature sensors are disposed in one or more locations external to a processing volume of a processing chamber. The context information relates to instructions executed by the system controller to control one or more operations of the processing system.

Abstract: To suppress lowering of dimensional accuracy.

Abstract: A device for recognizing wafer identification number with automatically turning on and off recognizing function comprises a base, a support frame, a light source, a plurality of image capturing units, an image recognition unit and a control unit. The base comprises a wafer boat placing portion and a first switch disposed on the wafer boat placing portion. The light source and the image capturing units are disposed on the support frame. The control unit is electrically connected to the first switch, the light source, the image capturing units and the image recognition unit. As such, the device for recognizing wafer identification number with automatically turning on and off recognizing function can automatically turn on and off the light source, the image capturing units, and the image recognition unit, therefore the operation is very easy and convenience.

Abstract: Gaskets for wafer containers include a seal body and a retention projection. The retention projection includes a retention segment extending from the seal body, a compression relief segment extending from the retention segment, and a bead disposed at an end of the compression relief segment. The compression relief segment has a cross-sectional width less than a cross-sectional width of the retention segment. The bead has a shape including portion having a width greater than a cross-sectional width of the gland at a corresponding depth in the gland. The gasket can be provided in a wafer container or a door of the wafer container.

Abstract: A calibration pod for calibrating a robotic wafer pod handling apparatus includes a pod body configured for handling by the robotic pod handling apparatus, at least one laser disposed on a bottom of the pod body, and a power module disposed on or in the pod body and operatively connected to power the at least one laser. In a manufacturing method, the pod body comprises a wafer carrier for carrying a cassette of semiconductor wafers, which has a bottom with a plurality of holes for aligning placement of the wafer carrier in a load port of a semiconductor device fabrication facility. The at least one laser here includes a plurality of lasers corresponding to the plurality of holes in the bottom of the wafer carrier, and each laser is mounted in a respective hole of the bottom of the wafer carrier.

Abstract: An article transfer system includes a plurality of stage modules respectively provided at a plurality of layers, an interlayer transfer apparatus configured to transfer an article to each of the plurality of stage modules, and a plurality of loading and unloading apparatus respectively provided on each stage module of the plurality of stage modules, the plurality of loading and unloading apparatus configured to load an article onto respective stage modules of the plurality of stage modules. The interlayer transfer apparatus includes a mast frame extending so as to intersect each stage module of the plurality of stage modules, and a plurality of carriage units configured to move along a length direction of the mast frame, transfer articles, and move in a parallel manner with each other.

Abstract: A substrate loading device including a frame adapted to connect to a substrate processing apparatus, the frame having a transport opening through which substrates are transported to the processing apparatus, a cassette support connected to the frame for holding at least one substrate cassette container proximate the transport opening, the support configured so that a sealed internal atmosphere of the container is accessed from the support at predetermined access locations of the container, and the cassette support has a predetermined continuous steady state differential pressure plenum region, determined at least in part by boundaries of fluid flow generating differential pressure, so that the predetermined continuous steady state differential pressure plenum region defines a continuously steady state fluidic flow isolation barrier disposed on the support between the predetermined access locations of the container and another predetermined section of the support isolating the other predetermined section from

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

Abstract: A component manufacturing method includes a step of obtaining a holding tool. The holding tool includes: a frame body having an opening; and a holding film placed on the frame body. The step is a step of placing the holding film on the frame body while stretching the holding film in at least three different directions or in all directions to the frame body. The holding film includes a base layer and a holding layer. The holding tool forming device includes: a mechanism that pushes a plain film from a base layer side to bring about a stretched state; a mechanism that fixes the plain film to the frame body such that the stretched state is maintained; and a mechanism that isolates an unnecessary portion from the plain film to obtain the holding film.

Abstract: An elastic membrane to be used for a polishing head includes a contact portion configured to come into contact with a wafer, an annular side wall provided to stand on an outer peripheral end of the contact portion, a first partition wall linearly extending inward in a radial direction in sectional view from the side wall, and a second partition wall linearly extending inward and upward in the radial direction in sectional view from an outer peripheral end portion of the contact portion, wherein the first partition wall, the second partition wall, and the side wall constitute an edge pressure chamber for pressing an edge of the wafer.

Abstract: A wafer flipping device for use in semiconductor processing, comprises a supported rotating assembly that receives a semiconductor work product on one side when in a first unrotated position, grips and aligns the work product, rotates with the semiconductor work product thereon into a rotated position, and releases the semiconductor work product from the rotated, position. The semiconductor work product may be any one of a range of different shapes and sizes and retractable pins are selected for the corresponding shape or size.

Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

Abstract: Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first conductive layer formed over a substrate, and an air gap structure adjacent to the first conductive layer. The semiconductor device structure includes a support layer formed over the air gap structure. A bottom surface of the support layer is in direct contact with the air gap structure, and the bottom surface of the support layer is lower than a top surface of the first conductive layer and higher than a bottom surface of the first conductive layer.

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: To provide a semiconductor device with less variations, a first insulator is deposited; a stack of first and a second oxides and a first conductor is formed over the first insulator; a second insulator is formed over the first insulator and the stack; an opening is formed in the second insulator; a top surface of the second oxide is exposed by removing a region of the first conductor, second and third conductors are formed over the second oxide, and then cleaning treatment is performed; a first oxide film is deposited in contact with a side surface of the first oxide and top and side surfaces of the second oxide; heat treatment is performed on an interface between the second oxide and the first oxide film through the first oxide film; and the second insulator is exposed and a fourth conductor, a third insulator, and a third oxide are formed in the opening.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.