Comprising A Silicon Crystal With Oxygen Containing Impurity Patents (Class 117/20)
  • Patent number: 7364618
    Abstract: This silicon wafer is obtained from a silicon single crystal grown by the CZ method in a hydrogen-containing inert gas atmosphere, and is a completely grown-in defect-free wafer containing no COPs or dislocation clusters throughout the wafer in the thickness and radial directions thereof, and all the portions consist essentially of an interstitial rich region. This method for growing silicon single crystals includes pulling a silicon single crystal in a hydrogen-containing inert gas atmosphere so as to expand the range of the pull rate for the PI region, wherein the pulling of the silicon single crystal is conducted at a pull rate within this expanded range of the pull rate for the PI region so as to grow a body portion that is an interstitial rich region.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: April 29, 2008
    Assignee: Sumco Corporation
    Inventors: Masataka Hourai, Wataru Sugimura, Toshiaki Ono
  • Patent number: 7361218
    Abstract: The present invention relates to a method for fabricating a crystal fiber having different regions of polarization inversion, comprising the following steps: (a) providing a source material; (b) putting the source material into a fabricating apparatus; and (c) forming the crystal fiber from the source material, and applying an external electric field on the grown crystal fiber during the growth procedure of the crystal fiber so as to induce micro-swing of the crystal fiber for polarization inversion, whereby poling at the time a ferroelectric crystalline body is being formed, whereas the conventional methods are designed for poling a ferroelectric crystalline body after it has been formed.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: April 22, 2008
    Assignee: National Sun Yat-Sen University
    Inventors: Chia-Chang Kuo, Li-Min Lee, Yu-Chieh Cho, Sheng-Lung Huang, Sheng Bang Huang
  • Patent number: 7351282
    Abstract: Cutting method of ingot into wafers along cleavage plane. Onto surface of single crystal ingot 10 is implanted ion beam 23 to generate lattice defects in a direction defined by the crystal axes that corresponds to the cleavage plane. Cleavage is generated by applying a shock by a knife edge to the position of the lattice having a cutting face as a cleavage plane. Production time of waters is reduced with a more numbers of sliced wafers from one ingot.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: April 1, 2008
    Assignee: Kabushiki Kaisha Y.Y.L.
    Inventor: Sataro Yamaguchi
  • Patent number: 7344689
    Abstract: A silicon wafer for an IGBT is produced by forming an ingot having an interstitial oxygen concentration [Oi] of not more than 7.0×1017 atoms/cm3 by the Czochralski method; doping phosphorus in the ingot by neutron beam irradiation to the ingot; slicing a wafer from the ingot; performing annealing of the wafer in an oxidizing atmosphere containing at least oxygen at a temperature satisfying a predetermined formula; and forming a polysilicon layer or a strained layer on one side of the wafer.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 18, 2008
    Assignee: Sumco Corporation
    Inventors: Shigeru Umeno, Yasuhiro Oura, Koji Kato
  • Patent number: 7329317
    Abstract: The present invention is to produce a silicon crystal wherein the boron concentration in the silicon crystal and the growth condition V/G are controlled so that the boron concentration in the silicon crystal is no less than 1×1018 atoms/cm3 and the growth condition V/G falls within the epitaxial defect-free region ?2 whose lower limit line LN1 is the line indicating that the growth rate V gradually drops as the boron concentration increases. A silicon wafer is also produced wherein the boron concentration in the silicon crystal and the growth condition V/G are controlled so as to include at least the epitaxial defect region ?1, and both the heat treatment condition and the oxygen concentration of the silicon crystal are controlled so that no OSF nuclei grow to OSFs.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: February 12, 2008
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Susumu Maeda, Hiroshi Inagaki, Shigeki Kawashima, Shoei Kurosaka, Kozo Nakamura
  • Patent number: 7326658
    Abstract: The present invention provides a method for producing a nitrogen-doped annealed wafer, wherein before a wafer sliced from a silicon single crystal doped with at least nitrogen and polished is subjected to a high temperature heat treatment at 1100° C. to 1350° C. in an atmosphere of argon, hydrogen or a mixed gas thereof, a step of maintaining the wafer at a temperature lower than the treatment temperature of the high temperature heat treatment is conducted to allow growth of oxygen precipitation nuclei having such a size that the nuclei should be annihilated by the high temperature heat treatment to such a size that the nuclei should not be annihilated by the high temperature heat treatment, and then the high temperature heat treatment is performed.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: February 5, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Makoto Iida, Masaro Tamatsuka
  • Patent number: 7326395
    Abstract: The present invention is a method for producing a single crystal in accordance with Czochralski method by flowing an inert gas downward in a chamber 1 of a single crystal-pulling apparatus 11 and surrounding a single crystal 3 pulled from a raw material melt 2 with a gas flow-guide cylinder 4, wherein when a single crystal within N region outside OSF region generated in a ring shape in the radial direction of the single crystal is pulled, the single crystal within N region is pulled in a condition that flow amount of the inert gas between the single crystal and the gas flow-guide cylinder is 0.6 D(L/min) or more and pressure in the chamber is 0.6 D(hPa) or less, in which D (mm) is a diameter of the single crystal to be pulled. It is preferable that there is used the gas flow-guide cylinder that Fe concentration is 0.05 ppm or less, at least, in a surface thereof.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: February 5, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Izumi Fusegawa, Nobuaki Mitamura, Takahiro Yanagimachi
  • Patent number: 7323048
    Abstract: A method for producing a single crystal in which when the single crystal is grown by Czochralski method, V/G is controlled by controlling a fluctuation of a temperature gradient G of the crystal which is being pulled without lowering a pulling rate V, thereby the single crystal including a desired defect region over a whole plane in a radial direction of the crystal entirely in a direction of the crystal growth axis can be produced effectively for a short time at a high yield.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: January 29, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Sakurada, Makoto Iida, Nobuaki Mitamura, Atsushi Ozaki
  • Patent number: 7320731
    Abstract: A process for growing a silicon single crystal which is capable of growing a silicon single crystal at a pulling rate which is not lower than the critical pulling rate at which an OSF-generating region will be generated is provided. Such a process for growing a silicon single crystal is characterized by using an atmospheric gas for growing a single crystal which is a hydrogen-containing gas which contains a hydrogen-containing substance, and pulling the silicon single crystal at a pulling rate ranging from a value with which the ratio (a/b) of the diameter (b) of the silicon single crystal and the outer diameter (a) of a ring which consists of the OSF-generating region in the radial direction of the silicon single crystal is not higher than 0.77 to another value with which the OSF-generating region disappears at the center part of the crystal.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: January 22, 2008
    Assignee: Sumco Corporation
    Inventors: Toshiaki Ono, Wataru Sugimura, Masataka Hourai
  • Patent number: 7316745
    Abstract: A high-resistance silicon wafer is manufactured, in which a gettering ability and economical efficiency is excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is to be implemented on the side of a device manufacturer. In order to implement the above, a high-temperature heat treatment at 1100° C. or higher is performed on a carbon doped high-resistance and high-oxygen silicon wafer in which specific resistivity is 100 ?cm or more and a carbon concentration is 5×1015 to 5×1017 atoms/cm3 so that a remaining oxygen concentration becomes 6.5×1017 atoms/cm3 or more (Old-ASTM). As this high-temperature treatment, an OD treatment for forming a DZ layer on a wafer surface, a high-temperature annealing treatment for eliminating a COP on the surface layer, a high-temperature heat treatment for forming a BOX layer in a SIMOX wafer manufacturing process and the like can be used.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: January 8, 2008
    Assignee: Sumco Corporation
    Inventors: Shinsuke Sadamitsu, Nobumitsu Takase, Hiroyuki Takao, Koji Sueoka, Masataka Horai
  • Patent number: 7311888
    Abstract: The present invention provides an annealed wafer which has a wafer surface layer serving as a device fabricating region and having an excellent oxide film dielectric breakdown characteristic, and a wafer bulk layer in which oxide precipitates are present at a high density at the stage before the wafer is loaded into the device fabrication processes to give an excellent IG capability, and a method for manufacturing the annealed wafer. The present invention is directed to an annealed wafer obtained by performing heat treatment on a silicon wafer manufactured from a silicon single crystal grown by the Czochralski method, wherein a good chip yield of an oxide film dielectric breakdown characteristic in a region having at least a depth of up to 5 ?m from a wafer surface is 95% or more, and a density of oxide precipitates detectable in the wafer bulk and each having a size not smaller than a size showing a gettering capability is not less than 1×109/cm3.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: December 25, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Takeno, Masahiro Sakurada, Takeshi Kobayashi
  • Patent number: 7300517
    Abstract: A manufacturing method of a hydrogen-doped silicon single crystal. A silicon single crystal is grown under an inert atmosphere containing hydrogen in a CZ pulling furnace comprising a pull chamber connected to a main chamber. At least one portion of a mixed gas composed of a hydrogen gas and an inert gas to be introduced into the CZ pulling furnace is supplied directly to a surface of a silicon melt in the main chamber, preferably to adjacent parts to a solid-liquid interface of the surface thereof, or in the silicon melt.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: November 27, 2007
    Assignee: Sumco Corporation
    Inventors: Wataru Sugimura, Masataka Hourai
  • Patent number: 7294196
    Abstract: In a method for producing a silicon single crystal by Czochralski method, the single crystal is grown with controlling a growth rate between a growth rate at a boundary where a defect region detected by Cu deposition remaining after disappearance of OSF ring disappears when gradually decreasing a growth rate of silicon single crystal during pulling and a growth rate at a boundary where a high oxygen precipitation Nv region having a density of BMDs of 1×107 numbers/cm3 or more and/or a wafer lifetime of 30 ?sec or less after oxygen precipitation treatment disappears when gradually decreasing the growth rate further. Thereby, there is provided a silicon single crystal which does not belong to any of V region rich in vacancy, OSF region and I region rich in interstitial silicon, and has excellent electrical characteristics and gettering capability, so that yield of devices can be surely improved, and also an epitaxial wafer.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: November 13, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Sakurada, Nobuaki Mitamura, Izumi Fusegawa, Tomohiko Ohta
  • Patent number: 7291220
    Abstract: A silicon wafer made by the Czochralski method, including a ring-shaped OSF region and having nitrogen concentration ranging from 2.9×1014 to 5.0×1015 atoms/cm3 and oxygen concentration of 1.27×1018 to 3.0×1018 atoms/cm3 is heat-treated in a reducing-gas or inert-gas atmosphere, by increasing the temperature at the rate of 0.5° C./min to 2.0° C./min until the wafer is heated to a heat-treatment temperature of 1000 to 1200° C.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: November 6, 2007
    Assignee: Covalent Materials Corporation
    Inventor: Yumiko Hirano
  • Patent number: 7282094
    Abstract: To precisely predict the distribution of densities and sizes of void defects comprising voids and inner wall oxide membranes in a single crystal. The computer-based simulation determines, at steps 1 to 7, the distribution of temperatures within a single crystal 14 growing from a melt 12 from the time of its pulling-up to the time of its completing cooling with due consideration paid to convection currents in the melt 12. The computer-based simulation, at steps 8 to 15, determines the density of voids considering the cooling process of the single crystal separated from the melt, that is, the pulling-up speed of the single crystal after the separation from the melt, and reflecting the effect of slow and rapid cooling of the single crystal in the result, and relates the radius of voids with the thickness of inner wall oxide membrane developed around the voids.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: October 16, 2007
    Assignee: Sumco Corporation
    Inventors: Kounosuke Kitamura, Jun Furukawa, Naoki Ono
  • Patent number: 7270706
    Abstract: A single roll crusher for comminuting high purity materials includes a roll with teeth spaced around the circumference of the roll. The roll is rotatably mounted inside a housing. The housing has a top with an entrance port, sides, and bottom with an exit port. The roll, teeth, and at least the inside surfaces of the top, sides, and bottom are fabricated from a material of construction that minimizes contamination of silicon. The material of construction may be tungsten carbide with a cobalt binder. The single roll crusher is used for processing polycrystalline silicon.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: September 18, 2007
    Assignee: Dow Corning Corporation
    Inventors: Douglas Andrejewski, Thomas Dubay, Terence Lee Horstman, Roger Dale Spencer, Jr.
  • Patent number: 7258739
    Abstract: Firstly, a silicon ingot in which boron and germanium were doped is sliced to prepare a silicon wafer and then the wafer is thermally processed by oxidation to form the thermal oxidation film on the surface layer portion of the wafer. Thereby, the concentration of germanium is enhanced in the vicinity of the interface with the thermal oxidation film of the wafer. Then, the thermal oxidation film is removed from the surface layer portion of the wafer. Further, an epitaxial layer consisting of a silicon single crystal in which a lower concentration of boron than the concentration of boron in the wafer was doped is grown on the shallow surface layer portion of the wafer by an epitaxial growth method. According to the present invention, the doping amount of germanium is reduced and the generation of misfit dislocations is suppressed.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: August 21, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Toshiaki Ono, Masataka Hourai
  • Patent number: 7258744
    Abstract: The present invention discloses a graphite heater for producing a single crystal used when producing a single crystal by the Czochralski method which comprises at least a terminal part to which electric current is supplied and a cylindrical heat generating part by resistance heating and are provided so as to surround a crucible for containing a raw material melt wherein the heat generating part has heat generating slit parts formed by being provided with upper slits extending downward from the upper end and lower slits extending upwards from the lower end by turns, and a length of at least one slit of the upper slits differs from others and/or a length of at least one slit of the lower slits differs from others so that a heat generating distribution of the heat generating part may be changed.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: August 21, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Sakurada, Izumi Fusegawa, Satoshi Soeta, Makoto Iida
  • Patent number: 7255740
    Abstract: A method is described for making low-stress single crystals with a hexagonal crystal structure, which has a crystallographic c-axis perpendicular to a [0001] surface. A single crystal maintained at a temperature under the melting point of the crystal raw material is dipped in a melt of the crystal raw material, whereby a solid-liquid phase boundary is formed. The crystal is subsequently drawn with an upwardly directed drawing motion e.g. by the Czochralski method. The method is characterized by drawing the crystal along the c-axis so that a temperature gradient of at least 30 K/cm is present in the crystal within a centimeter of the solid-liquid phase boundary and by subsequently performing a tempering treatment on the resulting single crystal. The method is especially suitable for corundum crystals, such as sapphire, which are used as substrates for semiconductor components, such as LEDs.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: August 14, 2007
    Assignee: Schott AG
    Inventors: Dirk Sprenger, Burkhard Speit, Markus Schweizer
  • Patent number: 7244306
    Abstract: A single crystal ingot is cut to an axial direction so as to including the central axis, a sample for measurement including regions [V], [Pv], [Pi] and [I] is prepared, and a first sample and second sample are prepared by dividing the sample into two so as to be symmetrical against the central axis. A first transition metal is metal-stained on the surface of the first sample and a second transition metal different from the first transition metal is metal-stained on the surface of the second sample. The first and second samples stained with the metals are thermally treated and the first and second transition metals are diffused into the inside of the samples. Recombination lifetimes in the whole of the first and second samples are respectively measured, and the vertical measurement of the first sample is overlapped on the vertical measurement of the second sample.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: July 17, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Kazunari Kurita, Jun Furukawa
  • Patent number: 7232484
    Abstract: Semiconductor materials such as silicon particles are doped by mixing the semiconductor material with a solution having a dopan and a solvent. The solvent is removed from the wetted surface of the particles of the semiconductor material, thereby yielding particles that are substantially free from the solvent and are uniformly coated with the dopant.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 19, 2007
    Assignee: Evergreen Solar Inc.
    Inventors: Mary C. Cretella, Richard L. Wallace, Jr.
  • Patent number: 7229496
    Abstract: A thermal processing operation is performed for a silicon wafer W (silicon single-crystal layer) in an atmosphere gas which is formed by a hydrogen gas or an inert gas or a mixture gas of these gases at a temperature in a range of 600° C. to 950° C. (here, the temperature should not be greater than 950° C.). By doing this, a quality of a surface of the silicon single-crystal layer is improved.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: June 12, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Takashi Shibayama, Yoshio Murakami, Takayuki Shingyoji
  • Patent number: 7229495
    Abstract: A method for growing a silicon single crystal ingot by a Czochralski method, which is capable of providing silicon wafers having very uniform in-plane quality and which results in improvement of semiconductor device yield. A method is provided for producing a silicon single crystal ingot by a Czochralski method, wherein when convection distribution of a silicon melt is divided into a core cell and an outer cell, the silicon single crystal ingot is grown under the condition that the maximal horizontal direction width of the core cell is 30 to 60% of a surface radius of the silicon melt. In one embodiment the silicon single crystal ingot is grown under the condition that the maximal vertical direction depth of the core cell is equal to or more than 50% of the maximal depth of the silicon melt.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: June 12, 2007
    Assignee: Siltron Inc.
    Inventors: Hyon-Jong Cho, Cheol-Woo Lee, Hong-Woo Lee, Jin Soo Cheong, Sunmi Kim
  • Patent number: 7226507
    Abstract: The present invention is a method for producing a single crystal of which a whole plane in a radial direction is a defect-free region with pulling the single crystal from a raw material melt in a chamber by Czochralski method, wherein a pulling condition is changed in a direction of the crystal growth axis during pulling the single crystal so that a margin of a pulling rate is always a predetermined value or more that the single crystal of which the whole plane in a radial direction is a defect-free region can be pulled. Thereby, there can be provided a method for producing a single crystal in which when a single crystal is produced by CZ method, the single crystal of which a whole plane in a radial direction is a defect-free region entirely in a direction of the crystal growth axis can be produced with stability.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: June 5, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Nobuaki Mitamura, Tomohiko Ohta, Izumi Fusegawa, Masahiro Sakurada, Atsushi Ozaki
  • Patent number: 7226505
    Abstract: A method for eliminating defects in single crystal silicon, which comprises subjecting single crystal silicon prepared by the CZ method to an oxidation treatment and then to an ultra high temperature heat treatment at a temperature of at least 1300° C., or comprises subjecting single crystal silicon which is prepared by the CZ method and is not subjected to an oxidation treatment (a bare wafer) to an ultra high temperature heat treatment in an oxygen atmosphere and at a temperature of higher than 1200° C. and lower than 1310° C. The method allows the elimination of void defects present in single crystal silicon with reliability.
    Type: Grant
    Filed: December 25, 2002
    Date of Patent: June 5, 2007
    Assignee: Sumco Techxiv Corporation
    Inventors: Masahiko Ando, Masaru Yuyama, Shiro Yoshino
  • Patent number: 7226571
    Abstract: A high resistivity p type silicon wafer with a resistivity of 100 ?cm or more, in the vicinity of the surface being formed denuded zone, wherein when a heat treatment in the device fabrication process is performed, a p/n type conversion layer due to thermal donor generation is located at a depth to be brought into contact with neither any device active region nor depletion layer region formed in contact therewith or at a depth more than 8 ?m from the surface, and a method for fabricating the same. The high resistivity silicon wafer can cause the influence of thermal donors to disappear without reducing the soluble oxygen concentration in the wafer, whereby even if various heat treatments are performed in the device fabrication process, devices such as CMOS that offer superior characteristics can be fabricated. The wafer has wide application as a substrate for a high-frequency integrated circuit device.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: June 5, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Nobumitsu Takase, Shinsuke Sadamitsu, Takayuki Kihara, Masataka Hourai
  • Patent number: 7220308
    Abstract: To suppress a fluctuation in resistivity around a target value to thereby stably manufacture high resistivity silicon single crystals having almost the same resistivity values in a manufacturing method wherein a silicon raw material is molten to manufacture a high resistivity silicon single crystal in the range of from 100 to 2000 ? cm with a CZ method. In a case where poly-silicon produced with a Siemens method using trichlorosilane as raw material is used as the silicon raw material, an impurity concentration in the silicon raw material is selected so as to be controlled in the range of from ?5 to 50 ppta method in terms of (a donor concentration—an acceptor concentration) and the selected poly-silicon is used. In a case of a MCZ method, the poly-silicon is selected in the range of from ?25 to 20 ppta and the selected poly-silicon is used. Instead of the raw material, poly-silicon produced with a Siemens method using monosilane as raw material is used.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: May 22, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Nobumitsu Takase, Hideshi Nishikawa, Makoto Ito, Koujl Sueoka, Shinsuke Sadamitsu
  • Patent number: 7217320
    Abstract: The present invention relates to a process for preparing a single crystal silicon ingot, as well as to the ingot or wafer resulting therefrom. The process comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, and (iii) a cooling rate of the crystal from solidification to about 750° C., in order to cause the formation of a segment having a first axially symmetric region extending radially inward from the lateral surface of the ingot wherein silicon self-interstitials are the predominant intrinsic point defect, and a second axially symmetric region extending radially inward from the first and toward the central axis of the ingot.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: May 15, 2007
    Assignee: MEMC Electronics Materials, Inc.
    Inventors: Chang Bum Kim, Steven L. Kimbel, Jeffrey L. Libbert, Mohsen Banan
  • Patent number: 7214268
    Abstract: The present invention is a method of producing a P(phosphorus)-doped silicon single crystal by Czochralski method, wherein, at least, a growth of the single crystal is performed so that an Al (aluminum) concentration is 2×1012 atoms/cc or more. Thereby, there can be provided a method of easily and inexpensively producing a P(phosphorus)-doped silicon single crystal of defect-free region having an excellent capability of electrical characteristics to be high breakdown voltage, which contains neither, for example, V region, OSF region, nor large dislocation cluster (LSEPD, LFPD) region.
    Type: Grant
    Filed: December 25, 2003
    Date of Patent: May 8, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Sakurada, Izumi Fusegawa
  • Patent number: 7214267
    Abstract: A silicon single crystal and a method for growing a silicon single crystal are provided. A p-type silicon single crystal is grown with a uniform resistivity value in a pulling direction. Pulling is conducted by the Czochralski method from molten silicon obtained by adding phosphorus to an initial melt in an amount equivalent to 25˜35% of an absolute concentration (atoms/cc) of boron contained in the melt.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: May 8, 2007
    Assignee: Sumitomo Mitsubishi Silicon
    Inventor: Koji Kato
  • Patent number: 7211141
    Abstract: The present invention is a method for producing a wafer comprising, at least, a BMD forming step of subjecting a silicon single crystal in a state of an ingot to heat treatment thereby to form bulk micro defects (BMDs) inside, and a wafer processing step of processing the ingot in which the bulk micro defects (BMDs) was formed into wafers. Thereby, there can be provided a method for producing a wafer, wherein heat treatment for providing IG capability in production of wafer can be shortened and wafers with high IG capability can be produced in large quantity. Also, the present invention can further comprise a wafer heat-treating step of subjecting the processed wafer to heat treatment, or an epitaxial growth step of forming an epitaxial layer on the wafer. Thereby, there is improved productivity of annealed wafers or epitaxial wafers that are excellent in gettering capability.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: May 1, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Takeshi Kobayashi
  • Patent number: 7208043
    Abstract: A silicon semiconductor substrate has a structure possessing oxygen precipitate defects fated to form gettering sites in a high density directly below the defect-free region of void type crystals. The silicon semiconductor substrate is formed by heat-treating a silicon semiconductor substrate derived from a silicon single crystal grown by the Czochralski method or the magnetic field-applied Czochralski method and characterized by satisfying the relational expression (Oi DZ)?(COP DZ)?10 ?m wherein Oi DZ denotes a defect-free zone of oxygen precipitate crystal defects and COP DZ denotes a region devoid of a void type defect measuring not less than 0.11 ?m in size, and having not less than 5×108 oxygen precipitate crystal defects per cm3.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: April 24, 2007
    Assignee: Siltronic AG
    Inventors: Akiyoshi Tachikawa, Atsushi Ikari
  • Patent number: 7208042
    Abstract: A silicon single crystal ingot is pulled at a pull rate so that the interior of the ingot results in a perfect region in which agglomerates of interstitial silicon-type point defects and agglomerates of vacancy-type point defects are absent, while rotating a quartz crucible for storing a silicon melt at a predetermined rotation speed and rotating the ingot pulled from the silicon melt in the opposite direction to the rotation of the quartz crucible at a predetermined rotation speed. An average rotation speed CRTAV of the quartz crucible during the pulling of a top ingot portion is set to be faster than an average rotation speed CRTAV of the quartz crucible during the pulling of a bottom ingot portion of the silicon single crystal ingot.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 24, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Kazuhiro Harada, Yoji Suzuki, Hidenobu Abe
  • Patent number: 7204881
    Abstract: There are disclosed a silicon wafer for epitaxial growth wherein the wafer is produced by slicing a silicon single crystal grown with doping nitrogen according to the Czochralski method (CZ method) in the region where at least the center of the wafer becomes V region in which the void type defects are generated, and wherein the number of defects having an opening size of 20 nm or less among the void type defects appearing on the surface of the wafer is 0.02/cm2 or less, and an epitalial wafer wherein an epitaxial layer is formed on the silicon wafer for epitaxial growth. Thereby, there can be produced an epitaxial wafer having a high gettering capability wherein very few SF exist in the epitaxial layer easily at high productivity and at low cost.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: April 17, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Ryoji Hoshi, Susumu Sonokawa
  • Patent number: 7201800
    Abstract: A process for imparting controlled oxygen precipitation behavior to a single crystal silicon wafer. Specifically, prior to formation of the oxygen precipitates, the wafer bulk comprises dopant stabilized oxygen precipitate nucleation centers. The dopant is selected from a group consisting of nitrogen and carbon, and the concentration of the dopant is sufficient to allow the oxygen precipitate nucleation centers to withstand thermal processing, such as an epitaxial deposition process, while maintaining the ability to dissolve any grown-in nucleation centers.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: April 10, 2007
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Jeffrey L. Libbert, Richard J. Phillips, Milind Kulkarni, Mohsen Banan, Stephen J. Brunkhorst
  • Patent number: 7195669
    Abstract: A silicon single crystal rod (24) is pulled from a silicon melt (13) made molten by a heater (17), and a change in diameter of the silicon single crystal rod every predetermined time is fed back to a pulling speed of the silicon single crystal rod and a temperature of the heater, thereby controlling a diameter of the silicon single crystal rod. A PID control in which a PID constant is changed on a plurality of stages is applied to a method which controls the pulling speed of the silicon single crystal rod so that the silicon single crystal rod has a target diameter and a method which controls a heater temperature so that the silicon single crystal rod has the target temperature. A set pulling speed for the silicon single crystal rod is set so that V/G becomes constant, and an actual pulling speed is accurately controlled so as to match with the set pulling speed, thereby suppressing a fluctuation in diameter of the single crystal rod.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: March 27, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Daisuke Wakabayashi, Masao Saito, Satoshi Sato, Jun Furukawa, Kounosuke Kitamura
  • Patent number: 7182809
    Abstract: A single crystal silicon, ingot or wafer form, which contains an axially symmetric region in which vacancies are the predominant intrinsic point defect, is substantially free of oxidation induced stacking faults and is nitrogen doped to stabilize oxygen precipitation nuclei therein, and a process for the preparation thereof.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: February 27, 2007
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Hiroyo Haga, Takaaki Aoshima, Mohsen Banan
  • Patent number: 7160387
    Abstract: This invention provides a high purity silica crucible having low impurity concentration in its inner portion, and its production method. The crucible, in which at least each content of Na and Li being contained in the depth of 1 mm from the inside surface is less than 0.05 ppm, is given by a production method of a high purity silica glass crucible, wherein a purity of the melted silica powder layer is increased by applying a voltage between a mold and an arc electrode to move impurity metals being contained in the melted silica glass layer to the outside, when the silica crucible is produced by arc plasma heating a raw material powder of silica in an inside surface of a hollow rotary mold. The method comprises, keeping an arc electrode potential of within ±500 V during an arc melting, applying a voltage of from ?1000 V to ?20000 V to a mold being insulated to the ground, and applying a high voltage to the un-melted silica powder layer of the outside.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: January 9, 2007
    Assignee: Japan Super Quartz Corporation
    Inventors: Hiroshi Kishi, Masanori Fukui, Yoshiyuki Tsuji
  • Patent number: 7147710
    Abstract: There is described a method which enables stable manufacture of a high-quality, ultra-thin epitaxial silicon wafer, as well as an epitaxial silicon wafer capable of bearing shipment manufactured by the method. A method of manufacturing an epitaxial silicon wafer having an ultra-thin epitaxial film, by means of forming an epitaxial film on a silicon wafer after having annealed the silicon wafer, includes the steps of: sufficiently smoothing COPs formed in the surface of the silicon wafer by means of appropriately setting annealing conditions according to an size of COPs in the vicinity of a surface of the silicon wafer; and forming an epitaxial film through epitaxial growth.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: December 12, 2006
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Kazuya Togashi, Masayoshi Danbata, Kuniaki Arai, Kaori Matsumoto
  • Patent number: 7141113
    Abstract: A method for growing a silicon crystal by a Czochralsky method, wherein, let a pulling speed be V (mm/min) and an average value of an in-crystal temperature gradient in a pulling axis direction within a temperature range, a silicon melting point to 1350° C., be G (° C./mm), V/G ranges from 0.16 to 0.18 mm2/° C. min between a crystal center position and a crystal outer periphery position, and a ratio G outer/G center of an average value G of an in-crystal temperature gradient in a pulling axis direction within a temperature range, a silicon melting point to 1350° C., at a crystal outer surface to that at a crystal center is set to up to 1.10 to thereby obtain a high-quality perfect crystal silicon wafer. Such a perfect crystal silicon wafer, wherein an oxygen concentration is controlled to up to 13×1017 atoms/cm3, an initial heat treatment temperature is at least up to 500° C. and a temperature is raised at up to 1° C./min at least within 700 to 900° C.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: November 28, 2006
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Kozo Nakamura, Toshiaki Saishoji, Hirotaka Nakajima, Shinya Sadohara, Masashi Nishimura, Toshirou Kotooka, Yoshiyuki Shimanuki
  • Patent number: 7125450
    Abstract: The present invention is directed to a process for preparing single crystal silicon, in ingot or wafer form, wherein crucible rotation is utilized to control the average axial temperature gradient in the crystal, G0, as a function of radius (i.e., G0(r)), particularly at or near the central axis. Additionally, crucible rotation modulation is utilized to obtain an axially uniform oxygen content therein.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: October 24, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Zheng Lu, Steven L. Kimbel, Ying Tao
  • Patent number: 7122082
    Abstract: A silicon wafer wherein stacking fault (SF) nuclei are distributed throughout the entire in-plane direction, and the density of the stacking fault nuclei is set to a range of between 0.5×108 cm?3 and 1×1011 cm?3.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: October 17, 2006
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Takaaki Shiota, Yoshinobu Nakada
  • Patent number: 7105050
    Abstract: A process for the preparation of a silicon single ingot in accordance with the Czochralski method. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C. to initially produce in the constant diameter portion of the ingot a series of predominant intrinsic point defects including vacancy dominated regions and silicon self interstitial dominated regions, alternating along the axis, and cooling the regions from the temperature of solidification at a rate which allows silicon self-interstitial atoms to diffuse radially to the lateral surface and to diffuse axially to vacancy dominated regions to reduce the concentration intrinsic point defects in each region.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: September 12, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Vladimir V. Voronkov, Robert J. Falster, Mohsen Banan
  • Patent number: 7097707
    Abstract: A method of making a single crystal GaN boule, comprising contacting a GaN seed wafer with a GaN source environment under process conditions including a thermal gradient in the GaN source environment producing growth of gallium nitride on the GaN seed wafer, thereby forming the GaN boule. The GaN source environment in various implementations includes gallium melt in an ambient atmosphere of nitrogen or ammonia, or alternatively, supercritical ammonia containing solubilized GaN. The method produces single crystal GaN boules >10 millimeters in diameter, of device quality suitable for production of GaN wafers useful in the fabrication of microelectronic, optoelectronic and microelectromechanical devices and device precursor structures therefor.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: August 29, 2006
    Assignee: Cree, Inc.
    Inventor: Xueping Xu
  • Patent number: 7097718
    Abstract: Epitaxial wafers comprising a single crystal silicon substrate comprising agglomerated vacancy defects and having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated intrinsic point defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: August 29, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
  • Patent number: 7083677
    Abstract: Using a seed crystal comprising a silicon single crystal not including a vacancy excess region, a neck comprising a silicon single crystal not including a vacancy excess region is grown with a diameter contracted smaller than, or equal to that of the contact surface of the silicon seed crystal in contact with a raw material silicon melt, and necking is performed so that the length L of the neck satisfies L?d·(cot ?), where d denotes the length of the diameter or the diagonal of the contact surface of the silicon seed crystal in contact with the raw material silicon melt, and ? denotes the angle formed between the propagation direction of dislocations and the growth direction of the neck, and then the silicon single crystal is grown with the diameter expanded.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: August 1, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventor: Masayuki Watanabe
  • Patent number: 7074271
    Abstract: A surface of a reference sample is contaminated with a transition metal, and a heat treatment is performed to diffuse the transition metal in the sample. A concentration of recombination centers formed by the transition metal is measured in the entire heat-treated reference sample, and a region [V], a region [Pv], a region [Pi], and a region [I] in the reference sample are defined based on the values measured. Meanwhile, recombination lifetimes associated with the transition metal are measured in the entire heat-treated reference sample. Based on both of the measurement results, a correlation line of the concentration of recombination centers and the recombination lifetimes is produced. A surface of the measurement sample is contaminated with the transition metal, and a heat treatment is performed to diffuse the transition metal in the sample.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: July 11, 2006
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Jun Furukawa, Kazunari Kurita, Kazuhiro Harada
  • Patent number: 7070649
    Abstract: A process for producing a doped silicon single crystal, comprising after-doping the melt during the pulling process with a quantity of volatile dopant ?N(t), calculated according to the equation ?N(t)=N0?N(t)=N0·(1?e??a·t) or according to the approximation equation ?N(t)=N0·?a·t where ?a is an evaporation coefficient which describes process-specific evaporation behavior of the foreign substance and which is obtained after a resistance profile R(t) of a further single crystal has been measured and calculated according to the equation R(t)=R0·e?a·t, where R0 is a starting resistivity and the further single crystal is pulled under the same process conditions without being after-doped with the foreign substance.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: July 4, 2006
    Assignee: Siltronic AG
    Inventors: Martin Weber, Peter Vilzmann, Erich Gmeilbauer, Robert Vorbuchner
  • Patent number: 7048796
    Abstract: At the time of fabricating a silicon single crystal wafer from a nitrogen-doped silicon single crystal grown according to the Czochralski method, a silicon single crystal wafer covered with a region in which an oxygen precipitation bulk micro defect and an oxidation induced stacking fault mixedly exist is subjected to heat treatment at a temperature of 1100 to 1300° C. in a reducing gas or inert gas atmosphere. In such a manner, a method of fabricating a high-quality silicon single crystal wafer and a silicon single crystal wafer in which no grown-in crystal defects exist in the whole surface and oxygen precipitation bulk micro defects (BMD) are formed at a sufficiently high density to display the IG effect on the inner side can be provided. The single crystal wafer can be suitably used to form an operation region of a semiconductor device.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: May 23, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Masayuki Watanabe, Junichi Osanai, Akihiko Kobayashi, Kazuhiko Kashima, Hiroyuki Fujimori
  • Patent number: RE39173
    Abstract: A method of making silicon single crystal wafers free of grown-in defects is provided. These wafers are formed from silicon single crystal manufactured by the Czochralski method. Careful control of the pulling rate, V (mm/min), and the temperature gradient G (° C./mm) permits crystals to be formed that are free from OSF rings, and other types of defects.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: July 11, 2006
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Masataka Hourai, Eiji Kajita