With A Step Of Measuring, Testing, Or Sensing Patents (Class 117/85)
  • Patent number: 11190132
    Abstract: A photocurrent scanning system comprises a laser generating device, a focusing device, a displacement adjustment device, a bias supply device, and a measuring device. The laser generating device is used to emit a laser. The focusing device is used to focus the laser to a surface of a sample. The displacement adjustment device is used to place the sample and adjust a position of the sample, to make the laser focused onto different parts of the surface of the sample. The bias supply device is used to supply a voltage to the sample. The measuring device is used to measure a photocurrent signal flowing through the sample.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 30, 2021
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ke Zhang, Yang Wei, Shou-Shan Fan
  • Patent number: 10790144
    Abstract: A method for preparing a device having a film on a substrate is disclosed. In the method, a film is deposited on a substrate. The film includes a single-crystalline or poly-crystalline semiconducting thin film. The single-crystalline or poly-crystalline semiconducting thin film is formed by sequential evaporation of a first and a second element. One example device prepared by the method includes a silicon substrate and a film on the substrate, wherein the film includes semiconducting and single- or poly-crystalline pyrite as the compound.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 29, 2020
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Nathan Newman, Mahmoud Vahidi, Stephen Lehner, Peter Buseck
  • Patent number: 10761021
    Abstract: A method of identifying the material and determining the physical thickness of each layer in a multilayer structure is disclosed. The method includes measuring the optical thickness of each of the layers of the multilayer object as a function of wavelength of a light source and calculating a normalized group index of refraction dispersion curve for each layer in the multilayer structure. The measured normalized group index of refraction dispersion curves for each of the layers is then compared to a reference database of known materials and the material of each layer is identified. The physical thickness of each layer is then determined from the group index of refraction dispersion curve for the material in each layer and the measured optical thickness data. A method for determining the group index of refraction dispersion curve of a known material, and an apparatus for performing the methods are also disclosed.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 1, 2020
    Assignee: Lumetrics, Inc.
    Inventors: Michael A. Marcus, Kyle J. Hadcock, Donald S. Gibson, Filipp V. Ignatovich
  • Patent number: 10550465
    Abstract: As a process of preparing for a restart of an epitaxial reactor in which epitaxial growth for a wafer is performed, an embodiment includes injecting a nitrogen gas into a process chamber provided in the epitaxial reactor and purging the gas for a predetermined time; heating the inside of the process chamber non-linearly according to time; and measuring MCLT for the epitaxial wafer after growing the epitaxial wafer. A method of preparing for a restart of an epitaxial reactor of the embodiment removes moisture and contaminants stagnated inside the process chamber at a higher rate compared to the related art and also reduces a time to reach the minimum value of MCLT for preparing for a restart of an epitaxial reactor, and thus a time for preparing for a restart of an epitaxial reactor may also be reduced.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: February 4, 2020
    Assignee: SK Siltron Co., Ltd.
    Inventors: Dong-Ho Kang, Man-Kee Cho
  • Patent number: 10365672
    Abstract: A system includes a cooling device, a memory, and a processor. The cooling device is configured to detect a temperature of a wafer and to provide air to the wafer. The memory is configured to store computer program codes. The processor is configured to execute the computer program codes in the memory to: determine whether the temperature of the wafer meet a predetermined requirement; adjust the temperature of the wafer on condition that the temperature does not meet the predetermined requirement; and control the cooling device to detect the temperature of the wafer again, in order to verify whether an adjusted temperature of the wafer meet predetermined requirement.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Han Chen, Sheng-Hung Lin, Han-Hsuan Hsu, Chien-Fang Lin
  • Patent number: 10190977
    Abstract: A method of identifying the material and determining the physical thickness of each layer in a multilayer structure is disclosed. The method includes measuring the optical thickness of each of the layers of the multilayer object as a function of wavelength of a light source and calculating a normalized group index of refraction dispersion curve for each layer in the multilayer structure. The measured normalized group index of refraction dispersion curves for each of the layers is then compared to a reference data base of known materials and the material of each layer is identified. The physical thickness of each layer is then determined from the group index of refraction dispersion curve for the material in each layer and the measured optical thickness data. A method for determining the group index of refraction dispersion curve of a known material is also disclosed.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: January 29, 2019
    Assignee: LUMETRICS, INC.
    Inventors: Michael A. Marcus, Donald S. Gibson, Kyle J. Hadcock, Filipp V. Ignatovich
  • Patent number: 10103288
    Abstract: Apparatus and method for control of epitaxial growth parameters, for example during manufacture of light emitting diodes (LEDs). Embodiments include PL measurement of a group III-V film following growth while a substrate at an elevated temperature is in a transfer chamber of a multi-chamber cluster tool. In other embodiments, a film thickness measurement, a contactless resistivity measurement, and a particle and/or roughness measure is performed while the substrate is disposed in the transfer chamber. One or more of the measurements performed in the transfer chamber are temperature corrected to room temperature by estimating the elevated temperature based on emission from a GaN base layer disposed below the group III-V film. In other embodiments, temperature correction is based on an absorbance band edge of the GaN base layer determined from collected white light reflectance spectra. Temperature corrected metrology is then used to control growth processes.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 16, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: David P. Bour, Alain Duboust, Alexey Goder
  • Patent number: 9649256
    Abstract: A method and a device for monitoring a property of a coating of a solid dosage form during a coating process forming the coating of the solid dosage form are provided. The device comprises a coating apparatus configured for forming the coating on the solid dosage form, and a monitoring apparatus configured for monitoring the property of the coating of the solid dosage form in process, wherein at least a part of the monitoring apparatus is located so as to have insight in an interior of the coating apparatus, the interior accommodating the solid dosage form to be coated and a precursor for forming the coating, and wherein the monitoring apparatus is configured for monitoring the property of the coating of the solid dosage form simultaneously with and during a coating process using low coherence interferometry.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: May 16, 2017
    Assignees: Research Center Pharmaceutical Engineering GmbH, Research Center for Non Destructive Testing GmbH
    Inventors: Daniel Markl, Guenther Hannesschlaeger, Michael Leitner, Stephan Sacher, Daniel Koller, Johannes Khinast
  • Patent number: 9401404
    Abstract: A semiconductor device is disclosed comprising: a substrate having a surface comprising germanium; a layer of gallium on said surface; and a layer of gallium arsenide on the gallium covered surface. The semiconductor heterostructure of gallium arsenide on germanium is fabricated by the steps of: protecting by a shutter a surface comprising germanium in an environment having a partial pressure of arsenic less than 10?8torr; epitaxially growing a layer of gallium on the said surface immediately after exposure of said surface; and epitaxially growing a layer of gallium arsenide on the gallium covered surface.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: July 26, 2016
    Assignee: UCL BUSINESS PLC
    Inventors: Huiyun Liu, Alwyn John Seeds, Francesca Pozzi
  • Patent number: 9082621
    Abstract: Each of first and second material substrates made of single crystal silicon carbide has first and second back surfaces, first and second side surfaces, and first and second front surfaces. The first and second back surfaces are connected to a supporting portion. The first and second side surfaces face each other with a gap interposed therebetween, the gap having an opening between the first and second front surfaces. A closing portion for closing the gap over the opening is formed. A connecting portion for closing the opening is formed by depositing a sublimate from the first and second side surfaces onto the closing portion. The closing portion is removed. A silicon carbide single crystal is grown on the first and second front surfaces.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 14, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Taro Nishiguchi, Shin Harada, Makoto Sasaki
  • Patent number: 8980000
    Abstract: In a rotating disk reactor for growing epitaxial layers on substrate or other CVD reactor system, gas directed toward the substrates at gas inlets at different radial distances from the axis of rotation of the disk has both substantially the same gas flow rate/velocity and substantially the same gas density at each inlet. The gas directed toward portions of the disk remote from the axis may include a higher concentration of a reactant gas than the gas directed toward portions of the disk close to the axis, so that portions of the substrate surfaces at different distances from the axis receive substantially the same amount of reactant gas per unit area, and a combination of carrier gases with different relative molecular weights at different radial distances from the axis of rotation are employed to substantially make equal the gas density in each region of the reactor.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: March 17, 2015
    Assignee: Veeco Instruments Inc.
    Inventors: Bojan Mitrovic, Alex Gurary, William Quinn, Eric A. Armour
  • Patent number: 8940093
    Abstract: A method of controlling an epitaxial growth process in an epitaxial reactor. The method includes optimizing the thermocouple offset parameter for a second run by setting up a modeled output parameter value as a linear function of the actual output parameter value, and a second thermocouple offset parameter value.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Manfred Schiekofer, Pietro Foglietti, Robert Maier
  • Publication number: 20150010726
    Abstract: Quality of a silicon carbide single crystal is improved. A crucible having first and second sides is prepared. A solid source material for growing silicon carbide with a sublimation method is arranged on the first side. A seed crystal made of silicon carbide is arranged on the second side. The crucible is arranged in a heat insulating container. The heat insulating container has an opening facing the second side. The crucible is heated such that the solid source material sublimes. A temperature on the second side is measured through the opening in the heat insulating container. The opening has a tapered inner surface narrowed toward the outside of the heat insulating container.
    Type: Application
    Filed: May 22, 2014
    Publication date: January 8, 2015
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tsubasa HONKE, Kyoko OKITA, Tomohiro KAWASE, Tsutomu HORI
  • Publication number: 20140264348
    Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.
    Inventors: Chun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
  • Publication number: 20140175461
    Abstract: Provided are a SiC epitaxial wafer in which the surface density of stacking faults is reduced, and a manufacturing method thereof. The method for manufacturing such a SiC epitaxial wafer comprises a step of determining a ratio of basal plane dislocations (BPD), which causes stacking faults in a SiC epitaxial film of a prescribed thickness which is formed on a SiC single crystal substrate having an off angle, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, a step of determining an upper limit of surface density of basal plane dislocations on the growth surface of a SiC single crystal substrate used based on the above ratio, and a step of preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio.
    Type: Application
    Filed: September 4, 2012
    Publication date: June 26, 2014
    Applicant: SHOWA DENKO K.K.
    Inventors: Kenji Momose, Michiya Odawara, Daisuke Muto, Yoshiaki Kageshima
  • Publication number: 20140145214
    Abstract: A SiC epitaxial wafer manufacturing method of the present invention includes: manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a surface of a SiC single crystal wafer while supplying a raw material gas into a chamber using a SIC epitaxial wafer manufacturing apparatus; and manufacturing a subsequent SiC epitaxial wafer after measuring a surface density of triangular defects originating from a material piece of an internal member of the chamber on the SiC epitaxial layer of the previously manufactured SiC epitaxial wafer.
    Type: Application
    Filed: July 12, 2012
    Publication date: May 29, 2014
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshiaki Kageshima, Daisuke Muto, Kenji Momose, Yoshihiko Miyasaka
  • Patent number: 8663389
    Abstract: A method and apparatus for depositing III-V material is provided. The apparatus includes a reactor partially enclosed by a selectively permeable membrane 12. A means is provided for generating source vapors, such as a vapor-phase halide of a group III element (IUPAC group 13) within the reactor volume 10, and an additional means is also provided for introducing a vapor-phase hydride of a group V element (IUPAC group 15) into the volume 10. The reaction of the group III halide and the group V hydride on a temperature-controlled substrate 18 within the reactor volume 10 produces crystalline III-V material and hydrogen gas. The hydrogen is preferentially removed from the reactor through the selectively permeable membrane 12, thus avoiding pressure buildup and reaction imbalance. Other gases within the reactor are unable to pass through the selectively permeable membrane.
    Type: Grant
    Filed: May 21, 2011
    Date of Patent: March 4, 2014
    Inventor: Andrew Peter Clarke
  • Patent number: 8658118
    Abstract: An object of the present invention is to provide more inexpensive high purity crystalline silicon which can satisfy not only a quality required to a raw material of silicon for a solar cell but also a part of a quality required to silicon for an up-to-date semiconductor and a production process for the same and provide high purity silicon tetrachloride used for production of high purity crystalline silicon and a production process for the same. The high purity crystalline silicon of the present invention has a boron content of 0.015 ppmw or less and a zinc content of 50 to 1000 ppbw. The production process for high purity crystalline silicon according to the present invention is characterized by that a silicon tetrachloride gas and a zinc gas are supplied to a vertical reactor to react them at 800 to 1200° C.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: February 25, 2014
    Assignees: JNC Corporation, JX Nippon Mining & Metals Corporation, Toho Titanium Co., ltd.
    Inventors: Satoshi Hayashida, Wataru Kato
  • Patent number: 8603243
    Abstract: A method of: supplying sources of carbon and silicon into a chemical vapor deposition chamber; collecting exhaust gases from the chamber; performing mass spectrometry on the exhaust gases; and correlating a partial pressure of a carbon species in the exhaust gases to a carbon:silicon ratio in the chamber.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: December 10, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, Charles R. Eddy, Jr., David Kurt Gaskill
  • Patent number: 8585822
    Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 19, 2013
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Masanori Ikari, Edward Letts
  • Patent number: 8586488
    Abstract: A computer program product and system for configuring J electromagnetic radiation sources (J?2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1?S1|, |W2?S2|, |WI?SI| is about minimized with respect to Pj (j=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 8557043
    Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: October 15, 2013
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Masanori Ikari, Edward Letts
  • Publication number: 20130263776
    Abstract: A method of fabricating a semiconductor processing device includes providing a susceptor including a substantially cylindrical body portion having opposing upper and lower surfaces. The body portion has a diameter larger than a wafer diameter. The method also includes providing a set of holes circumferentially disposed at a first susceptor diameter, the set of holes being evenly spaced with respect to adjacent holes and extending through the upper and lower surfaces in an area. The first susceptor diameter is larger than the wafer diameter, and holes are omitted along the first diameter in a set of predetermined orientations.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: John Allen Pitney, Manabu Hamano
  • Patent number: 8551246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Publication number: 20130239879
    Abstract: A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second port in communication with the lower portion of the chamber. The load lock includes a rack disposed within the chamber and a workpiece holder mounted on a first surface of the rack, wherein the rack and the workpiece holder are movable by an indexer that is capable of selectively moving wafer slots of the rack into communication with the second port. The indexer can also move the rack into an uppermost position, at which the first surface of the boat and the partition sealingly separate the upper portion and the lower portion to define an upper chamber and a lower chamber. Auxiliary processing, such as wafer pre-cleaning, or metrology can be conducted in the upper portion.
    Type: Application
    Filed: May 8, 2013
    Publication date: September 19, 2013
    Applicant: ASM AMERICA, INC.
    Inventors: Ravinder K. Aggarwal, Jeroen Stoutjesdijk, Eric R. Hill, Loring G. Davis, John T. DiSanto
  • Patent number: 8475593
    Abstract: In a crystal preparing device, a crucible holds a mixed molten metal containing alkali metal and group III metal. A container has a container space contacting the mixed molten metal and holds a molten alkali metal between the container space and an outside of the container, the molten alkali metal contacting the container space. A gas supply device supplies nitrogen gas to the container space. A heating device heats the crucible to a crystal growth temperature. The crystal preparing device is provided so that a vapor pressure of the alkali metal which evaporates from the molten alkali metal is substantially equal to a vapor pressure of the alkali metal which evaporates from the mixed molten metal.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: July 2, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Hirokazu Iwata, Seiji Sarayama, Akihiro Fuse
  • Patent number: 8454748
    Abstract: A calculation method for finding the hole mobility or the electron mobility of an organic film. The method includes the steps of: calculating the electron density of a film using semi-empirical quantum molecular dynamics calculations; using the fact that holes and electrons move easily through regions of high electron density to calculate the probability that a hole or an electron will move in an excited state in which an electron is excited from the HOMO (highest occupied molecular orbital) to the LUMO (lowest unoccupied molecular orbital) using a Monte Carlo method; and, using the probability as a performance index, calculating the hole mobility from the number of carriers which exist in the HOMO and the orbitals below the HOMO, or calculating the electron mobility from the number of carriers which exist in the LUMO and the orbitals above the LUMO.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: June 4, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Iwaki, Motoki Nakashima
  • Patent number: 8430959
    Abstract: Disclosed are a method and an apparatus for preparing a polycrystalline silicon rod using a mixed core means, comprising: installing a first core means made of a resistive material together with a second core means made of silicon material in an inner space of a deposition reactor; electrically heating the first core means and pre-heating the second core by the first core means which is electrically heated; electrically heating the preheated second core means; and supplying a reaction gas into the inner space in a state where the first core means and the second core means are electrically heated for silicon deposition.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: April 30, 2013
    Assignee: Korea Research Institute of Chemical Technology
    Inventors: Hee Young Kim, Kyung Koo Yoon, Yong Ki Park, Won Choon Choi, Won Wook So
  • Publication number: 20130098288
    Abstract: The present invention provides a method and a system for forming wires (1) that enables a large scale process combined with a high structural complexity and material quality comparable to wires formed using substrate-based synthesis. The wires (1) are grown from catalytic seed particles (2) suspended in a gas within a reactor. Due to a modular approach wires (1) of different configuration can be formed in a continuous process. In-situ analysis to monitor and/or to sort particles and/or wires formed enables efficient process control.
    Type: Application
    Filed: May 11, 2011
    Publication date: April 25, 2013
    Applicant: QUNANO AB
    Inventors: Lars Samuelson, Martin Magnusson, Knut Deppert, Magnus Heurlin
  • Patent number: 8409349
    Abstract: A film thickness measurement method for measuring a change in film thickness of 0.3 ?m or less in a silicon wafer by FTIR, having an auxiliary film formation step for depositing an auxiliary film for measurement on a surface to be measured for the change in film thickness, an auxiliary film thickness measurement step for measuring the film thickness of the auxiliary film, a measurement step for measuring the film thickness of the auxiliary film after the change in film thickness, and a calculation step for calculating a change in film thickness of a back surface deposit from the result of the measurement step and the result of the auxiliary film thickness measurement step.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: April 2, 2013
    Assignee: Sumco Corporation
    Inventor: Kazuhiro Ohkubo
  • Publication number: 20130071643
    Abstract: A silicon carbide substrate capable of stably forming a device of excellent performance, and a method of manufacturing the same are provided. A silicon carbide substrate is made of a single crystal of silicon carbide, and has a width of not less than 100 mm, a micropipe density of not more than 7 cm?2, a threading screw dislocation density of not more than 1×104 cm?2, a threading edge dislocation density of not more than 1×104 cm?2, a basal plane dislocation density of not more than 1×104 cm?2, a stacking fault density of not more than 0.1 cm?1, a conductive impurity concentration of not less than 1×1018 cm?2, a residual impurity concentration of not more than 1×1016 cm?2, and a secondary phase inclusion density of not more than 1 cm?3.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 21, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HARADA, Shinsuke FUJIWARA, Taro NISHIGUCHI
  • Patent number: 8394197
    Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 12, 2013
    Assignee: Sub-One Technology, Inc.
    Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
  • Patent number: 8394196
    Abstract: Methods for formation epitaxial layers containing silicon and carbon doped with phosphorus are disclosed. The pressure is maintained equal to or above 100 torr during deposition. The methods result in the formation of a film including substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: March 12, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Yihwan Kim
  • Patent number: 8372197
    Abstract: A control system and method for controlling temperatures while performing a MBE deposition process, wherein the control system comprises a MBE growth structure; a heater adapted to provide heat for the MBE deposition process on the MBE growth structure; and a control computer adapted to receive a plurality of dynamic feedback control signals derived from the MBE growth structure; switch among a plurality of control modes corresponding with the plurality of dynamic feedback control signals; and send an output power signal to the heater to control the heating for the MBE deposition process based on a combination of the plurality of control modes. In one embodiment, the plurality of dynamic feedback control signals comprises thermocouple signals and pyrometer signals.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: February 12, 2013
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Stefan P. Svensson
  • Patent number: 8357243
    Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: January 22, 2013
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Masanori Ikari, Edward Letts
  • Patent number: 8354618
    Abstract: A disk processing system with a load chamber having a stationary heater and a movable heater.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: January 15, 2013
    Assignee: WD Media, Inc.
    Inventors: Jinliang Chen, Yew Ming Chiong
  • Publication number: 20130000546
    Abstract: A method of vapor phase epitaxy that is one embodiment of the present invention characteristically includes loading a wafer in a reaction chamber and mounting the wafer on a supporting section; heating the wafer by a heater provided under the supporting section; performing deposition on the wafer by supplying a process gas onto the wafer while rotating the wafer; detecting a temperature distribution at least in a circumferential direction at a peripheral edge section of the wafer; and determining a presence/absence of adhesion between the wafer and the supporting section based on the detected temperature distribution.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 3, 2013
    Inventors: Kunihiko SUZUKI, Shinichi Mitani
  • Patent number: 8216364
    Abstract: Direct resistive heating is used to grow nanotubes out of carbon and other materials. A growth-initiated array of nanotubes is provided using a CVD or ion implantation process. These processes use indirect heating to heat the catalysts to initiate growth. Once growth is initiated, an electrical source is connected between the substrate and a plate above the nanotubes to source electrical current through and resistively heat the nanotubes and their catalysts. A material source supplies the heated catalysts with carbon or another material to continue growth of the array of nanotubes. Once direct heating has commenced, the source of indirect heating can be removed or at least reduced. Because direct resistive heating is more efficient than indirect heating the total power consumption is reduced significantly.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: July 10, 2012
    Assignee: Raytheon Company
    Inventors: Delmar L. Barker, Mead M. Jordan, William R. Owens
  • Publication number: 20120118224
    Abstract: Apparatus and method for control of epitaxial growth parameters, for example during manufacture of light emitting diodes (LEDs). Embodiments include PL measurement of a group III-V film following growth while a substrate at an elevated temperature is in a transfer chamber of a multi-chamber cluster tool. In other embodiments, a film thickness measurement, a contactless resistivity measurement, and a particle and/or roughness measure is performed while the substrate is disposed in the transfer chamber. One or more of the measurements performed in the transfer chamber are temperature corrected to room temperature by estimating the elevated temperature based on emission from a GaN base layer disposed below the group III-V film. In other embodiments, temperature correction is based on an absorbance band edge of the GaN base layer determined from collected white light reflectance spectra. Temperature corrected metrology is then used to control growth processes.
    Type: Application
    Filed: September 12, 2011
    Publication date: May 17, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: David P. Bour, Alain Duboust, Alexey Goder
  • Patent number: 8163573
    Abstract: InyGa1-yN (0<y<1) layers whose principal surface is a non-polar plane or a semi-polar plane are formed by an MOCVD under different growth conditions. Then, the relationship between the growth temperature and the In supply mole fraction in a case where the pressure and the growth rate are constant is determined based on a growth condition employed for formation of InxGa1-xN (0<x<1) layers whose emission wavelengths are equal among the InyGa1-yN layers. Then, a saturation point is determined on a curve representing the relationship between the growth temperature and the In supply mole fraction, the saturation point being between a region where the growth temperature monotonically increases according to an increase of the In supply mole fraction and a region where the growth temperature saturates. Under a growth condition corresponding to this saturation point, an InxGa1-xN layer is grown.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: April 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Shunji Yoshida, Ryou Kato, Toshiya Yokogawa
  • Patent number: 8163085
    Abstract: An apparatus for forming a protective layer of magnesium oxide on a front glass substrate (11) in an evaporation chamber (201) includes the following: oxygen outlet openings (222) for introducing oxygen into the evaporation chamber (201); water vapor outlet openings (210) for introducing water vapor into the evaporation chamber (201) from the downstream side in the transfer direction of the front glass substrate (11); a mass analyzer (224) for measuring the ionic strength of hydrogen and the ionic strength of oxygen in the evaporation chamber (201); and mass flow controllers (215) and (221) for controlling the introduction amount of the water vapor and the introduction amount of the oxygen, respectively, by the ionic strengths measured by the mass analyzer (224).
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: April 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Kazuo Uetani, Kaname Mizokami, Yoshinao Ooe, Akira Shiokawa, Hiroyuki Kado
  • Patent number: 8101020
    Abstract: A crystal growth apparatus comprises a reaction vessel holding a melt mixture containing an alkali metal and a group III metal, a gas supplying apparatus supplying a nitrogen source gas to a vessel space exposed to the melt mixture inside the reaction vessel, a heating unit heating the melt mixture to a crystal growth temperature, and a support unit supporting a seed crystal of a group III nitride crystal inside the melt mixture.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: January 24, 2012
    Assignee: Ricoh Company, Ltd.
    Inventors: Seiji Sarayama, Hirokazu Iwata, Akihiro Fuse
  • Publication number: 20120012047
    Abstract: A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jhi-Cherng LU, Jr-Hung LI, Chii-Horng LI, Pang-Yen TSAI, Bing-Hung CHEN, Tze-Liang LEE
  • Publication number: 20110297076
    Abstract: An apparatus for performing non-contact material characterization includes a wafer carrier adapted to hold a plurality of substrates and a material characterization device, such as a device for performing photoluminescence spectroscopy. The apparatus is adapted to perform non-contact material characterization on at least a portion of the wafer carrier, including the substrates disposed thereon.
    Type: Application
    Filed: August 12, 2011
    Publication date: December 8, 2011
    Applicant: VEECO INSTRUMENTS INC.
    Inventors: Dong Seung Lee, Mikhail Belousov, Eric A. Armour, William E. Quinn
  • Publication number: 20110290175
    Abstract: A multi-chamber CVD system includes a plurality of substrate carriers where each substrate carrier is adapted to support at least one substrate. A plurality of enclosures are each configured to form a deposition chamber enclosing one of the plurality of substrate carriers to maintain an independent chemical vapor deposition process chemistry for performing a processing step. A transport mechanism transports each of the plurality of substrate carriers to each of the plurality of enclosures in discrete steps that allow processing steps to be performed in the plurality of enclosures for a predetermined time. In some embodiments, the substrate carrier can be rotatable.
    Type: Application
    Filed: July 18, 2011
    Publication date: December 1, 2011
    Applicant: VEECO INSTRUMENTS, INC.
    Inventors: Ajit Paranjpe, Eric A. Armour, William E. Quinn
  • Patent number: 8052794
    Abstract: A method for locally controlling the stoichiometry of an epitaxially deposited layer on a semiconductor substrate is provided. The method includes directing a first reactant gas and a doping gas across a top surface of a semiconductor substrate and directing a drive gas and a second reactant gas against the substrate separately from the first reactant gas in a manner that rotates the substrate while introducing the second reactant gas at an edge of the substrate to control each reactant separately, thereby compensating and controlling depletion effects and improving doping uniformity in resulting epitaxial layers on the substrate.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: November 8, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Joseph John Sumakeris, Michael James Paisley, Michael John O'Loughlin
  • Publication number: 20110265710
    Abstract: A film-forming apparatus includes a chamber in which a substrate is to be placed, a reaction gas supply portion that supplies a reaction gas into the chamber, a heater that heats the substrate, a radiation thermometer that is provided outside the chamber to measure the temperature of the substrate by receiving radiant light from the substrate, and a tubular member that protects an optical path of radiant light between the substrate and the radiation thermometer. An inert gas is supplied from an inert gas supply portion to the tubular member. The tubular member preferably has an inner peripheral surface and an outer peripheral surface made of a material having a lower emissivity than the inner peripheral surface.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 3, 2011
    Inventors: Kunihiko Suzuki, Shinichi Mitani, Toshiro Tsumori
  • Patent number: 8029620
    Abstract: In a first aspect, a method is provided for forming an epitaxial layer stack on a substrate. The method includes (1) selecting a target carbon concentration for the epitaxial layer stack; (2) forming a carbon-containing silicon layer on the substrate, the carbon-containing silicon layer having at least one of an initial carbon concentration, a thickness and a deposition time selected based on the selected target carbon concentration; and (3) forming a non-carbon-containing silicon layer on the carbon-containing silicon layer prior to etching. Numerous other aspects are provided.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: October 4, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Yihwan Kim, Zhiyuan Ye, Ali Zojaji
  • Patent number: 8025728
    Abstract: A seed crystal is immersed in a melt containing a flux and a single crystal material in a growth vessel to produce a nitride single crystal on the seed crystal. A difference (TS-TB) of temperatures at a gas-liquid interface of the melt (TS) and at the lowermost part of the melt (TB) is set to 1° C. or larger and 8° C. or lower. Preferably, the substrate of seed crystal is vertically placed.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: September 27, 2011
    Assignees: NGK Insulators, Ltd., Osaka University
    Inventors: Mikiya Ichimura, Katsuhiro Imai, Chikashi Ihara, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
  • Publication number: 20110126759
    Abstract: An apparatus for growing a synthetic diamond comprises a growth chamber, at least one manifold allowing access to the growth chamber, and a plurality of safety clamps positioned on opposite sides of the growth chamber; wherein the growth chamber and the plurality of safety clamps are comprised of a material having a tensile strength of about 120,000-200,000 psi, a yield strength of about 100,000-160,000 psi, an elongation of about 10-20%, an area reduction of about 40-50%, an impact strength of about 30-40 ft-lbs, and a hardness greater than 320 BHN.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 2, 2011
    Applicant: THE GEMESIS CORPORATION
    Inventors: Robert CHODELKA, Hexiang ZHU, Alexander NOVIKOV