With A Step Of Measuring, Testing, Or Sensing Patents (Class 117/85)
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Patent number: 8052794Abstract: A method for locally controlling the stoichiometry of an epitaxially deposited layer on a semiconductor substrate is provided. The method includes directing a first reactant gas and a doping gas across a top surface of a semiconductor substrate and directing a drive gas and a second reactant gas against the substrate separately from the first reactant gas in a manner that rotates the substrate while introducing the second reactant gas at an edge of the substrate to control each reactant separately, thereby compensating and controlling depletion effects and improving doping uniformity in resulting epitaxial layers on the substrate.Type: GrantFiled: September 12, 2005Date of Patent: November 8, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventors: Joseph John Sumakeris, Michael James Paisley, Michael John O'Loughlin
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Publication number: 20110265710Abstract: A film-forming apparatus includes a chamber in which a substrate is to be placed, a reaction gas supply portion that supplies a reaction gas into the chamber, a heater that heats the substrate, a radiation thermometer that is provided outside the chamber to measure the temperature of the substrate by receiving radiant light from the substrate, and a tubular member that protects an optical path of radiant light between the substrate and the radiation thermometer. An inert gas is supplied from an inert gas supply portion to the tubular member. The tubular member preferably has an inner peripheral surface and an outer peripheral surface made of a material having a lower emissivity than the inner peripheral surface.Type: ApplicationFiled: April 28, 2011Publication date: November 3, 2011Inventors: Kunihiko Suzuki, Shinichi Mitani, Toshiro Tsumori
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Patent number: 8029620Abstract: In a first aspect, a method is provided for forming an epitaxial layer stack on a substrate. The method includes (1) selecting a target carbon concentration for the epitaxial layer stack; (2) forming a carbon-containing silicon layer on the substrate, the carbon-containing silicon layer having at least one of an initial carbon concentration, a thickness and a deposition time selected based on the selected target carbon concentration; and (3) forming a non-carbon-containing silicon layer on the carbon-containing silicon layer prior to etching. Numerous other aspects are provided.Type: GrantFiled: July 31, 2007Date of Patent: October 4, 2011Assignee: Applied Materials, Inc.Inventors: Yihwan Kim, Zhiyuan Ye, Ali Zojaji
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Patent number: 8025728Abstract: A seed crystal is immersed in a melt containing a flux and a single crystal material in a growth vessel to produce a nitride single crystal on the seed crystal. A difference (TS-TB) of temperatures at a gas-liquid interface of the melt (TS) and at the lowermost part of the melt (TB) is set to 1° C. or larger and 8° C. or lower. Preferably, the substrate of seed crystal is vertically placed.Type: GrantFiled: September 22, 2008Date of Patent: September 27, 2011Assignees: NGK Insulators, Ltd., Osaka UniversityInventors: Mikiya Ichimura, Katsuhiro Imai, Chikashi Ihara, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
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Publication number: 20110126759Abstract: An apparatus for growing a synthetic diamond comprises a growth chamber, at least one manifold allowing access to the growth chamber, and a plurality of safety clamps positioned on opposite sides of the growth chamber; wherein the growth chamber and the plurality of safety clamps are comprised of a material having a tensile strength of about 120,000-200,000 psi, a yield strength of about 100,000-160,000 psi, an elongation of about 10-20%, an area reduction of about 40-50%, an impact strength of about 30-40 ft-lbs, and a hardness greater than 320 BHN.Type: ApplicationFiled: January 28, 2011Publication date: June 2, 2011Applicant: THE GEMESIS CORPORATIONInventors: Robert CHODELKA, Hexiang ZHU, Alexander NOVIKOV
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Patent number: 7922814Abstract: In the production process of the present invention for high purity polycrystal silicon, using a vertical reactor having a silicon chloride gas-feeding nozzle and a reducing agent gas-feeding nozzle which are disposed at an upper part and a waste gas discharge pipe, a silicon chloride gas and a reducing agent gas are fed into the reactor to form polycrystal silicon at a tip part of the silicon chloride gas-feeding nozzle by the reaction of the silicon chloride gas with the reducing agent gas, and the polycrystal silicon is allowed to grow from the tip part of the silicon chloride gas-feeding nozzle toward a lower part thereof.Type: GrantFiled: November 3, 2006Date of Patent: April 12, 2011Assignee: Chisso CorporationInventors: Shuichi Honda, Minoru Yasueda, Satoshi Hayashida, Masatsugu Yamaguchi, Toru Tanaka
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Patent number: 7846499Abstract: A method of growing a thin film on a substrate by pulsing vapor-phase precursors material into a reaction chamber according to the ALD method. The method comprises vaporizing at least one precursor from a source material container maintained at a vaporising temperature, repeatedly feeding pulses of the vaporized precursor via a feed line into the reaction chamber at a first pressure, and subsequently purging the reaction chamber with pulses of inactive gas fed via the feed line at a second pressure. The second pressure is maintained at the same as or a higher level than the first pressure for separating successive pulses of said vaporized precursor from each other.Type: GrantFiled: December 30, 2004Date of Patent: December 7, 2010Assignee: ASM International N.V.Inventor: Tom E. Blomberg
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Patent number: 7820246Abstract: The present invention provides a method for growing a thin nitride film over a substrate and a thin nitride film device, in which the polarity of the thin nitride film can be controlled by a low temperature process. In the method for growing the thin nitride film over a substrate, a Ga face (2) and a N face (3) are formed over a c face sapphire (Al2O3) substrate (1), the Ga face (2) growing in +c face, and the N face (3) growing in ?c face.Type: GrantFiled: June 15, 2004Date of Patent: October 26, 2010Assignee: Japan Science and Technology AgencyInventors: Masatomo Sumiya, Shunro Fuke
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Patent number: 7790636Abstract: A method for configuring J electromagnetic radiation sources (J?2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1?S1|, |W2?S2, . . . , |WI?SI| is about minimized with respect to Pj=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).Type: GrantFiled: June 29, 2006Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Brent Alan Anderson, Edward Joseph Nowak
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Patent number: 7785414Abstract: A process for manufacturing a wafer of a silicon carbide single crystal having: cutting a wafer from an ? (hexagonal)-silicon carbide single crystal so that the off-angle is totally in the range from 0.4 to 2° to a plane obtained in perpendicular to the [0001]c axis of the silicon carbide single crystal; disposing the wafer in a reaction vessel; feeding a silicon source gas and carbon source gas in the reaction vessel; and epitaxially growing the ? (hexagonal) silicon carbide single crystal on the wafer by allowing the silicon source gas and carbon source gas to react.Type: GrantFiled: May 25, 2005Date of Patent: August 31, 2010Assignee: Bridgestone CorporationInventors: Takayuki Maruyama, Toshimi Chiba
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Patent number: 7776152Abstract: Apparatus and method for growing and observing the growth of epitaxial layers on a wafer. The apparatus includes: epitaxial growth apparatus; a source of light mounted to illuminate an entire surface of the wafer in the apparatus during growth of the epitaxial layer on the entire surface of the wafer; and apparatus for observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The method includes growing the epitaxial layer on a surface of the wafer and observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The growing process is varied in accordance with the observation. With an epitaxial layer of gallium nitride (GaN) the entire surface of the wafer is observed for balls of gallium.Type: GrantFiled: November 1, 2006Date of Patent: August 17, 2010Assignee: Raytheon CompanyInventors: William E. Hoke, Theodore D. Kennedy
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Patent number: 7771532Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: GrantFiled: February 19, 2009Date of Patent: August 10, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
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Patent number: 7754013Abstract: A deposition station allows atomic layer deposition (ALD) of films onto a substrate. The station comprises an upper and a lower substantially flat part between which a substrate is accommodated. The parts are positioned opposite each other and parallel to the substrate during processing. At least one of the parts is provided with a plurality of gas channels that allow at least two mutually reactive reactants to be discharged out of that part to the substrate. The discharge is configured to occur in a sequence of alternating, separated pulses for ALD. In addition, each part is preferably configured to be about 1 mm or less from the substrate to minimize the volume of the reaction chamber to increase the efficiency with which gases are purged from the chamber. Also, for each reactant, the upper and lower parts are preferably kept at a temperature outside of the window in which optimal ALD of that reactant occurs, thereby minimizing deposition of that reactant on deposition station surfaces.Type: GrantFiled: September 25, 2006Date of Patent: July 13, 2010Assignee: ASM International N.V.Inventor: Ernst H. A. Granneman
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Patent number: 7745854Abstract: It is to provide a substrate for growing a semiconductor, which is effective for suppressing an occurrence of surface defects different in type from hillock defects in case of epitaxially growing a compound semiconductor layer, particularly an Al-based compound semiconductor layer. In a substrate for growing a compound semiconductor, in which a crystal surface inclined at a predetermined off angle with respect to a (100) plane is a principal plane, an angle made by a direction of a vector obtained by projecting a normal vector of the principal plane on the (100) plane and one direction of a [0-11] direction, a [01-1] direction, a [011] direction and a [0-1-1] direction is set to be less than 35°, and the compound semiconductor layer is epitaxially grown on the substrate.Type: GrantFiled: February 2, 2007Date of Patent: June 29, 2010Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Hideki Kurita, Ryuichi Hirano
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Patent number: 7731796Abstract: Disclosed herein are a novel nitrogen semiconductor compound simultaneously including groups with different electrical properties and a device fabricated using the nitrogen semiconductor compound as an organic semiconductor material or a hole conducting material. The nitrogen semiconductor compound can be spin-coated at room temperature when applied to the fabrication of the device, and has superior electrical conductivity and photovoltaic properties.Type: GrantFiled: February 27, 2006Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jean Roncali, Antonio Cravino, Philippe Leriche, Pierre Frere, Sophie Roquet
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Patent number: 7713352Abstract: A process is provided to produce bulk quantities of nanowires in a variety of semiconductor materials. Thin films and droplets of low-melting metals such as gallium, indium, bismuth, and aluminum are used to dissolve and to produce nanowires. The dissolution of solutes can be achieved by using a solid source of solute and low-melting metal, or using a vapor phase source of solute and low-melting metal. The resulting nanowires range in size from 1 nanometer up to 1 micron in diameter and lengths ranging from 1 nanometer to several hundred nanometers or microns. This process does not require the use of metals such as gold and iron in the form of clusters whose size determines the resulting nanowire size. In addition, the process allows for a lower growth temperature, better control over size and size distribution, and better control over the composition and purity of the nanowire produced therefrom.Type: GrantFiled: September 14, 2006Date of Patent: May 11, 2010Assignee: University of Louisville Research Foundation, Inc.Inventors: Mahendra Kumar Sunkara, Shashank Sharma, Hari Chandrasekaran, Hongwei Li, Sreeram Vaddiraju
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Patent number: 7708832Abstract: Provided is a method for preparing a substrate for growing gallium nitride and a gallium nitride substrate. The method includes performing thermal cleaning on a surface of a silicon substrate, forming a silicon nitride (Si3N4) micro-mask on the surface of the silicon substrate in an in situ manner, and growing a gallium nitride layer through epitaxial lateral overgrowth (ELO) using an opening in the micro-mask. According to the method, by improving the typical ELO, it is possible to simplify the method for preparing the substrate for growing gallium nitride and the gallium nitride substrate and reduce process cost.Type: GrantFiled: July 22, 2008Date of Patent: May 4, 2010Assignee: Siltron Inc.Inventors: Yong-Jin Kim, Ji-Hoon Kim, Dong-Kun Lee, Doo-Soo Kim, Ho-Jun Lee
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Patent number: 7641988Abstract: A self-supported nitride semiconductor substrate of 10 mm or more in diameter having an X-ray diffraction half width of 500 seconds or less in at least one of a {20-24} diffraction plane and a {11-24} diffraction plane.Type: GrantFiled: April 12, 2004Date of Patent: January 5, 2010Assignee: Hitachi Cable, Ltd.Inventor: Takayuki Suzuki
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Patent number: 7621998Abstract: The present invention relates to a freestanding, thick, single crystalline gallium nitride (GaN) film having significantly reduced bending deformation. The inventive GaN film having a crystal tilt angle of C-axis to the <0001> direction per surface distance of 0.0022°/mm exhibits little bending deformation even at a thickness of 1 mm or more, and therefore, is beneficially used as a substrate for a luminescent device.Type: GrantFiled: November 23, 2005Date of Patent: November 24, 2009Assignee: Samsung Corning Co., Ltd.Inventors: Changho Lee, Hyun Min Shin, Sun-Hwan Kong, Hae Yong Lee
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Patent number: 7591897Abstract: A process for the rapid synthesis of metal oxide nanoparticles at low temperatures and methods which facilitate the fabrication of long metal oxide nanowires. The method is based on treatment of metals with oxygen plasma. Using oxygen plasma at low temperatures allows for rapid growth unlike other synthesis methods where nanomaterials take a long time to grow. Density of neutral oxygen atoms in plasma is a controlling factor for the yield of nanowires. The oxygen atom density window differs for different materials. By selecting the optimal oxygen atom density for various materials the yield can be maximized for nanowire synthesis of the metal.Type: GrantFiled: March 20, 2006Date of Patent: September 22, 2009Assignee: University of Louisville Research Foundation, Inc.Inventors: Mahendra Kumar Sunkara, Sreeram Vaddiraju, Miran Mozetic, Uros Cvelbar
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Patent number: 7563321Abstract: The invention is an improvement in the method of producing a high quality bulk single crystal of silicon carbide in a seeded sublimation system. In a first embodiment, the improvement comprises reducing the number of macrosteps in a growing crystal by incorporating a high concentration of nitrogen atoms in the initial one (1) millimeter of crystal growth.Type: GrantFiled: December 8, 2004Date of Patent: July 21, 2009Assignee: Cree, Inc.Inventors: Adrian Powell, Valeri F. Tsvetkov, Mark Brady, Robert T. Leonard
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Patent number: 7524376Abstract: A crystal growth setup within a physical vapor transport growth furnace system for producing AlN monocrystal boules at high temperatures includes a crucible effective to contain an AlN source material and a growing AlN crystal boule. This crucible has a thin wall thickness in at least that portion housing the growing AlN crystal boule. Other components include a susceptor, in case of an inductive heating, or a heater, in case of a resistive heating, a thermal insulation enclosing the susceptor or heater effective to provide a thermal gradient inside the crucible in the range of 5-100° C./cm and a furnace chamber capable of being operated from a vacuum (<0.1 torr) to a gas pressure of at least 4000 torr through filling or flowing a nitrogen gas or a mixture of nitrogen gas and argon gas. The high temperatures contribute to a high boule growth rate and the thin wall thickness contributes to reduced imparted stress during boule removal.Type: GrantFiled: April 25, 2007Date of Patent: April 28, 2009Assignee: Fairfield Crystal Technology, LLCInventor: Shaoping Wang
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Publication number: 20090038540Abstract: In a vapor phase growth apparatus, epitaxial growth is performed with respect to a wafer having a CVD film formed on a back surface thereof as a wafer for monitoring that is used to guarantee a resistance and/or measure a thickness of an epitaxial layer, then epitaxial growth is performed with respect to a wafer as a dummy or a vapor phase growth apparatus is activated under conditions for performing epitaxial growth without using a wafer, and subsequently epitaxial growth is carried out with respect to a wafer as a product, thereby manufacturing an epitaxial wafer. As a result, when using a wafer having no CVD film to manufacture an epitaxial wafer that is used to fabricate an imaging device, e.g., a CCD or a CMOS image sensor, a method capable of effectively avoiding heavy-metal contamination and manufacturing a high-quality epitaxial layer is provided.Type: ApplicationFiled: August 21, 2006Publication date: February 12, 2009Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tomosuke Yoshida, Naohisa Toda
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Patent number: 7473315Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: March 1, 2005Date of Patent: January 6, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Koji Uematsu
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Patent number: 7449064Abstract: An AlN single crystal is grown by pressurizing a melt including at least gallium, aluminum and sodium in an atmosphere containing nitrogen. Preferably, the AlN single crystal is grown under a nitrogen partial pressure of 50 atms or lower and at a temperature in a range of 850° C. to 1200° C.Type: GrantFiled: March 6, 2007Date of Patent: November 11, 2008Assignee: NGK Insulators, Ltd.Inventors: Makoto Iwai, Katsuhiro Imai
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Patent number: 7445671Abstract: A method of producing networks of low melting metal oxides such as crystalline gallium oxide comprised of one-dimensional nanostructures. Because of the unique arrangement of wires, these crystalline networks defined as “nanowebs”, “nanowire networks”, and/or “two-dimensional nanowires”. Nanowebs contain wire densities on the order of 109/cm2. A possible mechanism for the fast self-assembly of crystalline metal oxide nanowires involves multiple nucleation and coalescence via oxidation-reduction reactions at the molecular level. The preferential growth of nanowires parallel to the substrate enables them to coalesce into regular polygonal networks. The individual segments of the polygonal network consist of both nanowires and nanotubules of ?-gallium oxide. The synthesis of highly crystalline noncatalytic low melting metals such as ?-gallium oxide tubes, nanowires, and nanopaintbrushes is accomplished using molten gallium and microwave plasma containing a mixture of monoatomic oxygen and hydrogen.Type: GrantFiled: June 16, 2004Date of Patent: November 4, 2008Assignees: University of Louisville, University of KentuckyInventors: Mahendra Kumar Sunkara, Shashank Sharma, Burtron H. Davis, Uschi M. Graham
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Patent number: 7442355Abstract: An indium phosphide substrate for semiconductor devices is obtained as follows. In order to have the direction of growth of the crystal in the <100> orientation, a seed crystal having a specified cross-sectional area ratio with the crystal body is placed at the lower end of a growth container. The growth container housing the seed crystal, indium phosphide raw material, dopant, and boron oxide is placed in a crystal growth chamber. The temperature is raised to at or above the melting point of indium phosphide. After melting the boron oxide, indium phosphide raw material, and dopant, the temperature of the growth container is lowered in order to obtain an indium phosphide monocrystal having a low dislocation density and a uniform dopant concentration on the wafer as well as in the depth direction.Type: GrantFiled: May 6, 2004Date of Patent: October 28, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventor: Tomohiro Kawase
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Publication number: 20080213543Abstract: A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapour phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor.Type: ApplicationFiled: February 29, 2008Publication date: September 4, 2008Inventors: Gunnar Leibiger, Frank Habel, Stefan Eichler
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Patent number: 7402207Abstract: Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure the thickness of an SEG film in-situ utilizing optical ellipsometry equipment during or after SEG layer growth, prior to removing the wafer from the SEG growth tool. Optical ellipsometry equipment can be integrated into the SEG platform and control software, thus providing automated process control (APC) capability for SEG thickness. The integration of the ellipsometry equipment may be varied, dependent upon the needs of the fabrication facility, e.g., integration to provide ellipsometer monitoring of a single process tool, or multiple tool monitoring, among other configurations.Type: GrantFiled: May 5, 2004Date of Patent: July 22, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Paul R. Besser, Eric N. Paton, William G. En
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Patent number: 7387678Abstract: A GaN substrate comprises a GaN single crystal substrate, an AlxGa1-xN intermediate layer (0<x?1) epitaxially grown on the substrate, and an GaN epitaxial layer grown on the intermediate layer. The intermediate layer is made of AlGaN and this AlGaN grows over the entire surface of the substrate with contaminants thereon and high dislocation regions therein. Thus, the intermediate layer is normally grown on the substrate, and a growth surface of the intermediate layer can be made flat. Since the growth surface is flat, a growth surface of the GaN epitaxial layer epitaxially grown on the intermediate layer is also flat.Type: GrantFiled: June 25, 2004Date of Patent: June 17, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Katsushi Akita, Eiryo Takasuka, Masahiro Nakayama, Masaki Ueno, Kouhei Miura, Takashi Kyono
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Patent number: 7368014Abstract: A deposition method may include, at a first temperature, contacting a substrate with a first precursor and chemisorbing a first layer at least one monolayer thick over the substrate. At a second temperature different from the first temperature, the first layer may be contacted with a second precursor, chemisorbing a second layer at least one monolayer thick on the first layer. Temperature may be altered by adding or removing heat with a thermoelectric heat pump. The altering the substrate temperature may occur from the first to the second temperature. The second layer may be reacted with the first layer by heating to a third temperature higher than the second temperature. A deposition method may also include atomic layer depositing a first specie of a substrate approximately at an optimum temperature for the first specie deposition.Type: GrantFiled: August 9, 2001Date of Patent: May 6, 2008Assignee: Micron Technology, Inc.Inventor: Trung Tri Doan
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Publication number: 20080000414Abstract: A method for configuring J electromagnetic radiation sources (J?2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1?S1|, |W2?S2 , . . . , |W1?S1| is about minimized with respect to Pj=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj=1, . . . , J).Type: ApplicationFiled: June 29, 2006Publication date: January 3, 2008Inventors: Brent Allan Anderson, Edward Joseph Nowak
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Publication number: 20070277727Abstract: The liquid surface position of the melt in the crucible in the silicon single crystal growth process utilizing the Czochralski method is monitored using the melt surface position on the occasion of seeding as a reference position and an estimated melt surface position can be calculated according to every situation, so that the distance between the melt and the thermal shield or water-cooling structure can be controlled with high precision. When the estimated melt surface position passes a preset upper limit and approaches the thermal shield, an alarm goes off and, further, when the melt comes into contact with the thermal shield or approaches the water-cooling structure, an alarm goes off if desired and, at the same time, the crucible is forcedly stopped from moving, so that a serious accident such as steam-incurred explosion resulting from the melt coming into contact with the water-cooling structure can be prevented.Type: ApplicationFiled: May 25, 2007Publication date: December 6, 2007Inventors: Hiroshi Hayakawa, Tokuji Maeda
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Publication number: 20070266929Abstract: The present invention relates to a process for preparing a single crystal silicon ingot, as well as to the ingot or wafer resulting therefrom. In one embodiment, the process comprises controlling the growth velocity, v, and the effective or corrected axial temperature gradient, as defined herein, such that, within a given segment of the ingot, the ratio v/Geffective, or v/Gcorrected, is substantially near the critical value thereof over a substantial portion of the radius of that segment, and controlling the cooling rate of the segment between (i) solidification and about 1250° C., and (ii) about 1250° C. and about 1000° C., in order to manipulate the effect of the lateral incorporation of intrinsic point defects therein, and thus limit the formation of agglomerated intrinsic point defects and/or oxygen precipitate clusters in a ring extending radially inward from about the lateral surface of the ingot segment.Type: ApplicationFiled: May 18, 2007Publication date: November 22, 2007Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventor: Milind S. Kulkarni
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Patent number: 7270707Abstract: The present invention provides a method of preparation for diamond, graphite or mixtures of diamond and graphite by reduction of CO or CO2. Said method comprises a step of contacting an active metal capable of reducing a carbon source into elementary carbon with carbon source (such as CO and/or CO2 and/or their origin) under conditions suitable to reduce the carbon source to elementary carbon in the course of a reduction reaction. After the raw diamond or mixtures of diamond and graphite thus obtained are subjected to intensive heat treatment with perchloric acid, pure diamond granules are obtained. The present method employs relatively low reaction temperature and pressure and the facilities needed in the method are simple and easy to operate. Diamond finally obtained has good crystallinity and free of impurities with granule size of several hundred micrometer.Type: GrantFiled: November 15, 2002Date of Patent: September 18, 2007Assignee: University of Science and Technology of ChinaInventors: Qianwang Chen, Yitai Qian, Zhengsong Lou
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Patent number: 7232555Abstract: AlGaInN single-crystal wafer with alleviated cracking and improved utilization rate and cost effectiveness. A hexagonal AlxGayIn1?(x+y)N(0<x?1, 0?y<1, x+y?1) single-crystal wafer, characterized in that the wafer has a thickness T(cm) and a principal face with a surface area S(cm2), the area S and thickness T satisfying the conditions S?10 cm2 and 0.006S?T?0.002S.Type: GrantFiled: June 1, 2005Date of Patent: June 19, 2007Assignee: Sumitomo Electric Industries, Ltd.Inventor: Shinsuke Fujiwara
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Patent number: 7211144Abstract: A method of forming a tungsten nucleation layer using a sequential deposition process. The tungsten nucleation layer is formed by reacting pulses of a tungsten-containing precursor and a reducing gas in a process chamber to deposit tungsten on the substrate. Thereafter, reaction by-products generated from the tungsten deposition are removed from the process chamber. After the reaction by-products are removed from the process chamber, a flow of the reducing gas is provided to the process chamber to react with residual tungsten-containing precursor remaining therein. Such a deposition process forms tungsten nucleation layers having good step coverage. The sequential deposition process of reacting pulses of the tungsten-containing precursor and the reducing gas, removing reaction by-products, and than providing a flow of the reducing gas to the process chamber may be repeated until a desired thickness for the tungsten nucleation layer is formed.Type: GrantFiled: July 12, 2002Date of Patent: May 1, 2007Assignee: Applied Materials, Inc.Inventors: Xinliang Lu, Ping Jian, Jong Hyun Yoo, Ken Kaung Lai, Alfred W. Mak, Robert L. Jackson, Ming Xi
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Patent number: 7175708Abstract: Methods and apparatus are provided for the removal and purification of the water and salt by-products from spent BHP emitted from a lasing process. The apparatus comprises a liquid processing system that freezes the water and salt by-products into a slurry, and then separates out the water (as ice) and salt components by filtering in a centrifuge. In order to remove as much residual BHP from the wet mixed ice-salt component as possible, a heat source is used to partially melt ice crystals, thereby generating an aqueous rinsing liquid on the surface of the wet mixed ice-salt crystals. The applied centrifugal force causes a continual displacement of the liquid film wetting the surface, so that it becomes progressively diluted. As such, the purification of the mixture of ice and salt crystals is implemented with an aqueous (water) rinse that is unaffected by the sub-freezing temperatures within the centrifuge.Type: GrantFiled: July 28, 2005Date of Patent: February 13, 2007Assignee: The Boeing CompanyInventors: David Stelman, Steven M. Klee
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Patent number: 7153361Abstract: An opto-electronic device array is made from a multilayer epitaxial film by the following steps. The multilayer epitaxial film is separated into a plurality of segments. The segments are transferred to a first substrate to be arranged in an array substantially. Active regions are respectively confined in the segments so that the active regions form the array.Type: GrantFiled: December 23, 2003Date of Patent: December 26, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Hideto Furuyama
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Patent number: 7135073Abstract: What is described here is a method and a temperature management and reaction chamber system for the production of nitrogenous semiconductor crystal materials of the form AXBYCZNVMW, wherein A, B, C represent elements of group II or III, N represents nitrogen, M represents an element of group V or VI, and X, Y, Z, V, W represent the mol fraction of each element in this compound, operating on the basis of gas phase compositions and gas phase successions. The invention excels itself by the provisions that for the production of the semiconductor crystal materials the production process is controlled by the precise temperature control of defined positions in the reaction chamber system under predetermined conditions.Type: GrantFiled: June 1, 2001Date of Patent: November 14, 2006Assignee: Aixtron AGInventors: Michael Heuken, Gert Strauch, Harry Protzmann, Holger Jürgensen, Oliver Schön, Dietmar Schmitz
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Patent number: 7135071Abstract: A fractal structure is formed to have a plurality of regions different in fractal dimension characterizing the self-similarity. The fractal structure is grown from one or more origins under growth conditions providing a first fractal dimension in a first portion of the growth process from the start point of time to a first point of time, and under growth conditions providing a second fractal dimension lower than the first fractal dimension in another portion of the growth process from the first point of time to a second point of time. By adjusting the timing for changing the growth conditions, the fractal structure is controlled in nature of phase transition, such as critical temperature for ferromagnetic phase transition, which occurs in the fractal structure. For enhancing the controllability, the first fractal dimension is preferably larger than 2.7 and the second fractal dimension is preferably smaller than 2.3.Type: GrantFiled: August 24, 2001Date of Patent: November 14, 2006Assignee: Sony CorporationInventor: Ryuichi Ugajin
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Patent number: 7101434Abstract: A fractal structure is formed to have a plurality of regions different in fractal dimension characterizing the self-similarity. Especially in a stellar fractal structure, a region with a low fractal dimension is formed around a core with a high fractal dimension. By adjusting the ratios in volume of these regions relative to the entire fractal structure, the nature of phase transition occurring in the fractal structure, such as a magnetization curve of Mott transition or ferromagnetic phase transition, quantum chaos in the electron state, or the like. For enhancing the controllability, the fractal dimension of the core is preferably larger than 2.7 and the fractal dimension of the region around the core is preferably smaller than 2.3.Type: GrantFiled: May 22, 2001Date of Patent: September 5, 2006Assignee: Sony CorporationInventor: Ryuichi Ugajin
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Patent number: 7087114Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: October 8, 2002Date of Patent: August 8, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Patent number: 7074270Abstract: Techniques for predicting the behavior of dopant and defect components in a substrate lattice formed from a substrate material can be implemented in hardware or software. Fundamental data for a set of microscopic processes that can occur during one or more material processing operations is obtained. Such data can include data representing the kinetics of processes in the set of microscopic processes and the energetics and structure of possible states in the material processing operations. From the fundamental data and a set of external conditions, distributions of dopant and defect components in the substrate lattice are predicted.Type: GrantFiled: April 2, 2003Date of Patent: July 11, 2006Assignees: Seiko Epson Corporation, California Institute of TechnologyInventors: Yuzuru Sato, Masamitsu Uehara, Gyeong S. Hwang, William A. Goddard, III
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Patent number: 7056381Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film 103. Then, laser light is irradiated to diffuse the nickel element concentrated locally. After that, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. A thermal oxide film 106 is formed in this step. At this time, the nickel element is gettered to the thermal oxide film 106. Then, the thermal oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.Type: GrantFiled: January 16, 1997Date of Patent: June 6, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame
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Patent number: 7026009Abstract: A component for a substrate processing chamber comprises a structure having a textured coating with surface grains. The component is evaluated by directing a beam of electrons onto the textured coating of the component to cause at least some of the electrons to be backscattered. The backscattered electrons are detected and a signal image is generated. The component is selected when the signal image exhibits surface grains sized from about 0.1 to about 5 micron. In one version, the component is also selected when the grains are substantially flower shaped.Type: GrantFiled: March 27, 2002Date of Patent: April 11, 2006Assignee: Applied Materials, Inc.Inventors: Shyh-Nung Lin, Mark D. Menzie, Nimoal Sun
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Patent number: 7018467Abstract: A method of forming a three-dimensional (3D) complete photonic bandgap crystal by crystal modification is disclosed. The 3D crystal includes a first periodic array of unit cells formed from first voids connected by imaginary bonds. The first periodic array forms an incomplete bandgap. The first voids may be formed in any one of a number of shapes, including spherical. The 3D crystal further includes a second periodic array of second voids. The second voids are arranged along the imaginary bonds so as to modify each unit cell. The modification of the unit cells is designed to form a complete photonic bandgap.Type: GrantFiled: January 17, 2002Date of Patent: March 28, 2006Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Leonard Forbes
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Patent number: 7001459Abstract: A method of making a spinel-structured metal oxide on a substrate by molecular beam epitaxy, comprising the step of supplying activated oxygen, a first metal atom flux, and at least one other metal atom flux to the surface of the substrate, wherein the metal atom fluxes are individually controlled at the substrate so as to grow the spinel-structured metal oxide on the substrate and the metal oxide is substantially in a thermodynamically stable state during the growth of the metal oxide. A particular embodiment of the present invention encompasses a method of making a spinel-structured binary ferrite, including Co ferrite, without the need of a post-growth anneal to obtain the desired equilibrium state.Type: GrantFiled: August 29, 2003Date of Patent: February 21, 2006Assignee: Battelle Memorial InstituteInventor: Scott A. Chambers
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Patent number: 6994750Abstract: Reference infrared-absorption spectrum patterns are prepared in advance as a database. The infrared-absorption spectrum pattern of a film targeted for measurement is measured using FT-IR spectroscopy. Subsequently, multivariate analysis is performed using PLS regression, based on the reference infrared-absorption spectrum patterns and the infrared-absorption spectrum pattern of the target film. The film-growing temperature and other factors are then computed in accordance with the analysis results.Type: GrantFiled: September 10, 2002Date of Patent: February 7, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toshitaka Tatsunari
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Patent number: 6929695Abstract: The present invention is an tri-phase epitaxy method for preparing a single crystal oxide thin film, comprising the steps of depositing on a substrate an oxide thin film serving as a seed layer and having the same composition as that of an oxide thin film to be formed, depositing on the seed layer a thin film comprising a substance capable of being melted and liquidized by heat from the substrate and dissolving the oxide to be subsequent by deposited onto the seed layer, heating the substrate to form a liquid layer, and depositing an oxide on the seed layer through the liquid layer by use of a vapor-phase epitaxy method to form the single crystal oxide thin film. In this method, the oxygen partial pressure on the liquid layer is set in the range of 1.0 to 760 Torr during the film-forming step.Type: GrantFiled: August 31, 2001Date of Patent: August 16, 2005Assignee: Japan Science and Technology AgencyInventors: Hideomi Koinuma, Masashi Kawasaki, Yuji Matsumoto