Abstract: Preparations of a highly coherent diamond nitrogen vacancy (NV?) and a diamond anvil are provided. A graphite is used as a carbon source, a diamond is used as a crystal seed, aluminum/titanium is used as a nitrogen remover, and a single crystal diamond is synthesized under a high temperature and a high pressure, and high-pressure-high-temperature (HPHT) annealing is performed on the synthesized diamond; after the annealing, multiple NV?s are generated in <100> and <311> crystal orientation growth regions from scratch, while native NV?s in a <111> crystal orientation growth region are disappeared; and the <100> and <311> crystal orientation growth regions do not contain defects related to ferromagnetic elements. The high-density and highly coherent NV?s are produced under nondestructive conditions, and the diamond anvil with controlled NV? depths are prepared to achieve a precise detection of the NV? at a pressure above 60 GPa.

Abstract: There is provided a method of manufacturing a group III nitride semiconductor substrate including: a fixing step S10 of fixing abase substrate, which includes a group III nitride semiconductor layer having a semipolar plane as a main surface, to a susceptor; a first growth step S11 of forming a first growth layer by growing a group III nitride semiconductor over the main surface of the group III nitride semiconductor layer in a state in which the base substrate is fixed to the susceptor using an HVPE method; a cooling step S12 of cooling a laminate including the susceptor, the base substrate, and the first growth layer; and a second growth step S13 of forming a second growth layer by growing a group III nitride semiconductor over the first growth layer in a state in which the base substrate is fixed to the susceptor using the HVPE method.

Abstract: A method of manufacturing synthetic diamond material using a chemical vapour deposition process, and a diamond obtained by such a method are described. The method comprises providing a freestanding synthetic single crystal diamond substrate wafer having a dislocation density of at least 107 cm?2. The synthetic single crystal diamond substrate wafer is located over a substrate holder within a chemical vapour deposition reactor. Process gases are fed into the reactor, the process gases including a gas comprising carbon. Crack-free synthetic diamond material is grown on a surface of the single crystal diamond substrate wafer at a temperature of at least 900° C. to a thickness of at least 0.5 mm and with lateral dimensions of at least 4 mm by 4 mm.

Abstract: Methods to manufacture integrated circuits are described. Nanocrystalline diamond is used as a hard mask in place of amorphous carbon. Provided is a method of processing a substrate in which nanocrystalline diamond is used as a hard mask, wherein processing methods result in a smooth surface. The method involves two processing parts. Two separate nanocrystalline diamond recipes are combined—the first and second recipes are cycled to achieve a nanocrystalline diamond hard mask having high hardness, high modulus, and a smooth surface. In other embodiments, the first recipe is followed by an inert gas plasma smoothening process and then the first recipe is cycled to achieve a high hardness, a high modulus, and a smooth surface.

Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a bottom structure on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, selectively removing the second layer from the multi-material layer from the substrate, and selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer.

Abstract: A method capable of increasing a degree of freedom of process conditions that can be set in a plasma treatment while limiting deterioration in the electrical characteristics of a silicon or metal oxide film exposed to plasma, in performing the plasma treatment on a substrate. The method includes: processing a substrate on which a silicon or metal oxide film is formed, with plasma obtained by plasmarizing a process gas composed of a halogen compound; and subsequently, heating the substrate at a temperature of 450 degrees C. or higher in an inert gas atmosphere or a vacuum atmosphere in a state where the metal oxide film exposed to the plasma is exposed. Thus, deterioration in the characteristics of the oxide film caused by the plasma treatment are restored.

Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate is provided and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.

Abstract: A combination of doping, rapid pulsed optical and/or thermal annealing, and unique detector structure reduces or eliminates sources of electronic noise in a CdZnTe (CZT) detector. According to several embodiments, methods of forming a detector exhibiting minimal electronic noise include: pulse-annealing at least one surface of a detector comprising CZT for one or more pulses, each pulse having a duration of ˜0.1 seconds or less. The at least one surface may optionally be ion-implanted. In another embodiment, a CZT detector includes a detector surface with two or more electrodes operating at different electric potentials and coupled to the detector surface; and one or more ion-implanted CZT surfaces on or in the detector surface, each of the one or more ion-implanted CZT surfaces being independently connected to one of the two or more electrodes and the surface of the detector. At least two of the ion-implanted surfaces are in electrical contact.

Abstract: The present invention provides a method for manufacturing a monocrystalline graphene layer, comprising the steps of: forming polycrystalline graphene on a substrate by using a hydrocarbon gas to grow a graphene layer aligned on a wafer-scale insulator substrate in one direction like a monocrystal; forming a catalyst on the polycrystalline graphene; and recrystallizing the polycrystalline graphene to monocrystalline graphene by heat-treating the polycrystalline graphene and the catalyst.

Abstract: An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (TSVs), and a conductive layer. The TSVs extend between first and second substrate surfaces. The TSVs include a first subset of trench via(s) each having a primary axis aligned in a first direction, and a second subset of trench via(s) each having a primary axis aligned in a second and different direction. The TSVs form an alignment pattern in an alignment area of the substrate. The conductive layer is directly connected to the second substrate surface and to first ends of the TSVs. Using the TSVs for alignment, the conductive layer may be patterned so that a portion of the conductive layer is directly coupled to the TSVs, and so that the conductive layer includes at least one conductive material void (e.g., in alignment with a passive component at the first substrate surface).

Abstract: The present invention provides a method for producing a Group III nitride semiconductor single crystal having excellent crystallinity, and a method for producing a GaN substrate having excellent crystallinity, the method including controlling melting back. Specifically, a mask layer is formed on a GaN substrate serving as a growth substrate. Then, a plurality of trenches which penetrate the mask layer and reach the GaN substrate are formed through photolithography. The obtained seed crystal and raw materials of a single crystal are fed to a crucible and subjected to treatment under pressurized and high temperature conditions. Portions of the GaN substrate exposed to the trenches undergo melting back with a flux. Through dissolution of the GaN substrate, the dimensions of the trenches increase, to provide large trenches. The GaN layer is grown from the surface of the mask layer as a starting point.

Abstract: A method for making an epitaxial base includes the following steps. A plurality of grooves and a plurality of bulges are formed on an epitaxial growth surface of a substrate by etching the epitaxial growth surface. A carbon nanotube layer is located on the epitaxial growth surface, wherein the carbon nanotube layer defines a first part attached on top surface of bulges, and a second part suspended on the grooves. The second part of the carbon nanotube layer is attached on bottom surface of the grooves by treating the carbon nanotube layer.

Abstract: A method of producing a large area plate of single crystal diamond from CVD diamond grown on a substrate substantially free of surface defects by chemical vapor deposition (CVD). The homoepitaxial CVD grown diamond and the substrate are severed transverse to the surface of the substrate on which diamond growth took place to produce the large area plate of single crystal CVD diamond.

Abstract: An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, an optoelectronic device includes first and second semiconducting atomically thin layers with corresponding first and second lattice directions. The first and second semiconducting atomically thin layers are located proximate to each other, and an angular difference between the first lattice direction and the second lattice direction is between about 0.000001° and 0.5°, or about 0.000001° and 0.5° deviant from of a Vicnal angle of the first and second semiconducting atomically thin layers. Alternatively, or in addition to the above, the first and second semiconducting atomically thin layers may form a Moiré superlattice of exciton funnels with a period between about 50 nm to 3 cm. The optoelectronic device may also include charge carrier conductors in electrical communication with the semiconducting atomically thin layers to either inject or extract charge carriers.

Abstract: Techniques for epitaxial growth of CZT(S,Se) materials on Si are provided. In one aspect, a method of forming an epitaxial kesterite material is provided which includes the steps of: selecting a Si substrate based on a crystallographic orientation of the Si substrate; forming an epitaxial oxide interlayer on the Si substrate to enhance wettability of the epitaxial kesterite material on the Si substrate, wherein the epitaxial oxide interlayer is formed from a material that is lattice-matched to Si; and forming the epitaxial kesterite material on a side of the epitaxial oxide interlayer opposite the Si substrate, wherein the epitaxial kesterite material includes Cu, Zn, Sn, and at least one of S and Se, and wherein a crystallographic orientation of the epitaxial kesterite material is based on the crystallographic orientation of the Si substrate. A method of forming an epitaxial kesterite-based photovoltaic device and an epitaxial kesterite-based device are also provided.

Abstract: A method for growing a crystalline composition, the first crystalline composition may include gallium and nitrogen. The crystalline composition may have an infrared absorption peak at about 3175 cm?1, with an absorbance per unit thickness of greater than about 0.01 cm?1. In one embodiment, the composition may have an amount of oxygen present in a concentration of less than about 3×1018 per cubic centimeter, and may be free of two-dimensional planar boundary defects in a determined volume of the first crystalline composition.

Abstract: A method for fabricating a wafer according to the embodiment comprises the steps of depositing an epi layer in an epi deposition part; transferring the wafer to an annealing part connected to the epi deposition part; annealing the wafer in the annealing part; transferring the wafer to a cooling part connected to the annealing part; and cooling the wafer in the cooling part, wherein the depositing of the wafer, the annealing of the wafer and the cooling of the wafer are continuously performed. An apparatus for fabricating a wafer according to the embodiment comprises an epi deposition part; an annealing part connected to the epi deposition part; and a cooling part connected to the annealing part.

Abstract: Epitaxially coated semiconductor wafers are prepared by a process in which a semiconductor wafer polished at least on its front side is placed on a susceptor in a single-wafer epitaxy reactor and epitaxially coated on its polished front side at temperatures of 1000-1200° C., wherein, after coating, the semiconductor wafer is cooled in the temperature range from 1200° C. to 900° C. at a rate of less than 5° C. per second. In a second method for producing an epitaxially coated wafer, the wafer is placed on a susceptor in the epitaxy reactor and epitaxially coated on its polished front side at a deposition temperature of 1000-1200° C., and after coating, and while still at the deposition temperature, the wafer is raised for 1-60 seconds to break connections between susceptor and wafer produced by deposited semiconductor material before the wafer is cooled.

Abstract: A metal chloride gas generator includes: a tube reactor including a receiving section for receiving a metal on an upstream side, and a growing section in which a growth substrate is placed on a downstream side; a gas inlet pipe arranged to extend from an upstream end with a gas inlet via the receiving section to the growing section, for introducing a gas from the upstream end to supply the gas to the receiving section, and supplying a metal chloride gas produced by a reaction between the gas and the metal in the receiving section to the growing section; and a heat shield plate placed in the reactor to thermally shield the upstream end from the growing section. The gas inlet pipe is bent between the upstream end and the heat shield plate.

Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chosen photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarized III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.

Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.

Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Abstract: A semiconductor apparatus includes a buffer layer formed on a substrate; an SLS (Strained Layer Supperlattice) buffer layer formed on the buffer layer; an electron transit layer formed on the SLS buffer layer and formed of a semiconductor material; and an electron supply layer formed on the electron transit layer and formed of a semiconductor material. Further, the buffer layer is formed of AlGaN and includes two or more layers with different Al composition ratios, the SLS buffer layer is formed by alternately laminating a first lattice layer including AlN and a second lattice layer including GaN, and the Al composition ratio in one of the layers of the buffer layer being in contact with the SLS buffer layer is greater than or equal to an Al effective composition ratio in the SLS buffer layer.

Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a first temperature; and exposing the first layer to an RF plasma formed from a process gas comprising ammonia (NH3) to transform the first layer into a nitrogen-containing layer, wherein the plasma has an ion energy of less than about 8 eV.

Abstract: A large area nitride crystal, comprising gallium and nitrogen, with a non-polar or semi-polar large-area face, is disclosed, along with a method of manufacture. The crystal is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.

Abstract: A method for deposition of silicon carbide according to an embodiment includes preparing a wafer in a susceptor; introducing first etching gas into the susceptor; introducing second etching gas into the susceptor; producing an intermediate compound by introducing a reactive raw material into the susceptor; and forming a silicon carbide epitaxial layer on the wafer by reacting the intermediate compound with the wafer.

Abstract: The present invention is a base material for forming a single crystal diamond comprising, at least, a seed base material of a single crystal and a thin film heteroepitaxially grown on the seed base material, wherein the seed base material is a single crystal diamond and the thin film is Iridium film or Rhodium film. As a result, there is provided a base material for forming a single crystal diamond that enables a single crystal diamond having a high crystallinity to be heteroepitaxially grown thereon and that can be reused repeatedly and a method for producing a single crystal diamond that enables a single crystal diamond having a high crystallinity and a large area to be produced at low cost.

Abstract: Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten mixture (e.g., including KOH and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.

Abstract: Single crystal diamond material produced using chemical vapour deposition (CVD), and particularly diamond material having properties suitable for use in optical applications such as lasers, is disclosed. In particular, a CVD single crystal diamond material having preferred characteristics of longest linear internal dimension, birefringence and absorption coefficient, when measured at room temperature, is disclosed. Uses of the diamond material, including in a Raman laser, and methods of producing the diamond are also disclosed.

Abstract: The method for producing a silicon epitaxial wafer according to the present invention has: a growth step G at which an epitaxial layer is grown on a silicon single crystal substrate; a first polishing step E at which, before the growth step G, both main surfaces of the silicon single crystal substrate are subjected to rough polishing simultaneously; and a second polishing step H at which, after the growth step G, the both main surfaces of the silicon single crystal substrate are subjected to finish polishing simultaneously.

Abstract: The present invention provides a process for producing a two-dimensional nanomaterial by chemical vapour deposition (CVD), the process comprising contacting a substrate in a reaction chamber with a first flow which contains hydrogen and a second flow which contains a precursor for said material, wherein the contacting takes place under conditions such that the precursor reacts in the chamber to form said material on a surface of the substrate, wherein the ratio of the flow rate of the first flow to the flow rate of the second flow is at least 5:1. Two-dimensional nanomaterials obtainable by said process are also provided, as well as devices comprising said nanomaterials.

Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.

Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

Abstract: A system and method A method of growing an elongate nanoelement from a growth surface includes: a) cleaning a growth surface on a base element; b) providing an ultrahigh vacuum reaction environment over the cleaned growth surface; c) generating a reactive gas of an atomic material to be used in forming the nanoelement; d) projecting a stream of the reactive gas at the growth surface within the reactive environment while maintaining a vacuum of at most 1×10?4 Pascal; e) growing the elongate nanoelement from the growth surface within the environment while maintaining the pressure of step c); f) after a desired length of nanoelement is attained within the environment, stopping direction of reactive gas into the environment; and g) returning the environment to an ultrahigh vacuum condition.

Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.

Abstract: The present invention relates to a method for growing a non-polar m-plane epitaxial layer on a single crystal oxide substrate, which comprises the following steps: providing a single crystal oxide with a perovskite structure; using a plane of the single crystal oxide as a substrate; and forming an m-plane epitaxial layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process, wherein the non-polar m-plane epitaxial layer may be GaN, or III-nitrides. The present invention also provides an epitaxial layer having an m-plane obtained according to the aforementioned method.

Abstract: A method for manufacturing an epitaxial wafer includes: a step of pulling a single crystal from a boron-doped silicon melt in a chamber based on a Czochralski process; and a step of forming an epitaxial layer on a surface of a silicon wafer sliced from the single crystal. The single crystal is allowed to grow while passed through a temperature region of 800 to 600° C. in the chamber in 250 to 180 minutes during the pulling step. The grown single crystal has an oxygen concentration of 10×1017 to 12×1017 atoms/cm3 and a resistivity of 0.03 to 0.01 ?cm. The silicon wafer is subjected to pre-annealing prior to the step of forming the epitaxial layer on the surface of the silicon wafer, for 10 minutes to 4 hours at a predetermined temperature within a temperature region of 650 to 900° C. in an inert gas atmosphere. The method is to fabricate an epitaxial wafer that has a diameter of 300 mm or more, and that attains a high IG effect, and involves few epitaxial defects.

Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.

Abstract: Methods for forming an epilayer on a surface of a substrate are generally provided. For example, a substrate can be positioned within a hot wall CVD chamber (e.g., onto a susceptor within the CVD chamber). At least two source gases can then be introduced into the hot wall CVD chamber such that, upon decomposition, fluorine atoms, carbon atoms, and silicon atoms are present within the CVD chamber. The epilayer comprising SiC can then be grown on the surface of the substrate in the presence of the fluorine atoms.

Abstract: The object is to provide a photoelectric surface member which allows higher quantum efficiency. In order to achieve this object, a photoelectric surface member 1a is a crystalline layer formed by a nitride type semiconductor material, and comprises a nitride semiconductor crystal layer 10 where the direction from the first surface 101 to the second surface 102 is the negative c polar direction of the crystal, an adhesive layer 12 formed along the first surface 101 of the nitride semiconductor crystal layer 10, and a glass substrate 14 which is adhesively fixed to the adhesive layer 12 such that the adhesive layer 12 is located between the glass substrate 14 and the nitride semiconductor crystal layer 10.

Abstract: Relaxed germanium buffer layers can be grown economically on misoriented silicon wafers by low-energy plasma-enhanced chemical vapor deposition. In conjunction with thermal annealing and/or patterning, the buffer layers can serve as high-quality virtual substrates for the growth of crack-free GaAs layers suitable for high-efficiency solar cells, lasers and field effect transistors.

Abstract: A substrate is formed of AlxGa1-xN, wherein 0<x?1. The substrate is a single crystal and is used producing a Group III nitride semiconductor device. A method for producing a substrate of AlxGa1-xN, wherein 0<x?1, includes the steps of forming a layer of AlxGa1-xN, wherein 0<x?1, on a base material and removing the base material. The method adopts the MOCVD method using a raw material molar ratio of a Group V element to Group III element that is 1000 or less, a temperature of 1200° C. or more for forming the layer of AlxGa1-xN, wherein 0<x?1. The base material is formed of one member selected from the group consisting of sapphire, SiC, Si, ZnO and Ga2O3. The substrate is used for fabricating a Group III nitride semiconductor device.

Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.

Abstract: Affords Group-III nitride single-crystal ingots and III-nitride single-crystal substrates manufactured utilizing the ingots, as well as methods of manufacturing III-nitride single-crystal ingots and methods of manufacturing III-nitride single-crystal substrates, wherein the incidence of cracking during length-extending growth is reduced. Characterized by including a step of etching the edge surface of a base substrate, and a step of epitaxially growing onto the base substrate hexagonal-system III-nitride monocrystal having crystallographic planes on its side surfaces. In order to reduce occurrences of cracking during length-extending growth of the ingot, depositing-out of polycrystal and out-of-plane oriented crystal onto the periphery of the monocrystal must be controlled.

Abstract: Substrates for electronic device fabrication and methods thereof. A reusable substrate with at least a plurality of grooves for electronic device fabrication includes a substrate body made of one or more substrate materials and including a top planar surface, the top planar surface being divided into a plurality of planer regions by the plurality of grooves, the plurality of grooves including a plurality of bottom planar surfaces. Each of the plurality of grooves includes a bottom planar surface and two side surfaces, the bottom planar surface being selected from the plurality of bottom planar surfaces, the two side surfaces being in contact with the top surface and the bottom surface. The bottom planar surface is associated with a groove width from one of the two side surfaces to the other of the two side surfaces, the groove width ranging from 0.1 ?m to 5 mm.

Abstract: In some embodiments, the present disclosure pertains to methods of growing chalcogen-linked metallic films on a surface in a chamber. In some embodiments, the method comprises placing a metal source and a chalcogen source in the chamber, and gradually heating the chamber, where the heating leads to the chemical vapor deposition of the chalcogen source and the metal source onto the surface, and facilitates the growth of the chalcogen-linked metallic film from the chalcogen source and the metal source on the surface. In some embodiments, the chalcogen source comprises sulfur, and the metal source comprises molybdenum trioxide. In some embodiments, the growth of the chalcogen-linked metallic film occurs by formation of nucleation sites on the surface, where the nucleation sites merge to form the chalcogen-linked metallic film. In some embodiments, the formed chalcogen-linked metallic film includes MoS2.

Abstract: A system for depositing a film on a substrate comprises a lateral control shutter disposed between the substrate and a material source. The lateral control shutter is configured to block some predetermined portion of source material to prevent deposition of source material onto undesirable portion of the substrate. One of the lateral control shutter or the substrate moves with respect to the other to facilitate moving a lateral growth boundary originating from one or more seed crystals. A lateral epitaxial deposition across the substrate ensues, by having an advancing growth front that expands grain size and forms a single crystal film on the surface of the substrate.

Abstract: A method for using a silicon film formation apparatus includes performing a pre-coating process to cover a reaction tube with a silicon coating film, an etching process to etch natural oxide films on product target objects, a silicon film formation process to form a silicon product film on the product target objects, and a cleaning process to etch silicon films on the reaction tube, in this order. The pre-coating process includes supplying a silicon source gas into the reaction tube from a first supply port having a lowermost opening at a first position below the process field, while exhausting gas upward from inside the reaction tube. The etching process includes supplying an etching gas into the reaction tube from a second supply port having a lowermost opening between the process field and the first position, while exhausting gas upward from inside the reaction tube by the exhaust system.

Abstract: A method of: providing an off-axis silicon carbide substrate, and etching the surface of the substrate with a dry gas, hydrogen, or an inert gas.

Abstract: A method for forming a topological insulator structure is provided. A strontium titanate substrate having a surface (111) is used. The surface (111) of the strontium titanate substrate is cleaned by heat-treating the strontium titanate substrate in the molecular beam epitaxy chamber. The strontium titanate substrate is heated and Bi beam, Sb beam, Cr beam, and Te beam are formed in the molecular beam epitaxy chamber in a controlled ratio achieved by controlling flow rates of the Bi beam, Sb beam, Cr beam, and Te beam. The magnetically doped topological insulator quantum well film is formed on the surface (111) of the strontium titanate substrate. The amount of the hole type charge carriers introduced by the doping with Cr is substantially equal to the amount of the electron type charge carriers introduced by the doping with Bi.