Material Removal (e.g., Etching, Cleaning, Polishing) Patents (Class 117/97)
  • Patent number: 9960310
    Abstract: A combination of doping, rapid pulsed optical and/or thermal annealing, and unique detector structure reduces or eliminates sources of electronic noise in a CdZnTe (CZT) detector. According to several embodiments, methods of forming a detector exhibiting minimal electronic noise include: pulse-annealing at least one surface of a detector comprising CZT for one or more pulses, each pulse having a duration of ˜0.1 seconds or less. The at least one surface may optionally be ion-implanted. In another embodiment, a CZT detector includes a detector surface with two or more electrodes operating at different electric potentials and coupled to the detector surface; and one or more ion-implanted CZT surfaces on or in the detector surface, each of the one or more ion-implanted CZT surfaces being independently connected to one of the two or more electrodes and the surface of the detector. At least two of the ion-implanted surfaces are in electrical contact.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 1, 2018
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Lars Voss, Adam Conway, Art Nelson, Rebecca J. Nikolic, Stephen A. Payne, Erik Lars Swanberg, Jr.
  • Patent number: 9834855
    Abstract: The present invention provides a method for manufacturing a monocrystalline graphene layer, comprising the steps of: forming polycrystalline graphene on a substrate by using a hydrocarbon gas to grow a graphene layer aligned on a wafer-scale insulator substrate in one direction like a monocrystal; forming a catalyst on the polycrystalline graphene; and recrystallizing the polycrystalline graphene to monocrystalline graphene by heat-treating the polycrystalline graphene and the catalyst.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: December 5, 2017
    Assignee: KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCE
    Inventor: Chanyong Hwang
  • Patent number: 9666523
    Abstract: An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (TSVs), and a conductive layer. The TSVs extend between first and second substrate surfaces. The TSVs include a first subset of trench via(s) each having a primary axis aligned in a first direction, and a second subset of trench via(s) each having a primary axis aligned in a second and different direction. The TSVs form an alignment pattern in an alignment area of the substrate. The conductive layer is directly connected to the second substrate surface and to first ends of the TSVs. Using the TSVs for alignment, the conductive layer may be patterned so that a portion of the conductive layer is directly coupled to the TSVs, and so that the conductive layer includes at least one conductive material void (e.g., in alignment with a passive component at the first substrate surface).
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: May 30, 2017
    Assignee: NXP USA, INC.
    Inventor: Thomas E. Wood
  • Patent number: 9567693
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor single crystal having excellent crystallinity, and a method for producing a GaN substrate having excellent crystallinity, the method including controlling melting back. Specifically, a mask layer is formed on a GaN substrate serving as a growth substrate. Then, a plurality of trenches which penetrate the mask layer and reach the GaN substrate are formed through photolithography. The obtained seed crystal and raw materials of a single crystal are fed to a crucible and subjected to treatment under pressurized and high temperature conditions. Portions of the GaN substrate exposed to the trenches undergo melting back with a flux. Through dissolution of the GaN substrate, the dimensions of the trenches increase, to provide large trenches. The GaN layer is grown from the surface of the mask layer as a starting point.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 14, 2017
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Miki Moriyama, Shohei Kumegawa, Shiro Yamazaki
  • Patent number: 9570293
    Abstract: A method for making an epitaxial base includes the following steps. A plurality of grooves and a plurality of bulges are formed on an epitaxial growth surface of a substrate by etching the epitaxial growth surface. A carbon nanotube layer is located on the epitaxial growth surface, wherein the carbon nanotube layer defines a first part attached on top surface of bulges, and a second part suspended on the grooves. The second part of the carbon nanotube layer is attached on bottom surface of the grooves by treating the carbon nanotube layer.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 14, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 9518338
    Abstract: A method of producing a large area plate of single crystal diamond from CVD diamond grown on a substrate substantially free of surface defects by chemical vapor deposition (CVD). The homoepitaxial CVD grown diamond and the substrate are severed transverse to the surface of the substrate on which diamond growth took place to produce the large area plate of single crystal CVD diamond.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: December 13, 2016
    Assignee: Element Six Technologies Limited
    Inventors: Geoffrey Alan Scarsbrook, Philip Maurice Martineau, Daniel James Twitchen
  • Patent number: 9484489
    Abstract: An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, an optoelectronic device includes first and second semiconducting atomically thin layers with corresponding first and second lattice directions. The first and second semiconducting atomically thin layers are located proximate to each other, and an angular difference between the first lattice direction and the second lattice direction is between about 0.000001° and 0.5°, or about 0.000001° and 0.5° deviant from of a Vicnal angle of the first and second semiconducting atomically thin layers. Alternatively, or in addition to the above, the first and second semiconducting atomically thin layers may form a Moiré superlattice of exciton funnels with a period between about 50 nm to 3 cm. The optoelectronic device may also include charge carrier conductors in electrical communication with the semiconducting atomically thin layers to either inject or extract charge carriers.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: November 1, 2016
    Assignee: Massachusetts Institute of Technology
    Inventors: Ju Li, Xiaofeng Qian, Menghao Wu
  • Patent number: 9287426
    Abstract: Techniques for epitaxial growth of CZT(S,Se) materials on Si are provided. In one aspect, a method of forming an epitaxial kesterite material is provided which includes the steps of: selecting a Si substrate based on a crystallographic orientation of the Si substrate; forming an epitaxial oxide interlayer on the Si substrate to enhance wettability of the epitaxial kesterite material on the Si substrate, wherein the epitaxial oxide interlayer is formed from a material that is lattice-matched to Si; and forming the epitaxial kesterite material on a side of the epitaxial oxide interlayer opposite the Si substrate, wherein the epitaxial kesterite material includes Cu, Zn, Sn, and at least one of S and Se, and wherein a crystallographic orientation of the epitaxial kesterite material is based on the crystallographic orientation of the Si substrate. A method of forming an epitaxial kesterite-based photovoltaic device and an epitaxial kesterite-based device are also provided.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Talia S. Gershon, Supratik Guha, Byungha Shin, Yu Zhu
  • Patent number: 9279193
    Abstract: A method for growing a crystalline composition, the first crystalline composition may include gallium and nitrogen. The crystalline composition may have an infrared absorption peak at about 3175 cm?1, with an absorbance per unit thickness of greater than about 0.01 cm?1. In one embodiment, the composition may have an amount of oxygen present in a concentration of less than about 3×1018 per cubic centimeter, and may be free of two-dimensional planar boundary defects in a determined volume of the first crystalline composition.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: March 8, 2016
    Assignee: Momentive Performance Materials Inc.
    Inventors: Mark Philip D'Evelyn, Kristi Jean Narang, Dong-Sil Park, Huicong Hong, Xian-An Cao, Larry Qiang Zeng
  • Patent number: 9281188
    Abstract: A method for fabricating a wafer according to the embodiment comprises the steps of depositing an epi layer in an epi deposition part; transferring the wafer to an annealing part connected to the epi deposition part; annealing the wafer in the annealing part; transferring the wafer to a cooling part connected to the annealing part; and cooling the wafer in the cooling part, wherein the depositing of the wafer, the annealing of the wafer and the cooling of the wafer are continuously performed. An apparatus for fabricating a wafer according to the embodiment comprises an epi deposition part; an annealing part connected to the epi deposition part; and a cooling part connected to the annealing part.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: March 8, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Seok Min Kang, Moo Seong Kim
  • Patent number: 9240316
    Abstract: Epitaxially coated semiconductor wafers are prepared by a process in which a semiconductor wafer polished at least on its front side is placed on a susceptor in a single-wafer epitaxy reactor and epitaxially coated on its polished front side at temperatures of 1000-1200° C., wherein, after coating, the semiconductor wafer is cooled in the temperature range from 1200° C. to 900° C. at a rate of less than 5° C. per second. In a second method for producing an epitaxially coated wafer, the wafer is placed on a susceptor in the epitaxy reactor and epitaxially coated on its polished front side at a deposition temperature of 1000-1200° C., and after coating, and while still at the deposition temperature, the wafer is raised for 1-60 seconds to break connections between susceptor and wafer produced by deposited semiconductor material before the wafer is cooled.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: January 19, 2016
    Assignee: SILTRONIC AG
    Inventors: Reinhard Schauer, Christian Hager
  • Patent number: 9236252
    Abstract: A metal chloride gas generator includes: a tube reactor including a receiving section for receiving a metal on an upstream side, and a growing section in which a growth substrate is placed on a downstream side; a gas inlet pipe arranged to extend from an upstream end with a gas inlet via the receiving section to the growing section, for introducing a gas from the upstream end to supply the gas to the receiving section, and supplying a metal chloride gas produced by a reaction between the gas and the metal in the receiving section to the growing section; and a heat shield plate placed in the reactor to thermally shield the upstream end from the growing section. The gas inlet pipe is bent between the upstream end and the heat shield plate.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: January 12, 2016
    Assignee: SCIOCS COMPANY LIMITED
    Inventors: Taichiroo Konno, Hajime Fujikura, Michiko Matsuda
  • Patent number: 9230818
    Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chosen photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarized III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: January 5, 2016
    Assignee: TRUSTEES OF BOSTON UNIVERSITY
    Inventors: Theordore D Moustakas, Adrian D Williams
  • Patent number: 9209596
    Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 8, 2015
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 9184241
    Abstract: A semiconductor apparatus includes a buffer layer formed on a substrate; an SLS (Strained Layer Supperlattice) buffer layer formed on the buffer layer; an electron transit layer formed on the SLS buffer layer and formed of a semiconductor material; and an electron supply layer formed on the electron transit layer and formed of a semiconductor material. Further, the buffer layer is formed of AlGaN and includes two or more layers with different Al composition ratios, the SLS buffer layer is formed by alternately laminating a first lattice layer including AlN and a second lattice layer including GaN, and the Al composition ratio in one of the layers of the buffer layer being in contact with the SLS buffer layer is greater than or equal to an Al effective composition ratio in the SLS buffer layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: November 10, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
  • Patent number: 9184159
    Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 10, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
  • Patent number: 9177787
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a first temperature; and exposing the first layer to an RF plasma formed from a process gas comprising ammonia (NH3) to transform the first layer into a nitrogen-containing layer, wherein the plasma has an ion energy of less than about 8 eV.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: November 3, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Theresa Kramer Guarini, Wei Liu
  • Patent number: 9175418
    Abstract: A large area nitride crystal, comprising gallium and nitrogen, with a non-polar or semi-polar large-area face, is disclosed, along with a method of manufacture. The crystal is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: November 3, 2015
    Assignee: Soraa, Inc.
    Inventors: Mark P. D'Evelyn, James S. Speck
  • Patent number: 9165768
    Abstract: A method for deposition of silicon carbide according to an embodiment includes preparing a wafer in a susceptor; introducing first etching gas into the susceptor; introducing second etching gas into the susceptor; producing an intermediate compound by introducing a reactive raw material into the susceptor; and forming a silicon carbide epitaxial layer on the wafer by reacting the intermediate compound with the wafer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: October 20, 2015
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Seok Min Kang
  • Patent number: 9127375
    Abstract: The present invention is a base material for forming a single crystal diamond comprising, at least, a seed base material of a single crystal and a thin film heteroepitaxially grown on the seed base material, wherein the seed base material is a single crystal diamond and the thin film is Iridium film or Rhodium film. As a result, there is provided a base material for forming a single crystal diamond that enables a single crystal diamond having a high crystallinity to be heteroepitaxially grown thereon and that can be reused repeatedly and a method for producing a single crystal diamond that enables a single crystal diamond having a high crystallinity and a large area to be produced at low cost.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: September 8, 2015
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Hitoshi Noguchi
  • Publication number: 20150129897
    Abstract: Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten mixture (e.g., including KOH and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.
    Type: Application
    Filed: December 2, 2014
    Publication date: May 14, 2015
    Inventors: Tangali S. Sudarshan, Haizheng Song, Tawhid Rana
  • Patent number: 9017633
    Abstract: Single crystal diamond material produced using chemical vapour deposition (CVD), and particularly diamond material having properties suitable for use in optical applications such as lasers, is disclosed. In particular, a CVD single crystal diamond material having preferred characteristics of longest linear internal dimension, birefringence and absorption coefficient, when measured at room temperature, is disclosed. Uses of the diamond material, including in a Raman laser, and methods of producing the diamond are also disclosed.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 28, 2015
    Assignee: Element Six Technologies Limited
    Inventors: Ian Friel, Sarah Louise Geoghegan, Daniel James Twitchen, Joseph Michael Dodson
  • Patent number: 8999061
    Abstract: The method for producing a silicon epitaxial wafer according to the present invention has: a growth step G at which an epitaxial layer is grown on a silicon single crystal substrate; a first polishing step E at which, before the growth step G, both main surfaces of the silicon single crystal substrate are subjected to rough polishing simultaneously; and a second polishing step H at which, after the growth step G, the both main surfaces of the silicon single crystal substrate are subjected to finish polishing simultaneously.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: April 7, 2015
    Assignee: Sumco Corporation
    Inventors: Masayuki Ishibashi, Tomonori Miura
  • Publication number: 20150064098
    Abstract: The present invention provides a process for producing a two-dimensional nanomaterial by chemical vapour deposition (CVD), the process comprising contacting a substrate in a reaction chamber with a first flow which contains hydrogen and a second flow which contains a precursor for said material, wherein the contacting takes place under conditions such that the precursor reacts in the chamber to form said material on a surface of the substrate, wherein the ratio of the flow rate of the first flow to the flow rate of the second flow is at least 5:1. Two-dimensional nanomaterials obtainable by said process are also provided, as well as devices comprising said nanomaterials.
    Type: Application
    Filed: March 28, 2013
    Publication date: March 5, 2015
    Applicant: Isis Innovation Limited
    Inventors: Nicole Grobert, Adrian Timothy Murdock, Antal Adolf Koós
  • Publication number: 20150040822
    Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.
    Type: Application
    Filed: July 22, 2014
    Publication date: February 12, 2015
    Inventors: Christopher S. OLSEN, Theresa K. Guarini, Jeffrey Tobin, Lara Hawrylchak, Peter Stone, Chi Wei Lo, Saurabh Chopra
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8945304
    Abstract: A system and method A method of growing an elongate nanoelement from a growth surface includes: a) cleaning a growth surface on a base element; b) providing an ultrahigh vacuum reaction environment over the cleaned growth surface; c) generating a reactive gas of an atomic material to be used in forming the nanoelement; d) projecting a stream of the reactive gas at the growth surface within the reactive environment while maintaining a vacuum of at most 1×10?4 Pascal; e) growing the elongate nanoelement from the growth surface within the environment while maintaining the pressure of step c); f) after a desired length of nanoelement is attained within the environment, stopping direction of reactive gas into the environment; and g) returning the environment to an ultrahigh vacuum condition.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: February 3, 2015
    Assignee: The Board of Regents of the Nevada System of Higher Education on behalf of the University of Nevada, Las Vegas University of Nevada
    Inventors: Biswajit Das, Myung B. Lee
  • Patent number: 8936681
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 20, 2015
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Publication number: 20150004435
    Abstract: The present invention relates to a method for growing a non-polar m-plane epitaxial layer on a single crystal oxide substrate, which comprises the following steps: providing a single crystal oxide with a perovskite structure; using a plane of the single crystal oxide as a substrate; and forming an m-plane epitaxial layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process, wherein the non-polar m-plane epitaxial layer may be GaN, or III-nitrides. The present invention also provides an epitaxial layer having an m-plane obtained according to the aforementioned method.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 1, 2015
    Inventors: Li CHANG, Yen-Teng HO
  • Patent number: 8920560
    Abstract: A method for manufacturing an epitaxial wafer includes: a step of pulling a single crystal from a boron-doped silicon melt in a chamber based on a Czochralski process; and a step of forming an epitaxial layer on a surface of a silicon wafer sliced from the single crystal. The single crystal is allowed to grow while passed through a temperature region of 800 to 600° C. in the chamber in 250 to 180 minutes during the pulling step. The grown single crystal has an oxygen concentration of 10×1017 to 12×1017 atoms/cm3 and a resistivity of 0.03 to 0.01 ?cm. The silicon wafer is subjected to pre-annealing prior to the step of forming the epitaxial layer on the surface of the silicon wafer, for 10 minutes to 4 hours at a predetermined temperature within a temperature region of 650 to 900° C. in an inert gas atmosphere. The method is to fabricate an epitaxial wafer that has a diameter of 300 mm or more, and that attains a high IG effect, and involves few epitaxial defects.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: December 30, 2014
    Assignee: Sumco Corporation
    Inventors: Yasuo Koike, Toshiaki Ono, Naoki Ikeda, Tomokazu Katano
  • Patent number: 8906487
    Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 9, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Shimada
  • Publication number: 20140338588
    Abstract: Methods for forming an epilayer on a surface of a substrate are generally provided. For example, a substrate can be positioned within a hot wall CVD chamber (e.g., onto a susceptor within the CVD chamber). At least two source gases can then be introduced into the hot wall CVD chamber such that, upon decomposition, fluorine atoms, carbon atoms, and silicon atoms are present within the CVD chamber. The epilayer comprising SiC can then be grown on the surface of the substrate in the presence of the fluorine atoms.
    Type: Application
    Filed: November 20, 2012
    Publication date: November 20, 2014
    Inventors: Tangali S. Sudarshan, Haizheng Song, Tawhid Rana
  • Patent number: 8888914
    Abstract: The object is to provide a photoelectric surface member which allows higher quantum efficiency. In order to achieve this object, a photoelectric surface member 1a is a crystalline layer formed by a nitride type semiconductor material, and comprises a nitride semiconductor crystal layer 10 where the direction from the first surface 101 to the second surface 102 is the negative c polar direction of the crystal, an adhesive layer 12 formed along the first surface 101 of the nitride semiconductor crystal layer 10, and a glass substrate 14 which is adhesively fixed to the adhesive layer 12 such that the adhesive layer 12 is located between the glass substrate 14 and the nitride semiconductor crystal layer 10.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 18, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Tokuaki Nihashi, Masatomo Sumiya, Minoru Hagino, Shunro Fuke
  • Patent number: 8882910
    Abstract: A substrate is formed of AlxGa1-xN, wherein 0<x?1. The substrate is a single crystal and is used producing a Group III nitride semiconductor device. A method for producing a substrate of AlxGa1-xN, wherein 0<x?1, includes the steps of forming a layer of AlxGa1-xN, wherein 0<x?1, on a base material and removing the base material. The method adopts the MOCVD method using a raw material molar ratio of a Group V element to Group III element that is 1000 or less, a temperature of 1200° C. or more for forming the layer of AlxGa1-xN, wherein 0<x?1. The base material is formed of one member selected from the group consisting of sapphire, SiC, Si, ZnO and Ga2O3. The substrate is used for fabricating a Group III nitride semiconductor device.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 11, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hiroshi Amano, Akira Bando
  • Patent number: 8882909
    Abstract: Relaxed germanium buffer layers can be grown economically on misoriented silicon wafers by low-energy plasma-enhanced chemical vapor deposition. In conjunction with thermal annealing and/or patterning, the buffer layers can serve as high-quality virtual substrates for the growth of crack-free GaAs layers suitable for high-efficiency solar cells, lasers and field effect transistors.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: November 11, 2014
    Assignee: Dichroic Cell S.R.L.
    Inventor: Hans Von Kaenel
  • Publication number: 20140291694
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 8845992
    Abstract: Affords Group-III nitride single-crystal ingots and III-nitride single-crystal substrates manufactured utilizing the ingots, as well as methods of manufacturing III-nitride single-crystal ingots and methods of manufacturing III-nitride single-crystal substrates, wherein the incidence of cracking during length-extending growth is reduced. Characterized by including a step of etching the edge surface of a base substrate, and a step of epitaxially growing onto the base substrate hexagonal-system III-nitride monocrystal having crystallographic planes on its side surfaces. In order to reduce occurrences of cracking during length-extending growth of the ingot, depositing-out of polycrystal and out-of-plane oriented crystal onto the periphery of the monocrystal must be controlled.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: September 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takuji Okahisa, Seiji Nakahata, Tomoki Uemura
  • Patent number: 8841207
    Abstract: Substrates for electronic device fabrication and methods thereof. A reusable substrate with at least a plurality of grooves for electronic device fabrication includes a substrate body made of one or more substrate materials and including a top planar surface, the top planar surface being divided into a plurality of planer regions by the plurality of grooves, the plurality of grooves including a plurality of bottom planar surfaces. Each of the plurality of grooves includes a bottom planar surface and two side surfaces, the bottom planar surface being selected from the plurality of bottom planar surfaces, the two side surfaces being in contact with the top surface and the bottom surface. The bottom planar surface is associated with a groove width from one of the two side surfaces to the other of the two side surfaces, the groove width ranging from 0.1 ?m to 5 mm.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: September 23, 2014
    Assignee: Lux Material Co., Ltd.
    Inventor: Baoguo Zhang
  • Publication number: 20140251205
    Abstract: A system for depositing a film on a substrate comprises a lateral control shutter disposed between the substrate and a material source. The lateral control shutter is configured to block some predetermined portion of source material to prevent deposition of source material onto undesirable portion of the substrate. One of the lateral control shutter or the substrate moves with respect to the other to facilitate moving a lateral growth boundary originating from one or more seed crystals. A lateral epitaxial deposition across the substrate ensues, by having an advancing growth front that expands grain size and forms a single crystal film on the surface of the substrate.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: Tivra Corporation
    Inventor: Indranil De
  • Publication number: 20140251204
    Abstract: In some embodiments, the present disclosure pertains to methods of growing chalcogen-linked metallic films on a surface in a chamber. In some embodiments, the method comprises placing a metal source and a chalcogen source in the chamber, and gradually heating the chamber, where the heating leads to the chemical vapor deposition of the chalcogen source and the metal source onto the surface, and facilitates the growth of the chalcogen-linked metallic film from the chalcogen source and the metal source on the surface. In some embodiments, the chalcogen source comprises sulfur, and the metal source comprises molybdenum trioxide. In some embodiments, the growth of the chalcogen-linked metallic film occurs by formation of nucleation sites on the surface, where the nucleation sites merge to form the chalcogen-linked metallic film. In some embodiments, the formed chalcogen-linked metallic film includes MoS2.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 11, 2014
    Applicant: William Marsh Rice University
    Inventors: Sina Najmaei, Zheng Liu, Pulickel M. Ajayan, Jun Lou
  • Patent number: 8808452
    Abstract: A method for using a silicon film formation apparatus includes performing a pre-coating process to cover a reaction tube with a silicon coating film, an etching process to etch natural oxide films on product target objects, a silicon film formation process to form a silicon product film on the product target objects, and a cleaning process to etch silicon films on the reaction tube, in this order. The pre-coating process includes supplying a silicon source gas into the reaction tube from a first supply port having a lowermost opening at a first position below the process field, while exhausting gas upward from inside the reaction tube. The etching process includes supplying an etching gas into the reaction tube from a second supply port having a lowermost opening between the process field and the first position, while exhausting gas upward from inside the reaction tube by the exhaust system.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Naotaka Noro, Takahiro Miyahara
  • Publication number: 20140190399
    Abstract: A method of: providing an off-axis silicon carbide substrate, and etching the surface of the substrate with a dry gas, hydrogen, or an inert gas.
    Type: Application
    Filed: March 11, 2014
    Publication date: July 10, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Rachael L. Myers-Ward, David Kurt Gaskill, Charles R. Eddy, JR., Robert E. Stahlbush, Nadeemmullah A. Mahadik, Virginia D. Wheeler
  • Publication number: 20140174343
    Abstract: A method for forming a topological insulator structure is provided. A strontium titanate substrate having a surface (111) is used. The surface (111) of the strontium titanate substrate is cleaned by heat-treating the strontium titanate substrate in the molecular beam epitaxy chamber. The strontium titanate substrate is heated and Bi beam, Sb beam, Cr beam, and Te beam are formed in the molecular beam epitaxy chamber in a controlled ratio achieved by controlling flow rates of the Bi beam, Sb beam, Cr beam, and Te beam. The magnetically doped topological insulator quantum well film is formed on the surface (111) of the strontium titanate substrate. The amount of the hole type charge carriers introduced by the doping with Cr is substantially equal to the amount of the electron type charge carriers introduced by the doping with Bi.
    Type: Application
    Filed: October 16, 2013
    Publication date: June 26, 2014
    Applicants: Institute of Physics, Chinese Academy of Sciences, Tsinghua University
    Inventors: QI-KUN XUE, KE HE, XU-CUN MA, XI CHEN, LI-LI WANG, CUI-ZU CHANG, XIAO FENG, YAO-YI LI, JIN-FENG JIA
  • Patent number: 8652255
    Abstract: A method of: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxial grow silicon carbide on a wafer in the growth chamber; stopping or reducing the flow of the silicon source gas to interrupt the silicon carbide growth and maintaining the flow of the carrier gas while maintaining an elevated temperature in the growth chamber for a period of time; and resuming the flow of the silicon source gas to reinitiate silicon carbide growth. The wafer remains in the growth chamber throughout the method.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 18, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Robert E Stahlbush, Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, David Kurt Gaskill, Charles R. Eddy, Jr.
  • Publication number: 20140014030
    Abstract: In some embodiments, the present disclosure pertains to methods of forming single-crystal graphenes by: (1) cleaning a surface of a catalyst; (2) annealing the surface of the catalyst; (3) applying a carbon source to the surface of the catalyst; and (4) growing single-crystal graphene on the surface of the catalyst from the carbon source. Further embodiments of the present disclosure also include a step of separating the formed single-crystal graphene from the surface of the catalyst. In some embodiments, the methods of the present disclosure also include a step of transferring the formed single-crystal graphene to a substrate. Additional embodiments of the present disclosure also include a step of growing stacks of single crystals of graphene.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 16, 2014
    Applicant: William Marsh Rice University
    Inventors: James M. Tour, Zheng Yan
  • Patent number: 8591652
    Abstract: The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the material for forming the mask layer consists at least partially of tungsten silicide nitride or tungsten silicide and wherein the semiconductor substrate self-separates from the starting substrate without further process steps.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 26, 2013
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Christian Hennig, Markus Weyers, Eberhard Richter, Guenther Traenkle
  • Patent number: 8580035
    Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities—e.g., a dislocation density below 104 cm?2 and an inclusion density below 104 cm?3 and/or a MV density below 104 cm?3.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 12, 2013
    Assignee: Crystal IS, Inc.
    Inventors: Robert Bondokov, Kenneth E. Morgan, Glen A. Slack, Leo J. Schowalter
  • Patent number: 8574528
    Abstract: A method of growing an epitaxial layer on a substrate is generally provided. According to the method, the substrate is heated in a chemical vapor deposition chamber to a growth temperature in the presence of a carbon source gas, then the epitaxial layer is grown on the substrate at the growth temperature, and finally the substrate is cooled in a chemical vapor deposition chamber to at least about 80% of the growth temperature in the presence of a carbon source gas. Substrates formed from this method can have a carrier lifetime between about 0.25 ?s and about 9.9 ?s.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: November 5, 2013
    Assignee: University of South Carolina
    Inventors: Tangali S. Sudarshan, Amitesh Srivastava
  • Patent number: 8541313
    Abstract: A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: September 24, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stéphan Borel, Jeremy Bilde
  • Publication number: 20130239879
    Abstract: A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second port in communication with the lower portion of the chamber. The load lock includes a rack disposed within the chamber and a workpiece holder mounted on a first surface of the rack, wherein the rack and the workpiece holder are movable by an indexer that is capable of selectively moving wafer slots of the rack into communication with the second port. The indexer can also move the rack into an uppermost position, at which the first surface of the boat and the partition sealingly separate the upper portion and the lower portion to define an upper chamber and a lower chamber. Auxiliary processing, such as wafer pre-cleaning, or metrology can be conducted in the upper portion.
    Type: Application
    Filed: May 8, 2013
    Publication date: September 19, 2013
    Applicant: ASM AMERICA, INC.
    Inventors: Ravinder K. Aggarwal, Jeroen Stoutjesdijk, Eric R. Hill, Loring G. Davis, John T. DiSanto