With Decomposition Of A Precursor (except Impurity Or Dopant Precursor) Composed Of Diverse Atoms (e.g., Cvd) Patents (Class 117/88)
  • Patent number: 11600538
    Abstract: A SiC epitaxial wafer according to an embodiment includes: a SiC substrate; and a SiC epitaxial layer formed on a first surface of the SiC substrate. The in-plane uniformity of a density of Z1/2 centers of the SiC epitaxial layer is 5% or less.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 7, 2023
    Assignee: SHOWA DENKO K.K.
    Inventors: Naoto Ishibashi, Koichi Murata, Hidekazu Tsuchida
  • Patent number: 11600963
    Abstract: Chip technology for fabricating ultra-low-noise, high-stability optical devices for use in an optical atomic clock system. The proposed chip technology uses diamond material to form stabilized lasers, frequency references, and passive laser cavity structures. By utilizing the exceptional thermal conductivity of diamond and other optical and dielectric properties, a specific temperature range of operation is proposed that allows significant reduction of the total energy required to generate and maintain an ultra-stable laser. In each configuration, the diamond-based chip is cooled by a cryogenic cooler containing liquid nitrogen.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: March 7, 2023
    Assignee: The Boeing Company
    Inventors: Anguel Nikolov, John R. Lowell, David K. Mefford, John Dalton Williams
  • Patent number: 11587814
    Abstract: A vertical batch furnace assembly for processing wafers comprising a cassette handling space, a wafer handling space, and an internal wall separating the cassette handling space and the wafer handling space. The cassette handling space is provided with a cassette storage configured to store a plurality of wafer cassettes provided with a plurality of wafers. The cassette handling space is also provided with a cassette handler configured to transfer wafer cassettes between the cassette storage and a wafer transfer position. The wafer handling space is provided with a wafer handler configured to transfer wafers between a wafer cassette in the wafer transfer position and a wafer boat in a wafer boat transfer position. The internal wall is provided with a wafer transfer opening adjacent the wafer transfer position for a wafer cassette from or to which wafers are to be transferred. The cassette storage comprises two cassette storage carousels.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 21, 2023
    Assignee: ASM IP Holding B.V.
    Inventor: Chris G. M. de Ridder
  • Patent number: 11555256
    Abstract: In various embodiments, single-crystal aluminum nitride boules and substrates have low Urbach energies and/or absorption coefficients at deep-ultraviolet wavelengths. The single-crystal aluminum nitride may function as a platform for the fabrication of light-emitting devices such as light-emitting diodes and lasers.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: January 17, 2023
    Assignee: CRYSTAL IS, INC.
    Inventors: Robert T. Bondokov, James R. Grandusky, Jianfeng Chen, Shichao Wang, Toru Kimura, Thomas Miebach, Keisuke Yamaoka, Leo J. Schowalter
  • Patent number: 11542631
    Abstract: A method for producing a p-type 4H—SiC single crystal includes sublimating a nitrided aluminum raw material and a SiC raw material. Further, there is a stacking of a SiC single crystal, which is co-doped with aluminum and nitrogen, on one surface of a seed crystal.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 3, 2023
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, SHOWA DENKO K.K., DENSO CORPORATION
    Inventors: Kazuma Eto, Tomohisa Kato, Hiromasa Suo, Yuichiro Tokuda
  • Patent number: 11459669
    Abstract: A SiC ingot includes a core portion; and a surface layer that is formed on a plane of the core portion in a growing direction, and a coefficient of linear thermal expansion of the surface layer is smaller than a coefficient of linear thermal expansion of the core portion.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 4, 2022
    Assignee: SHOWA DENKO K.K.
    Inventors: Rimpei Kindaichi, Yohei Fujikawa, Yoshishige Okuno
  • Patent number: 11454599
    Abstract: A thermal conductivity measuring device includes a sample container that has a plurality of storage sections; a drive unit that is configured to move the plurality of storage sections of the sample container; and a radiation thermometer that is configured to measure the temperature of a predetermined position of the sample container.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 27, 2022
    Assignee: SHOWA DENKO K.K.
    Inventor: Yohei Fujikawa
  • Patent number: 11408841
    Abstract: A thermal conductivity measuring device includes a sample container that has a plurality of storage sections; a drive unit that is configured to move the plurality of storage sections of the sample container; and a radiation thermometer that is configured to measure the temperature of a predetermined position of the sample container.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: August 9, 2022
    Assignee: SHOWA DENKO K.K.
    Inventor: Yohei Fujikawa
  • Patent number: 11149359
    Abstract: A physical vapor transport growth system includes a growth chamber charged with SiC source material and a SiC seed crystal in spaced relation and an envelope that is at least partially gas-permeable disposed in the growth chamber. The envelope separates the growth chamber into a source compartment that includes the SiC source material and a crystallization compartment that includes the SiC seed crystal. The envelope is formed of a material that is reactive to vapor generated during sublimation growth of a SiC single crystal on the SiC seed crystal in the crystallization compartment to produce C-bearing vapor that acts as an additional source of C during the growth of the SiC single crystal on the SiC seed crystal.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 19, 2021
    Assignee: II-VI DELAWARE, INC.
    Inventors: Avinash Gupta, Ilya Zwieback, Edward Semenas, Marcus Getkin, Patrick Flynn
  • Patent number: 11077525
    Abstract: A method of processing silicon carbide containing crystalline substrate is provided. The method includes pyrolyzing a surface of the silicon carbide containing crystalline substrate to produce a silicon and carbon containing debris layer over the silicon carbide containing crystalline substrate, and removing the silicon and carbon containing debris layer, wherein the pyrolyzing and the removing is repeated at least once.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Michael Roesner, Markus Menath, Gudrun Stranzl
  • Patent number: 11072871
    Abstract: A preparation apparatus for uniform silicon carbide crystals comprises a circular cylinder, a doping tablet, and a plate to stabilize and control the supply of dopants. The accessory does not participate in the reaction in the growth chamber but maintains its efficacy during growth. Finally, a single semi-insulating silicon carbide crystal with uniform electrical characteristics can be obtained.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 27, 2021
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Chih-Wei Kuo, Dai-Liang Ma, Chia-Hung Tai, Bang-Ying Yu, Cheng-Jung Ko, Bo-Cheng Lin, Hsueh-I Chen
  • Patent number: 11049717
    Abstract: A method for fabricating an ultra-thin graphite film on a silicon carbide substrate includes the steps of: (A) providing a polyamic acid solution and a siloxane-containing coupling agent for polymerizing under an inert gas atmosphere to form a siloxane-coupling-group-containing polyamic acid solution; (B) performing a curing process after applying the siloxane-coupling-group-containing polyamic acid solution to a silicon carbide substrate; (C) placing the silicon carbide substrate in a graphite crucible before placing the graphite crucible in a reaction furnace to perform a carbonization process under an inert gas atmosphere; (D) subjecting the silicon carbide substrate to a graphitization process to obtain a graphite film, thereby make it possible to fabricate an ultra-thin graphite film of high-quality on the surface of silicon carbide in a lower graphitization temperature range.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 29, 2021
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Dai-Liang Ma, Cheng-Jung Ko, Chia-Hung Tai, Jun-Bin Huang, Bang-Ying Yu
  • Patent number: 11046582
    Abstract: A method of purifying silicon carbide powder includes: providing a container with a surface coated by a nitrogen-removal metal layer, wherein the nitrogen-removal metal layer is tantalum, niobium, tungsten, or a combination thereof; putting a silicon carbide powder into the container to contact the nitrogen-removal metal layer; and heating the silicon carbide powder under an inert gas at a pressure of 400 torr to 760 torr at 1700° C. to 2300° C. for 2 to 10 hours, thereby reducing the nitrogen content of the silicon carbide powder.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 29, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ta-Ching Hsiao, Chu-Pi Jeng, Mu-Hsi Sung, Kuo-Lun Huang
  • Patent number: 11011376
    Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along <111> crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and an above-surface portion formed on the blocking layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
  • Patent number: 10927451
    Abstract: Methods and apparatus for processing a substrate. The method, for example, includes directing a stream of material from a PVD source at a first non-perpendicular angle to selectively deposit the material on a top portion of one or more features on the substrate and form a first overhang and a second overhang extending beyond a third sidewall and a fourth sidewall that are arranged parallel and opposite to each other and at non-zero angles to a first sidewall and a second sidewall, the first sidewall and the second sidewall defining a length of the one or more features, and the third sidewall and fourth sidewall defining a width of the one or more features; performing an etch process to selectively remove some of the first sidewall and the second sidewall while keeping the third sidewall and fourth sidewall in intact and maintaining the width of the one or more features.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 23, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Byeong Chan Lee, Huixiong Dai, Tejinder Singh, Joung Joo Lee, Xianmin Tang
  • Patent number: 10734255
    Abstract: A substrate cleaning method includes supplying, onto a substrate, a film-forming processing liquid including a volatile component and a polar organic material that forms a processing film on the substrate, volatilizing the volatile component such that the film-forming processing liquid solidifies or cures and forms the processing film on the substrate, supplying, to the processing film formed on the substrate, a peeling processing liquid that peels off the processing film from the substrate and includes a non-polar solvent, and supplying, to the processing film, a dissolution processing liquid that dissolves the processing film and includes a polar solvent after the supplying of the peeling processing liquid. The non-polar solvent does not contain water, and the polar solvent does not contain water.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kenji Sekiguchi, Itaru Kanno, Meitoku Aibara, Kouzou Tachibana
  • Patent number: 10720752
    Abstract: The method includes the steps of: preparing a single crystal SiC including an upper surface 10a and a lower surface 10b and provided with a micropipe 11 penetrating from the upper surface 10a to the lower surface 10b; forming a first seed layer 21 made of a metal material on the upper surface 10a of the single crystal SiC; and forming a first plated layer 31 on the first seed layer 21 so as to close an upper end of the micropipe 11, using an electroplating method.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: July 21, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Akinori Yoneda, Shinya Sonobe, Hiroaki Yuto
  • Patent number: 10573716
    Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor deposition layer of the first conductivity type, deposited on a front surface of the silicon carbide semiconductor substrate and having an impurity concentration that is lower than that of the silicon carbide semiconductor substrate, a base region of a second conductivity type, selectively provided in the first silicon carbide semiconductor deposition layer at a front surface thereof, and a second silicon carbide semiconductor deposition layer of the second conductivity type, deposited on the front surface of the first silicon carbide semiconductor deposition layer. The base region has an impurity concentration of 1×1018 to 1×1020/cm3 and a thickness of 0.3 to 1.0 ?m. The second silicon carbide semiconductor deposition layer has a surface defect density of 3 defects/cm2.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: February 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi Tawara
  • Patent number: 10535518
    Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 14, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Danny M. Kim, Rongming Chu, Yu Cao, Thaddeus D. Ladd
  • Patent number: 10494735
    Abstract: A crystal growth apparatus includes: a chamber including a gas inlet, a gas outlet, a welded portion, and a water-cooling portion configured to water-cool a portion at least including the welded portion; an exhaust pump connected to the gas outlet; a dew point instrument disposed between the gas outlet and the exhaust pump, the dew point instrument being configured to measure a dew point of gas passing through the gas outlet.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 3, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Tsutomu Hori, Sho Sasaki, Tetsuya Kishida
  • Patent number: 10475627
    Abstract: A carrier ring configured to support a substrate during transport to or from a pedestal of a process tool and surrounding the substrate during processing is defined by, an inner annular portion having a first thickness, the inner annular portion defined to be adjacent a substrate support region of the pedestal; a middle annular portion surrounding the inner annular portion, the middle annular portion having a second thickness greater than the first thickness, such that a transition from a top surface of the inner annular portion to a top surface of the middle annular portion defines a first step; an outer annular portion surrounding the middle annular portion, the outer annular portion having a third thickness greater than the second thickness, such that a transition from the top surface of the middle annular portion to a top surface of the outer annular portion defines a second step.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: November 12, 2019
    Assignee: Lam Research Corporation
    Inventors: Chengzhu Qi, Yukinori Sakiyama, Bin Luo, Douglas Keil, Pramod Subramonium, Chunhai Ji, Joseph Lindsey Womack
  • Patent number: 10358718
    Abstract: A method is described for providing a hydrophilic effect to a fluoropolymer, e.g. polytetrafluoroethylene (PTFE) material. The method comprises obtaining an at least partly hydrophobic fluoropolymer material, applying a plasma and/or ozone activation step and depositing an inorganic coating using an atomic layer deposition process. Plasma activation step and/or said atomic layer deposition process thereby comprises using process parameters determining a high interaction probability between one or more precursors for the atomic layer deposition process and the fluoropolymer material so as to obtain a coated fluoropolymer material having a contact angle with water below 30°.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: July 23, 2019
    Assignee: UNIVERSITEIT GENT
    Inventors: Christophe Detavernier, Davy Deduytsche, Amit Kumar Roy
  • Patent number: 10294584
    Abstract: A physical vapor transport growth system includes a growth chamber charged with SiC source material and a SiC seed crystal in spaced relation and an envelope that is at least partially gas-permeable disposed in the growth chamber. The envelope separates the growth chamber into a source compartment that includes the SiC source material and a crystallization compartment that includes the SiC seed crystal. The envelope is formed of a material that is reactive to vapor generated during sublimation growth of a SiC single crystal on the SiC seed crystal in the crystallization compartment to produce C-bearing vapor that acts as an additional source of C during the growth of the SiC single crystal on the SiC seed crystal.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: May 21, 2019
    Assignee: II-VI INCORPORATED
    Inventors: Avinash K. Gupta, Ilya Zwieback, Edward Semenas, Marcus L. Getkin, Patrick D. Flynn
  • Patent number: 10153207
    Abstract: An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 11, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Abbondanza
  • Patent number: 9991411
    Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 5, 2018
    Assignee: Artilux Corporation
    Inventors: Szu-Lin Cheng, Han-Din Liu, Shu-Lu Chen, Yun-Chung Na, Hui-Wen Chen
  • Patent number: 9963343
    Abstract: Disclosed are a transition metal dichalcogenide alloy and a method of manufacturing the same. A method of manufacturing a transition metal dichalcogenide alloy according to an embodiment of the present disclosure includes a step of depositing transition metal dichalcogenide on a substrate using atomic layer deposition (ALD); and a step of forming a transition metal dichalcogenide alloy by thermally treating the transition metal dichalcogenide with a sulfur compound.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: May 8, 2018
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Hyungjun Kim, Kyung Yong Ko, Kyunam Park
  • Patent number: 9903046
    Abstract: Single crystal silicon carbide epitaxial layer on an off-axis substrate are manufactured by placing the substrate in an epitaxial growth reactor, growing a first layer of epitaxial silicon carbide on the substrate, interrupting the growth of the first layer of epitaxial silicon carbide, etching the first layer of epitaxial silicon carbide to reduce the thickness of the first layer, and regrowing a second layer of epitaxial silicon carbide on the first layer of epitaxial silicon carbide. Carrot defects may be terminated by the process of interrupting the epitaxial growth process, etching the grown layer and regrowing a second layer of epitaxial silicon carbide. The growth interruption/etching/regrowth may be repeated multiple times. A silicon carbide epitaxial layer has at least one carrot defect that is terminated within the epitaxial layer.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: February 27, 2018
    Assignee: Cree, Inc.
    Inventors: Michael John O'Loughlin, Joseph John Sumakeris
  • Patent number: 9893152
    Abstract: A semi-insulating silicon carbide monocrystal and a method of growing the same are disclosed. The semi-insulating silicon carbide monocrystal comprises intrinsic impurities, deep energy level dopants and intrinsic point defects. The intrinsic impurities are introduced unintentionally during manufacture of the silicon carbide monocrystal, and the deep energy level dopants and the intrinsic point defects are doped or introduced intentionally to compensate for the intrinsic impurities. The intrinsic impurities include shallow energy level donor impurities and shallow energy level acceptor impurities. A sum of a concentration of the deep energy level dopants and a concentration of the intrinsic point defects is greater than a difference between a concentration of the shallow energy level donor impurities and a concentration of the shallow energy level acceptor impurities, and the concentration of the intrinsic point defects is less than the concentration of the deep energy level dopants.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 13, 2018
    Assignee: Institute of Physics, Chinese Academy of Sciences
    Inventors: Xiaolong Chen, Chunjun Liu, Tonghua Peng, Longyuan Li, Bo Wang, Gang Wang, Wenjun Wang, Yu Liu
  • Patent number: 9752255
    Abstract: A single-crystal diamond growth base material on which single-crystal diamond is grown having at least a base substrate of a material having a linear expansion coefficient smaller than that of MgO and not smaller than 0.5×10?6/K; a single-crystal MgO layer formed on a face of the base substrate where the single-crystal diamond is grown by a bonding method; and a film constituted of any one of an iridium film, a rhodium film, and a platinum film heteroepitaxially grown on the single-crystal MgO layer.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: September 5, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hitoshi Noguchi, Shozo Shirai
  • Patent number: 9735022
    Abstract: An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 ?m. All nanowires of the plurality of nanowires are substantially parallel to each other.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: August 15, 2017
    Assignee: ALPHABET ENERGY, INC.
    Inventors: Mingqiang Yi, Matthew L. Scullin, Gabriel Matus, Dawn L. Hilken, Chii Guang Lee, Sylvain Muckenhirn
  • Patent number: 9543500
    Abstract: At least two types of dielectric materials such as oxide nanosheets having a layered perovskite structure that differ from each other are laminated, and the nanosheets are bonded to each other via an ionic material, thereby producing a superlattice structure-having ferroelectric thin film. Having the layered structure, the film can exhibit ferroelectricity as a whole, though not using a ferroelectric material therein. Accordingly, there is provided a ferroelectric film based on a novel principle, which is favorable for ferroelectric memories and others and which is free from a size effect even though extremely thinned.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: January 10, 2017
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Minoru Osada, Takayoshi Sasaki
  • Patent number: 9499905
    Abstract: Methods and apparatus for deposition of materials on substrates are provided herein. In some embodiments, an apparatus may include a process chamber having a substrate support; a heating system to provide heat energy to the substrate support; a gas inlet port disposed to a first side of the substrate support to provide at least one of a first process gas or a second process gas across a processing surface of the substrate; a first gas distribution conduit disposed above the substrate support and having one or more first outlets disposed along the length of the first gas distribution conduit to provide a third process gas to the processing surface of the substrate, wherein the one or more first outlets are substantially linearly arranged; and an exhaust manifold disposed to a second side of the substrate support opposite the gas inlet port to exhaust the process gases from the process chamber.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: November 22, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mehmet Tugrul Samir, Nyi Oo Myo
  • Patent number: 9502636
    Abstract: Disclosed is a composition for ferroelectric thin film formation which is used in the formation of a ferroelectric thin film of one material selected from the group consisting of PLZT, PZT, and PT. The composition for ferroelectric thin film formation is a liquid composition for the formation of a thin film of a mixed composite metal oxide formed of a mixture of a composite metal oxide (A) represented by general formula (1): (PbxLay)(ZrzTi(1-z))O3 [wherein 0.9<x<1.3, 0?y<0.1, and 0?z<0.9 are satisfied] with a composite oxide (B) or a carboxylic acid (B) represented by general formula (2): CnH2n+1COOH [wherein 3?n?7 is satisfied]. The composite oxide (B) contains one or at least two elements selected from the group consisting of P (phosphorus), Si, Ce, and Bi and one or at least two elements selected from the group consisting of Sn, Sm, Nd, and Y (yttrium).
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: November 22, 2016
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Jun Fujii, Hideaki Sakurai, Takashi Noguchi, Nobuyuki Soyama
  • Patent number: 9428389
    Abstract: A process for preparing a vitreous carbon including the steps of: (I) providing a curable low viscosity liquid carbon precursor formulation comprising (a) at least one aromatic epoxy resin; and (b)(i) at least one aromatic co-reactive curing agent, (b) (ii) at least one catalytic curing agent, or (b)(iii) a mixture thereof; wherein the liquid precursor composition has a neat viscosity of less than 10,000 mPa·s at 25° C.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: August 30, 2016
    Assignee: BLUE CUBE IP LLC
    Inventors: Hamed Lakrout, Maurice J. Marks, Ludovic Valette
  • Patent number: 9316589
    Abstract: This method for evaluating an oxide semiconductor thin film includes evaluating the stress stability of an oxide semiconductor thin film on the basis of the light emission intensity of luminescent light excited when radiating an electron beam or excitation light at a sample at which the oxide semiconductor thin film is formed. The stress stability of the oxide semiconductor thin film is evaluated on the basis of the light emission intensity (L1) observed in the range of 1.6-1.9 eV of the luminescent light excited from the oxide semiconductor thin film.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: April 19, 2016
    Assignee: Kobe Steel, Ltd.
    Inventors: Kazushi Hayashi, Toshihiro Kugimiya, Tomoya Kishi, Aya Miki
  • Patent number: 9222197
    Abstract: Provided is a shield member and an apparatus for growing a single crystal equipped with the shield member. Such a shield member includes: a vessel for growing the single crystal; a raw material storage part positioned at a lower portion of the vessel for growing the single crystal; a substrate supporting part, positioned above the raw material storage part to support the substrate; and a heating apparatus positioned at a an outer periphery of the vessel for growing the single crystal, thereby sublimating the raw material from the raw material storage part to grow the single crystal of the raw material onto the substrate, in which a plurality of permeation holes through which the raw material gas passes is formed. The shield member is configured such that the heat capacity thereof increases from the center to the outer periphery.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: December 29, 2015
    Assignee: SHOWA DENKO K.K.
    Inventor: Akihiro Matsuse
  • Patent number: 9214342
    Abstract: A method for producing a compound semiconductor crystal, includes; a sacrificial layer formation step of forming a sacrificial layer containing Cx1Siy1Gez1Sn1-x1-y1-z1 (0?x1<1, 0?y1?1, 0?z1?1, and 0<x1+y1+z1?1), on a base wafer whose surface is made of a silicon crystal; a crystal formation step of forming, on the sacrificial layer, a compound semiconductor crystal lattice-matching or pseudo lattice-matching the sacrificial layer; and a crystal removal step of removing the compound semiconductor crystal from the base wafer, by etching the sacrificial layer.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: December 15, 2015
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Hiroyuki Sazawa
  • Patent number: 9209011
    Abstract: A method of operating a film deposition apparatus including a turntable provided in a vacuum chamber and configured to rotate a substrate mounted thereon, a first reaction gas supplying portion, a second reaction gas supplying portion, a separation area, a first vacuum evacuation port for mainly evacuating the first reaction gas, a second vacuum evacuation port for mainly evacuating the second reaction gas, and a cleaning gas supplying portion for supplying a cleaning gas to clean the turntable, the method includes a cleaning step of supplying the cleaning gas from the cleaning gas supplying portion into the vacuum chamber while terminating the evacuation from the first vacuum evacuation port and performing the evacuation from the second vacuum evacuation port.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 8, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Shigehiro Miura
  • Patent number: 9190515
    Abstract: Methods of making Si-containing films that contain relatively high levels of Group III or Group V dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain at least about 3×1020 atoms cm?3 of an electrically active dopant. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 17, 2015
    Assignee: ASM America, Inc.
    Inventor: Matthias Bauer
  • Patent number: 9039834
    Abstract: Non-polar (11 20) a-plane gallium nitride (GaN) films with planar surfaces are grown on (1 102) r-plane sapphire substrates by employing a low temperature nucleation layer as a buffer layer prior to a high temperature growth of the non-polar (11 20) a-plane GaN thin films.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: May 26, 2015
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, James Stephen Speck
  • Patent number: 9034103
    Abstract: In various embodiments, methods of forming single-crystal AlN include providing a substantially undoped polycrystalline AlN ceramic having an oxygen concentration less than approximately 100 ppm, forming a single-crystal bulk AlN crystal by a sublimation-recondensation process at a temperature greater than approximately 2000° C., and cooling the bulk AlN crystal to a first temperature between approximately 1500° C. and approximately 1800° C. at a first rate less than approximately 250° C./hour.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 19, 2015
    Assignee: CRYSTAL IS, INC.
    Inventors: Sandra B. Schujman, Shailaja P. Rao, Robert T. Bondokov, Kenneth E. Morgan, Glen A. Slack, Leo J. Schowalter
  • Patent number: 9034104
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A single-component oxide semiconductor layer is formed over a substrate; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a single-component oxide semiconductor layer including single crystal regions is formed; and a multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
  • Patent number: 9028612
    Abstract: In various embodiments, non-zero thermal gradients are formed within a growth chamber both substantially parallel and substantially perpendicular to the growth direction during formation of semiconductor crystals, where the ratio of the two thermal gradients (parallel to perpendicular) is less than 10, by, e.g., arrangement of thermal shields outside of the growth chamber.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 12, 2015
    Assignee: Crystal IS, Inc.
    Inventors: Robert T. Bondokov, Shailaja P. Rao, Shawn Robert Gibb, Leo J. Schowalter
  • Patent number: 9023306
    Abstract: The invention relates to a single crystal boron doped CVD diamond that has a toughness of at least about 22 MPa m1/2. The invention further relates to a method of manufacturing single crystal boron doped CVD diamond. The growth rate of the diamond can be from about 20-100 ?m/h.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: May 5, 2015
    Assignee: Carnegie Institution of Washington
    Inventors: Russell J. Hemley, Ho-Kwang Mao, Chih-Shiue Yan, Qi Liang
  • Patent number: 9023427
    Abstract: Atomic layer deposition of multi-component, preferably multi-component oxide, thin films. Provide herein is a method for depositing a multi-component oxide film by, for example, an ALD or PEALD process, wherein the process comprises at least two individual metal oxide deposition cycles. The method provided herein has particular advantages in producing multi-component oxide films having superior uniformity. A method is presented, for example, including depositing multi-component oxide films comprising components A?B?O by ALD comprising mixing two individual metal oxides deposition cycles A+O and B+O, wherein the subcycle order is selected in such way that as few as possible consecutive deposition subcycles for A+O or B+O are performed.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: May 5, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Raija Matero, Tom Blomberg
  • Patent number: 9017633
    Abstract: Single crystal diamond material produced using chemical vapour deposition (CVD), and particularly diamond material having properties suitable for use in optical applications such as lasers, is disclosed. In particular, a CVD single crystal diamond material having preferred characteristics of longest linear internal dimension, birefringence and absorption coefficient, when measured at room temperature, is disclosed. Uses of the diamond material, including in a Raman laser, and methods of producing the diamond are also disclosed.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 28, 2015
    Assignee: Element Six Technologies Limited
    Inventors: Ian Friel, Sarah Louise Geoghegan, Daniel James Twitchen, Joseph Michael Dodson
  • Patent number: 9011599
    Abstract: A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jhi-Cherng Lu, Jr-Hung Li, Chii-Horng Li, Pang-Yen Tsai, Bing-Hung Chen, Tze-Liang Lee
  • Patent number: 9005363
    Abstract: Methods of depositing thin film materials having crystalline content are provided. The methods use plasma enhanced chemical vapor deposition. According to one embodiment of the present invention, microcrystalline silicon films are obtained. According to a second embodiment of the present invention, crystalline films of zinc oxide are obtained. According to a third embodiment of the present invention, crystalline films of iron oxide are obtained.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Sencera Energy, Inc.
    Inventors: Russell F Jewett, Steven F Pugh, Paul Wickboldt
  • Publication number: 20150096488
    Abstract: The present disclosure generally relates to systems and methods for growing and preferentially volumetrically enhancing group III-V nitride crystals. In particular the systems and methods include diffusing constituent species of the crystals through a porous body composed of the constituent species, where the species freely nucleate to grow large nitride crystals. The systems and methods further include using thermal gradients and/or chemical driving agents to enhance or limit crystal growth in one or more planes.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 9, 2015
    Inventors: Peng Lu, Jason Schmitt
  • Publication number: 20150079329
    Abstract: Bulk single crystals of AlN having a diameter greater than about 25 mm and dislocation densities of about 10,000 cm?2 or less and high-quality AlN substrates having surfaces of any desired crystallographic orientation fabricated from these bulk crystals.
    Type: Application
    Filed: October 22, 2014
    Publication date: March 19, 2015
    Inventors: Leo Schowalter, Glen A. Slack, Juan Carlos Rojo, Robert T. Bondokov, Kenneth E. Morgan, Joseph A. Smart