Material Removal (e.g., Etching, Cleaning, Polishing) Patents (Class 117/97)
  • Patent number: 8652255
    Abstract: A method of: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxial grow silicon carbide on a wafer in the growth chamber; stopping or reducing the flow of the silicon source gas to interrupt the silicon carbide growth and maintaining the flow of the carrier gas while maintaining an elevated temperature in the growth chamber for a period of time; and resuming the flow of the silicon source gas to reinitiate silicon carbide growth. The wafer remains in the growth chamber throughout the method.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 18, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Robert E Stahlbush, Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, David Kurt Gaskill, Charles R. Eddy, Jr.
  • Publication number: 20140014030
    Abstract: In some embodiments, the present disclosure pertains to methods of forming single-crystal graphenes by: (1) cleaning a surface of a catalyst; (2) annealing the surface of the catalyst; (3) applying a carbon source to the surface of the catalyst; and (4) growing single-crystal graphene on the surface of the catalyst from the carbon source. Further embodiments of the present disclosure also include a step of separating the formed single-crystal graphene from the surface of the catalyst. In some embodiments, the methods of the present disclosure also include a step of transferring the formed single-crystal graphene to a substrate. Additional embodiments of the present disclosure also include a step of growing stacks of single crystals of graphene.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 16, 2014
    Applicant: William Marsh Rice University
    Inventors: James M. Tour, Zheng Yan
  • Patent number: 8591652
    Abstract: The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the material for forming the mask layer consists at least partially of tungsten silicide nitride or tungsten silicide and wherein the semiconductor substrate self-separates from the starting substrate without further process steps.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 26, 2013
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Christian Hennig, Markus Weyers, Eberhard Richter, Guenther Traenkle
  • Patent number: 8580035
    Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities—e.g., a dislocation density below 104 cm?2 and an inclusion density below 104 cm?3 and/or a MV density below 104 cm?3.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 12, 2013
    Assignee: Crystal IS, Inc.
    Inventors: Robert Bondokov, Kenneth E. Morgan, Glen A. Slack, Leo J. Schowalter
  • Patent number: 8574528
    Abstract: A method of growing an epitaxial layer on a substrate is generally provided. According to the method, the substrate is heated in a chemical vapor deposition chamber to a growth temperature in the presence of a carbon source gas, then the epitaxial layer is grown on the substrate at the growth temperature, and finally the substrate is cooled in a chemical vapor deposition chamber to at least about 80% of the growth temperature in the presence of a carbon source gas. Substrates formed from this method can have a carrier lifetime between about 0.25 ?s and about 9.9 ?s.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: November 5, 2013
    Assignee: University of South Carolina
    Inventors: Tangali S. Sudarshan, Amitesh Srivastava
  • Patent number: 8541313
    Abstract: A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: September 24, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stéphan Borel, Jeremy Bilde
  • Publication number: 20130240876
    Abstract: The present invention relates to a method for growing a novel non-polar (13 40) plane epitaxy layer of wurtzite structure, which comprises the following steps: providing a single crystal oxide with perovskite structure; using a plane of the single crystal oxide as a substrate; and forming a non-polar (13 40) plane epitaxy layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process. The present invention also provides an epitaxy layer having non-polar (13 40) plane obtained according to the aforementioned method.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 19, 2013
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Li CHANG, Yen-Teng HO
  • Publication number: 20130239879
    Abstract: A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second port in communication with the lower portion of the chamber. The load lock includes a rack disposed within the chamber and a workpiece holder mounted on a first surface of the rack, wherein the rack and the workpiece holder are movable by an indexer that is capable of selectively moving wafer slots of the rack into communication with the second port. The indexer can also move the rack into an uppermost position, at which the first surface of the boat and the partition sealingly separate the upper portion and the lower portion to define an upper chamber and a lower chamber. Auxiliary processing, such as wafer pre-cleaning, or metrology can be conducted in the upper portion.
    Type: Application
    Filed: May 8, 2013
    Publication date: September 19, 2013
    Applicant: ASM AMERICA, INC.
    Inventors: Ravinder K. Aggarwal, Jeroen Stoutjesdijk, Eric R. Hill, Loring G. Davis, John T. DiSanto
  • Patent number: 8536030
    Abstract: A method of manufacturing a semipolar semiconductor crystal comprising a group-III-nitride (III-N), the method comprising: providing a substrate comprising sapphire (Al2O3) having a first surface that intersects c-planes of the sapphire; forming a plurality of trenches in the first surface, each trench having a wall whose surface is substantially parallel to a c-plane of the substrate; epitaxially growing a group-III-nitride (III-N) material in the trenches on the c-plane surfaces of their walls until the material overgrows the trenches to form a second planar surface, substantially parallel to a (20-2l) crystallographic plane of the group-III-nitride, wherein l is an integer.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: September 17, 2013
    Assignee: Freiberger Compund Materials GmbH
    Inventors: Thomas Wunderer, Stephan Schwaiger, Ilona Argut, Rudolph Rosch, Frank Lipski, Ferdinand Scholz
  • Patent number: 8501143
    Abstract: A single crystal diamond prepared by CVD and having one or more electronic characteristics; making the diamond suitable for electronic applications. Also provided is a method of making the single crystal CVD diamond.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: August 6, 2013
    Assignee: Element Six Ltd.
    Inventors: Geoffrey Alan Scarsbrook, Philip Maurice Martineau, John Lloyd Collins, Ricardo Simon Sussmann, Bärbel Susanne Charlotte Dorn, Andrew John Whitehead, Daniel James Twitchen
  • Publication number: 20130145984
    Abstract: This invention relates to a method of epitaxial growth effectively preventing auto-doping effect. This method starts with the removal of impurities from the semiconductor substrate having heavily-doped buried layer region and from the inner wall of reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions so as to remove moisture and oxide from the surface of said semiconductor substrate before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate where the dopant atoms have been extracted out. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling.
    Type: Application
    Filed: June 27, 2011
    Publication date: June 13, 2013
    Inventors: Chao Zhang, Zhitang Song, Xudong Wan, Bo Liu, Guanping Wu, Ting Zhang, Zuoya Yang
  • Patent number: 8460464
    Abstract: A method for producing one or more single crystalline diamonds. The method comprises placing one or more substrates on a substrate holder in chemical vapor vaporization (CVD) chamber. A mixture of gases including at least one gas having a carbon component is provided adjacent to the one or more substrates in the CVD chamber. Thereafter, the mixture of gases is exposed to microwave radiation to generate a plasma. Reactive species of nitrogen produced in a remote reactive gas generator are introduced in the plasma. Then, the one or more substrates are exposed to the plasma, such that diamond growth occurs at a rate of 10 to 100 microns per hour, to produce one or more single crystalline diamonds.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: June 11, 2013
    Inventor: Rajneesh Bhandari
  • Patent number: 8420041
    Abstract: The present invention discloses a high-pressure vessel of large size formed with a limited size of e.g. Ni—Cr based precipitation hardenable superalloy. Vessel may have multiple zones. For instance, the high-pressure vessel may be divided into at least three regions with flow-restricting devices and the crystallization region is set higher temperature than other regions. This structure helps to reliably seal both ends of the high-pressure vessel, at the same time, may help to greatly reduce unfavorable precipitation of group III nitride at the bottom of the vessel. Invention also discloses novel procedures to grow crystals with improved purity, transparency and structural quality. Alkali metal-containing mineralizers are charged with minimum exposure to oxygen and moisture until the high-pressure vessel is filled with ammonia. Several methods to reduce oxygen contamination during the process steps are presented.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 16, 2013
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts, Masanori Ikari
  • Publication number: 20130062628
    Abstract: A method for the epitaxial growth of SiC is described which includes contacting a surface of a substrate with hydrogen and HCl, subsequently increasing the temperature of the substrate to at least 1550° C. and epitaxially growing SiC on the surface of the substrate. A method for the epitaxial growth of SiC is also described which includes heating a substrate to a temperature of at least 1550° C., contacting a surface of the substrate with a C containing gas and a Si containing gas at a C/Si ratio of 0.5-0.8 to form a SiC buffer layer and subsequently contacting the surface with a C containing gas and a Si containing gas at a C/Si ratio >0.8 to form a SiC epitaxial layer on the SiC buffer layer. The method results in silicon carbide epitaxial layers with improved surface morphology.
    Type: Application
    Filed: August 21, 2012
    Publication date: March 14, 2013
    Applicant: SEMISOUTH LABORATORIES, INC.
    Inventors: Hrishikesh DAS, Swapna SUNKARI, Timothy OLDHAM, Janna B. CASADY
  • Patent number: 8394197
    Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 12, 2013
    Assignee: Sub-One Technology, Inc.
    Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
  • Publication number: 20130059124
    Abstract: An R-cut substrate is prepared by cutting lumbered synthetic quartz crystal along a surface parallel to the R-face. The surface of the thus obtained R-cut substrate has a structure in which the R-face smoothest in terms of the crystal structure accounts for the most part of the surface, and the m- and r-faces are exposed on this surface to extend in a direction parallel to the X-axis albeit only slightly upon processing. After catalytic metals are arranged on the surface of the R-cut substrate, a carbon source gas is supplied onto the surface of the R-cut substrate to grow carbon nanotubes in accordance with the crystal lattice structure using the crystal metals as nuclei. This makes it possible to manufacture carbon nanotubes with a good orientation and linearity.
    Type: Application
    Filed: March 1, 2011
    Publication date: March 7, 2013
    Inventors: Shigeo Maruyama, Shohei Chiashi, Hiroto Okabe, Masami Terasawa, Shuichi Kono, Tadashi Sato
  • Patent number: 8372198
    Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: February 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
  • Publication number: 20130022773
    Abstract: Provided are a single-crystal substrate for epitaxial growth on which a crystalline film may be formed with stress thereon being suppressed or eliminated, a single-crystal substrate having a crystalline film, a crystalline film, a method of producing a single-crystal substrate having a crystalline film, a method of producing a crystalline substrate, and an element producing method. The single-crystal substrate has a roughened surface formed on at least a partial region of a surface of the single-crystal substrate. And in order to obtain the single-crystal substrate having a crystalline film, a single-crystalline film is formed by epitaxial growth on a roughened-surface unformed surface on which the roughened surface is not formed, and a crystalline film having low crystallinity than the single-crystalline film is formed by epitaxial growth on a roughened-surface formed surface of the single-crystal substrate.
    Type: Application
    Filed: April 6, 2011
    Publication date: January 24, 2013
    Applicant: NAMIKI SEIMITSU HOUSEKI KABUSHIKIKAISHA
    Inventors: Hideo Aida, Natsuko Aota
  • Patent number: 8357243
    Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: January 22, 2013
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Masanori Ikari, Edward Letts
  • Patent number: 8349076
    Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: January 8, 2013
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventors: In-Jae Song, Jai-yong Han
  • Patent number: 8349077
    Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities—e.g., a dislocation density below 104 cm?2 and an inclusion density below 104 cm?3 and/or a MV density below 104 cm?3.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: January 8, 2013
    Assignee: Crystal IS, Inc.
    Inventors: Robert T. Bondokov, Kenneth Morgan, Glen A. Slack, Leo J. Schowalter
  • Patent number: 8334156
    Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 ?m. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol Kyu Kim, Yung Ho Ryu, Soo Min Lee, Jong In Yang, Tae Hyung Kim
  • Patent number: 8328935
    Abstract: The present invention is a method of manufacturing polycrystalline silicon rods, wherein silicon is deposited onto a silicon core wire by a chemical vapor deposition (CVD) method such that a silicon member, which is cut out from a single-crystalline silicon ingot at an off-angle range of 5 to 40 degrees relative to a crystal habit line of the ingot, is used as the silicon core wire. The single-crystalline silicon ingot is preferably grown by a Czochralski (CZ) method or floating zone (FZ) method, such that the ingot preferably has an interstitial oxygen concentration of 7 ppma to 20 ppma. Silicon rods produced by this method are less likely to suffer a breakage caused by cleavage during the growth process of polycrystalline silicon during CVD, and exhibit improved FZ method success rates. The polycrystalline silicon rods produced by this method also have low impurity contamination and high single-crystallization efficiency.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: December 11, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Michihiro Mizuno, Shinichi Kurotani, Shigeyoshi Netsu, Kyoji Oguro
  • Patent number: 8323402
    Abstract: Methods of growing and manufacturing aluminum nitride crystal, and aluminum nitride crystal produced by the methods. Preventing sublimation of the starting substrate allows aluminum nitride crystal of excellent crystallinity to be grown at improved growth rates. The aluminum nitride crystal growth method includes the following steps. Initially, a laminar baseplate is prepared, furnished with a starting substrate having a major surface and a back side, a first layer formed on the back side, and a second layer formed on the first layer. Aluminum nitride crystal is then grown onto the major surface of the starting substrate by vapor deposition. The first layer is made of a substance that at the temperatures at which the aluminum nitride crystal is grown is less liable to sublimate than the starting substrate. The second layer is made of a substance whose thermal conductivity is higher than that of the first layer.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: December 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keisuke Tanizaki, Naho Mizuhara, Michimasa Miyanaga, Hideaki Nakahata, Yoshiyuki Yamamoto
  • Publication number: 20120269717
    Abstract: The present application relates generally to methods for growth of high quality graphene films. In particular, a method is provided for forming a graphene film using a modified chemical vapor deposition process using an oxygen-containing hydrocarbon liquid precursor. Desirably, the graphene films are a single-layer and have a single grain continuity of at least 1 ?m2.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Applicant: THE AEROSPACE CORPORATION
    Inventors: Gouri Radhakrishnan, Paul Michael Adams
  • Publication number: 20120258286
    Abstract: A surface of a sapphire (0001) substrate is processed to form recesses and protrusions so that protrusion tops are flat and a given plane-view pattern is provided. An initial-stage AlN layer is grown on the surface of the sapphire (0001) substrate having recesses and protrusions by performing a C+ orientation control so that a C+ oriented AlN layer is grown on flat surfaces of the protrusion tops, excluding edges, in such a thickness that the recesses are not completely filled and the openings of the recesses are not closed. An AlxGayN(0001) layer (1?x>0, x+y=1) is epitaxially grown on the initial-stage AlN layer by a lateral overgrowth method. The recesses are covered with the AlxGayN(0001) layer laterally overgrown from above the protrusion tops. Thus, an template for epitaxial growth having a fine and flat surface and a reduced threading dislocation density is produced.
    Type: Application
    Filed: December 25, 2009
    Publication date: October 11, 2012
    Applicant: Soko Kagaku Co., Ltd.,
    Inventors: Hiroshi Amano, Satoshi Kamiyama, Myunghee Kim, Cyril Pernot, Akira Hirano
  • Publication number: 20120234230
    Abstract: A system and methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. The system is configured with an upper bank of heat elements perpendicular to the gas flow path, such that when the substrate is heated, the temperature across the substrate can be maintained relatively uniform via zoned heating. Advantageously, a short, low temperature process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 20, 2012
    Applicant: ASM America, Inc.
    Inventors: Michael W. Halpin, Paul T. Jacobson
  • Patent number: 8263984
    Abstract: In some embodiments, the invention relates to a process for making a GaN substrate comprising: transferring a first monocrystal GaN layer onto a supporting substrate; applying crystal growth for a second monocrystal GaN layer on the first layer; the first and second GaN layers thereby forming together the GaN substrate, the GaN substrate having a thickness of at least 10 micrometers, and removing at least one portion of the supporting substrate.
    Type: Grant
    Filed: November 11, 2007
    Date of Patent: September 11, 2012
    Assignee: Soitec
    Inventor: Bruce Faure
  • Patent number: 8241422
    Abstract: It is provided a method of growing gallium nitride single crystal of good quality with a high productivity, in the growth of gallium nitride single crystal by Na-flux method. Gallium nitride single crystal is grown using flux 8 containing at least sodium metal. Gallium nitride single crystal is grown in atmosphere composed of gases mixture “B” containing nitrogen gas at a pressure of 300 atms or higher and 2000 atms or lower. Preferably, the nitrogen partial pressure in the atmosphere is 100 atms or higher and 2000 atms or lower. Preferably, the growth temperature is 1000° C. or higher and 1500° C. or lower.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: August 14, 2012
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Iwai, Katsuhiro Imai, Minoru Imaeda
  • Patent number: 8241423
    Abstract: A semiconductor wafer for an epitaxial growth is disclosed comprising: a main face on which a vapor phase epitaxial layer grows; a back face provided on an opposite side of the wafer; a main chamfered part along a circumferential edge where the main face and a side face of the wafer meet; and a back chamfered part along a circumferential edge where the back face and the side face meet is provided. After a CVD layer formation process is conducted to form a layer at least on the back face and the back chamfered part, a machining process is conducted on the main face to remove a CVD layer at least partially formed thereon so as to polish the main face to a mirror finished surface with a maximum height of profile (Rz) not exceeding 0.3 ?m.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 14, 2012
    Assignee: Sumco Techxiv Corporation
    Inventors: Eisyun Ikubo, Naoto Hirano, Moritaka Iwasa
  • Patent number: 8236267
    Abstract: The present invention discloses a high-pressure vessel of large size formed with a limited size of e.g. Ni—Cr based precipitation hardenable superalloy. The vessel may have multiple zones. For instance, the high-pressure vessel may be divided into at least three regions with flow-restricting devices and the crystallization region is set higher temperature than other regions. This structure helps to reliably seal both ends of the high-pressure vessel, and at the same time, may help to greatly reduce unfavorable precipitation of group III nitride at the bottom of the vessel. This invention also discloses novel procedures to grow crystals with improved purity, transparency and structural quality. Alkali metal-containing mineralizers are charged with minimum exposure to oxygen and moisture until the high-pressure vessel is filled with ammonia. Several methods to reduce oxygen contamination during the process steps are presented.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: August 7, 2012
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts, Masanori Ikari
  • Publication number: 20120180716
    Abstract: Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial silicon growth, in order to clean the wafers. The methods exhibit enhanced selectivity and reduced lateral growth of epitaxial silicon. The wafers may have dielectric areas that are passivated by the exposure of the wafer to a plasma.
    Type: Application
    Filed: March 2, 2012
    Publication date: July 19, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Jingyan Zhang, Er-Xuan Ping
  • Patent number: 8221548
    Abstract: A process for producing a diamond thin-film includes forming a diamond crystal thin-film on a substrate and firing the diamond crystal thin-film at a sufficient temperature under high pressure under which a diamond is stable. A diamond single-crystal substrate having a diamond single-crystal thin-film formed thereon is placed in an ultra-high-pressure and high-temperature firing furnace to anneal the diamond single-crystal thin-film under the conditions of 1200° C. and 6 GPa.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 17, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Patent number: 8216367
    Abstract: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 10, 2012
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Publication number: 20120167819
    Abstract: The disclosed subject matter pertains to deposition of thin film or thin foil materials in general, but more specifically to deposition of epitaxial monocrystalline or quasi-monocrystalline silicon film (epi film) for use in manufacturing of high efficiency solar cells. In operation, methods are disclosed which extend the reusable life and to reduce the amortized cost of a substrate or template used in the manufacturing process of silicon solar cells. Further, methods are disclosed which provide for the conversion of a low quality starting surface into an improved quality starting surface of a silicon wafer.
    Type: Application
    Filed: December 31, 2011
    Publication date: July 5, 2012
    Applicant: SOLEXEL, INC.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, David Xuan-Qi Wang, Rahim Kavari, Rafael Ricolcol, Jay Ashjaee
  • Publication number: 20120162766
    Abstract: A polarizer is provided comprising: a transparent substrate, on a main surface of which a plurality of grooves in parallel with each other are provided at an interval; a birefringence crystal layer with a single orientation formed on the main surface of the transparent substrate where the grooves are provided, wherein the birefringence crystal layer is at least filled in the grooves so that linearly polarized light incident on a location corresponding to the grooves and passing through the polarizer is converted into first polarized light, and linearly polarized light incident on a location between the grooves and passing through the polarizer is converted into second polarized light, the polarization directions of the first and the second polarized light are different from each other.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 28, 2012
    Applicants: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yun Bok LEE, Ku Hyun PARK
  • Publication number: 20120145070
    Abstract: A process for advantageously producing a graphene/SiC composite material is provided in which a large-area graphene layer that is flat in an atomic level is formed on a SiC single crystal substrate. The process for producing a graphene/SiC composite material in which at least one graphene layer is formed on a SiC single crystal substrate, comprising the steps of: removing an oxide film that is formed by natural oxidation and covers a surface of the SIC single crystal substrate, thereby exposing a Si surface of the SiC single crystal substrate, heating the SiC single crystal substrate with the Si surface exposed under an oxygen atmosphere, thereby forming a SiO2 layer on the surface of the SiC single crystal substrate, and heating the SiC single crystal substrate under vacuum on which the SiO2 layer was formed.
    Type: Application
    Filed: January 20, 2012
    Publication date: June 14, 2012
    Applicant: National University Corporation Nagoya University
    Inventors: Michiko KUSUNOKI, Wataru NORIMATSU
  • Patent number: 8197598
    Abstract: A method for making iron silicide nano-wires comprises the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of iron powder into the reacting room. Thirdly, introducing a silicon-containing gas into the reacting room. Finally, heating the reacting room to a temperature of 600˜1200° C.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: June 12, 2012
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8187377
    Abstract: The present invention provides for treating a surface of a semiconductor material. The method comprises exposing the surface of the semiconductor material to a halogen etchant in a hydrogen environment at an elevated temperature. The method controls the surface roughness of the semiconductor material. The method also has the unexpected benefit of reducing dislocations in the semiconductor material.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: May 29, 2012
    Assignee: Silicon Genesis Corporation
    Inventors: Igor J. Malik, Sien G. Kang, Martin Fuerfanger, Harry Kirk, Ariel Flat, Michael Ira Current, Philip James Ong
  • Patent number: 8187956
    Abstract: A method for forming a microcrystalline semiconductor film over a base formed of a different material, which has high crystallinity in the entire film and at an interface with the base, is proposed. Further, a method for manufacturing a thin film transistor including a microcrystalline semiconductor film with high crystallinity is proposed. Furthermore, a method for manufacturing a photoelectric conversion device including a microcrystalline semiconductor film with high crystallinity is proposed. By forming crystal nuclei with high density and high crystallinity over a base film and then growing crystals in a semiconductor from the crystal nuclei, a microcrystalline semiconductor film which has high crystallinity at an interface with the base film, which has high crystallinity in crystal grains, and which has high adhesion between the adjacent crystal grains is formed.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: May 29, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Hidekazu Miyairi, Koji Dairiki
  • Patent number: 8168000
    Abstract: A method of fabricating a III-nitride power semiconductor device which includes selective prevention of the growth of III-nitride semiconductor bodies to selected areas on a substrate in order to reduce stresses and prevent cracking.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: May 1, 2012
    Assignee: International Rectifier Corporation
    Inventors: Mike Briere, Robert Beach
  • Publication number: 20120090536
    Abstract: The method for producing a silicon epitaxial wafer according to the present invention has: a growth step G at which an epitaxial layer is grown on a silicon single crystal substrate; a first polishing step E at which, before the growth step G, both main surfaces of the silicon single crystal substrate are subjected to rough polishing simultaneously; and a second polishing step H at which, after the growth step G, the both main surfaces of the silicon single crystal substrate are subjected to finish polishing simultaneously.
    Type: Application
    Filed: May 7, 2010
    Publication date: April 19, 2012
    Applicant: SUMCO CORPORATION
    Inventors: Masayuki Ishibashi, Tomonori Miura
  • Patent number: 8142566
    Abstract: A Ga-containing nitride semiconductor single crystal characterized in that (a) the maximum reflectance measured by irradiating the Ga-containing nitride semiconductor single crystal with light at a wavelength of 450 nm is 20% or less and the difference between the maximum reflectance and the minimum reflectance is within 10%, (b) the ratio of maximum value to minimum value (maximum value/minimum value) of the dislocation density measured by a cathode luminescence method is 10 or less, and/or (c) the lifetime measured by a time-resolved photoluminescence method is 95 ps or more.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: March 27, 2012
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Kazumasa Kiyomi, Hirobumi Nagaoka, Hirotaka Oota, Isao Fujimura
  • Patent number: 8133321
    Abstract: A process for producing a silicon carbide single crystal in which a silicon carbide single crystal layer is homo-epitaxially or hetero-epitaxially grown on a surface of a single crystal substrate, wherein a plurality of substantially parallel undulation ridges that extend in a first direction on the single crystal substrate surface is formed on said single crystal substrate surface; each of the undulation ridges on said single crystal substrate surface has a height that undulates as each of the undulation ridges extends in the first direction; and the undulation ridges are disposed so that planar defects composed of anti-phase boundaries and/or twin bands that propagate together with the epitaxial growth of the silicon carbide single crystal merge with each other.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: March 13, 2012
    Assignee: Hoya Corporation
    Inventors: Takamitsu Kawahara, Kuniaki Yagi, Naoki Hatta, Hiroyuki Nagasawa
  • Publication number: 20120052656
    Abstract: Methods of fabricating dimensional silica-based substrates or structures comprising a porous silicon layers are contemplated. According to one embodiment, oxygen is extracted from the atomic elemental composition of a silica glass substrate by reacting a metallic gas with the substrate in a heated inert atmosphere to form a metal-oxygen complex along a surface of the substrate. The metal-oxygen complex is removed from the surface of the silica glass substrate to yield a crystalline porous silicon surface portion and one or more additional layers are formed over the crystalline porous silicon surface portion of the silica glass substrate to yield a dimensional silica-based substrate or structure comprising the porous silicon layer. Embodiments are also contemplated where the substrate is glass-based, but is not necessarily a silica-based glass substrate. Additional embodiments are disclosed and claimed.
    Type: Application
    Filed: May 4, 2011
    Publication date: March 1, 2012
    Inventors: Robert A. Bellman, Nicholas F. Borrelli, David A. Deneka, Shawn M. O'Malley, Vitor M. Schneider
  • Publication number: 20120017825
    Abstract: A method for growing a crystalline composition, the first crystalline composition may include gallium and nitrogen. The crystalline composition may have an infrared absorption peak at about 3175 cm?1, with an absorbance per unit thickness of greater than about 0.01 cm?1. In one embodiment, the composition ay have an amount of oxygen present in a concentration of less than about 3×1018 per cubic centimeter, and may be free of two-dimensional planar boundary defects in a determined volume of the first crystalline composition.
    Type: Application
    Filed: November 9, 2006
    Publication date: January 26, 2012
    Applicant: General Electric Company
    Inventors: Mark Philip D'Evelyn, Kristi Jean Narang, Dong-Sil Park, Huicong Hong, Xian-An Cao, Larry Qiang Zeng
  • Patent number: 8097080
    Abstract: A method of dividing single crystals, particularly of plates of parts thereof, is proposed, which can comprise: pre-adjusting the crystallographic cleavage plane (2?) relative to the cleavage device, setting a tensional intensity (K) by means of tensional fields (3?, 4?), determining an energy release rate G(?) in dependence from a possible deflection angle (?) from the cleavage plane (2?) upon crack propagation, controlling the tensional fields (3?, 4?) such that the crack further propagates in the single crystal, wherein G(0)?2?e(0) and simultaneously at least one of the following conditions is satisfied: ? ? G ? ? ? ? = 0 ? 2 ? ? e h ? ? if ? ? ? 2 ? G ? ? 2 ? 0 ? ? or ( 2.1 ) ? ? G ? ? ? ? 2 ? ? e h ? ? ? ? : ? ? 1 < ? < ? 2 . ( 2.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: January 17, 2012
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Ralf Hammer, Manfred Jurisch
  • Patent number: 8092597
    Abstract: Method for producing a III-N (AlN, GaN, AlxGa(1-x)N) crystal by Vapor Phase Epitaxy (VPE), the method comprising: providing a reactor having: a growth zone for growing a III-N crystal; a substrate holder located in the growth zone that supports at least one substrate on which to grow the III-N crystal; a gas supply system that delivers growth material for growing the III-N crystal to the growth zone from an outlet of the gas supply system; and a heating element that controls temperature in the reactor; determining three growth sub-zones in the growth zone for which a crystal grown in the growth sub-zones has respectively a concave, flat or convex curvature; growing the III-N crystal on a substrate in a growth region for which the crystal has a by desired curvature.
    Type: Grant
    Filed: January 22, 2011
    Date of Patent: January 10, 2012
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Vladimir A. Dmitriev, Yuri V. Melnik
  • Publication number: 20110300058
    Abstract: The present invention relates to a method for manufacturing graphene by vapour phase epitaxy on a substrate comprising a surface of SiC, characterized in that the process of sublimation of silicon from the substrate is controlled by a flow of an inert gas or a gas other than an inert gas through the epitaxial reactor. The invention also relates to graphene obtained by this method.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 8, 2011
    Applicant: INSTYTUT TECHNOLOGII MATERIALOW ELEKTRONICZNYCH
    Inventor: Wlodzimierz Strupinski
  • Publication number: 20110290176
    Abstract: Systems, methods, and apparatus are provided for using a cluster tool to pre-clean a substrate in a first processing chamber utilizing a first gas prior to epitaxial film formation, transfer the substrate from the first processing chamber to a second processing chamber through a transfer chamber under a vacuum, and form an epitaxial layer on the substrate in the second processing chamber without utilizing the first gas. Numerous additional aspects are disclosed.
    Type: Application
    Filed: August 9, 2011
    Publication date: December 1, 2011
    Applicant: Applied Materials, Inc.
    Inventor: Arkadii V. Samoilov