Silicon Or Germanium Containing Patents (Class 136/261)
  • Patent number: 10316247
    Abstract: An atom, molecule, atomic layer, or molecular layer is adhered to a carbon nanotube surface, or the surface is doped with the atom, molecule, atomic layer, or molecular layer, to form a deep localized level so that an exciton is localized. Alternatively, an atom, molecule, inorganic or organic substance of an atomic or molecular layer, a metal, a semiconductor, or an insulator is absorbed to, deposited on, or encapsulated in the carbon tube inside surface to make permittivity of the portion undergoing the absorption, deposition, or encapsulation higher than that of a clean portion free of the absorption, deposition, or encapsulation so that binding energy of the exciton in the clean portion is high, or reduce a band gap of the portion undergoing the absorption, deposition, or encapsulation so that the exciton is confined and localized in the clean portion or the position undergoing the absorption, deposition, or encapsulation.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: June 11, 2019
    Assignee: KEIO UNIVERSITY
    Inventor: Hideyuki Maki
  • Patent number: 10283279
    Abstract: A photoelectric conversion device of an embodiment includes, in sequence: a substrate; a first electrode; a photoelectric conversion layer containing a perovskite compound and a solvent; and a second electrode. The perovskite compound has a composition represented by a composition formula of ABX3. The A represents at least one selected from a monovalent cation of a metal element and a monovalent cation of an amine compound. The B represents a bivalent cation of a metal element. The X represents a monovalent anion of a halogen element. The number of molecules of the solvent with respect to one crystal lattice of the perovskite compound ranges from 0.004 to 0.5.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 7, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hyangmi Jung, Takeshi Gotanda
  • Patent number: 10263135
    Abstract: The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material, wherein a first doping region (5) is formed by means of ion implantation (S2) of a first dopant in a first surface (3a) of a semiconductor substrate (3), and a second doping region (7) is formed by means of ion implantation (S3) or thermal indiffusion of a second dopant in the second surface (3b) of the semiconductor substrate. After the doping of the second surface, a cap (9b) acting as an outdiffusion barrier for the second dopant is applied and an annealing step (S4) is subsequently carried out.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: April 16, 2019
    Assignee: ION BEAM SERVICES
    Inventors: Tim Boescke, Daniel Kania, Claus Schoellhorn
  • Patent number: 10256353
    Abstract: A solar cell can include a substrate of a first conductive type; an emitter region which is positioned at a front surface of the substrate and has a second conductive type different from the first conductive type; a back surface field region which is positioned at a back surface opposite the front surface of the substrate; a front passivation region including a plurality of layers which are sequentially positioned on the emitter region; a back passivation region including a plurality of layers which are sequentially positioned on the back surface field region; a front electrode part which passes through the front passivation region and is connected to the emitter region, wherein the front electrode part comprises a plurality of front electrodes that are apart from each other and a front bus bar connecting the plurality of front electrodes; a back electrode part which passes through the back passivation region and is connected to the back surface field region, wherein the back electrode part comprises a plural
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: April 9, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Juhwa Cheong, Yiyin Yu, Youngsung Yang, Yongduk Jin, Manhyo Ha, Seongeun Lee
  • Patent number: 10233338
    Abstract: Intercalation pastes for use with semiconductor devices are disclosed. The pastes contain precious metal particles, intercalating particles, and an organic vehicle and can be used to improve the material properties of metal particle layers. Specific formulations have been developed to be screen-printed directly onto a dried metal particle layer and fired to make a fired multilayer stack. The fired multilayer stack can be tailored to create a solderable surface, high mechanical strength, and low contact resistance. In some embodiments, the fired multilayer stack can etch through a dielectric layer to improve adhesion to a substrate. Such pastes can be used to increase the efficiency of silicon solar cells, specifically multi- and mono-crystalline silicon back-surface field (BSF), and passivated emitter and rear contact (PERC) photovoltaic cells. Other applications include integrated circuits and more broadly, electronic devices.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: March 19, 2019
    Assignee: PLANT PV, Inc.
    Inventors: Brian E. Hardin, Erik Sauar, Dhea Suseno, Jesse J. Hinricher, Jennifer Huang, Tom Yu-Tang Lin, Stephen T. Connor, Daniel J. Hellebusch, Craig H. Peters
  • Patent number: 10211345
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10181529
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: January 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10164255
    Abstract: A silicon material useful as a negative electrode active material is provided. The silicon material has a band gap within a range of greater than 1.1 eV and not greater than 1.7 eV. A secondary battery in which this silicon material is used as a negative electrode active material has improved initial efficiency.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: December 25, 2018
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Takashi Mohri, Masataka Nakanishi, Hiroki Oshima, Masanori Harata, Nobuhiro Goda
  • Patent number: 10128392
    Abstract: Solar cell arrangement of a thin film solar cell array on a substrate; each solar cell being layered with a bottom electrode, a photovoltaic active layer, a top electrode and an insulating layer. A first trench and a second trench parallel to the first trench at a first side, separate a first solar cell and an adjacent second solar cell. The first and second trenches are filled with insulating material. The first trench extends to the substrate. The second trench extends into the photovoltaic active layer below the top electrode. A third trench extending to the bottom electrode is between the first and second trench. A fourth trench extending to the top electrode is at a second side of the first trench. The third and fourth trench are filled with conductive material. A conductive bridge connects the third trench and the fourth trench across the first trench.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: November 13, 2018
    Assignee: Stichting Energieonderzoek Centrum Nederland
    Inventors: Johan Bosman, Tristram Budel
  • Patent number: 10121915
    Abstract: A method for manufacturing a solar cell includes forming a passivation layer on a rear surface of a substrate of a first conductivity type; forming connecting electrodes having a plurality of electrical contacts that are in contact with the rear surface of the substrate by using a first paste for a first temperature firing on portions of the passivation layer; and forming a rear electrode layer by using a second paste for a second temperature firing on the passivation layer and the plurality of electrical contacts, wherein a temperature of the second temperature firing is lower than a temperature of the first temperature firing.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: November 6, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Daeyong Lee, Junyong Ahn, Jihoon Ko
  • Patent number: 10079319
    Abstract: Solar cell fabrication using laser patterning of ion-implanted etch-resistant layers, and the resulting solar cells, are described. In an example, a back contact solar cell includes a maximum concentration of the approximately Gaussian distribution of P-type dopants approximately in the center of each of segmented P-type emitter regions between first and second sides of each of the segmented P-type emitter regions.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 18, 2018
    Assignee: SunPower Corporation
    Inventors: Staffan Westerberg, Alejandro Levander, Peter John Cousins
  • Patent number: 10079320
    Abstract: The invention provides an optoelectronic device comprising a porous material, which porous material comprises a semiconductor comprising a perovskite. The porous material may comprise a porous perovskite. Thus, the porous material may be a perovskite material which is itself porous. Additionally or alternatively, the porous material may comprise a porous dielectric scaffold material, such as alumina, and a coating disposed on a surface thereof, which coating comprises the semiconductor comprising the perovskite. Thus, in some embodiments the porosity arises from the dielectric scaffold rather than from the perovskite itself. The porous material is usually infiltrated by a charge transporting material such as a hole conductor, a liquid electrolyte, or an electron conductor. The invention further provides the use of the porous material as a semiconductor in an optoelectronic device. Further provided is the use of the porous material as a photosensitizing, semiconducting material in an optoelectronic device.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: September 18, 2018
    Assignee: OXFORD UNIVERSITY INNOVATION LIMITED
    Inventors: Henry Snaith, Michael Lee
  • Patent number: 10062800
    Abstract: A photovoltaic device is presented. The photovoltaic device includes a layer stack; and an absorber layer is disposed on the layer stack. The absorber layer includes selenium, and an atomic concentration of selenium varies non-linearly across a thickness of the absorber layer. A method of making a photovoltaic device is also presented.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: August 28, 2018
    Assignee: First Solar, Inc.
    Inventors: Holly Ann Blaydes, Kristian William Andreini, William Hullinger Huber, Eugene Thomas Hinners, Joseph John Shiang, Yong Liang, Jongwoo Choi, Adam Fraser Halverson
  • Patent number: 10030156
    Abstract: Disclosed herein is a conductive paste for forming a conductive film, including: (A) a conductive powder; (B) as a first additive, at least one selected from a first group consisting of Se, Te, a compound containing Se, and a compound containing Te; (C) as a second additive, a compound containing at least one element selected from a second group consisting of V, Nb, Ta, Sb, Bi, Mn, Ge, Si, and W; (D) glass frit; (E) an organic binder; and (F) a solvent.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: July 24, 2018
    Assignee: KYOTO ELEX CO., LTD.
    Inventors: Kazuya Takagi, Seiichi Nakatani, Kenichi Harigae, Nobuo Ochiai, Masashi Nakayama, Kairi Otani, Nozomu Hayashida
  • Patent number: 10002977
    Abstract: The invention relates to an electro-conductive paste comprising coarse SiO2 particles in the preparation of electrodes in solar cells, particularly in the preparation of electrodes in MWT solar cells, particularly in the preparation of the metal wrap through, or plug, electrode in such solar cells. In particular, the invention relates to a solar cell precursor, a process for preparing a solar cells, a solar cell and a module comprising solar cells. The invention relates to a solar cell precursor at least comprising as precursor parts: i) a wafer (101) with at least one hole (315) with a Si surface (113); ii) an electro-conductive paste (105) at least comprising as paste constituents: a) metallic particles; b) an inorganic reaction system; c) an organic vehicle; and d) inorganic oxide particles having no glass transition temperature below about 750° C. or a glass transition temperature which is at least about 50° C.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: June 19, 2018
    Assignee: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Lei Wang, Crystal J. Han, Matthias Hörteis
  • Patent number: 9972733
    Abstract: A method for fabricating a solar cell includes providing a first substrate with at least one protruding element on the first substrate. The method removes a portion of a lower conducting layer located on the first substrate, wherein the removed portion of the lower conducting layer is located near the at least one protruding element. The method removes a first portion of an active layer located on the lower conducting layer. The method deposits an upper conducting layer on the active layer, wherein the conducting layer covers the at least one protruding element. The method removes a portion of the upper conducting layer, wherein the removed portion of the upper conducting is located near the at least one protruding element.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Hans-Juergen Eickelmann, Ruediger Kellmann, Markus Schmidt
  • Patent number: 9966195
    Abstract: A layered perovskite structure comprising a substrate having an upper surface and a lower surface; and a layer of a perovskite film on the upper surface. A passivating layer may be applied to the upper surface of the substrate to which the perovskite film is attached. The passivating layer comprises at least one a chalcogenide-containing species with the general chemical formula (E3E4)N(E1E2)N?C?X where any one of E1, E2, E3 and E4 is independently selected from C1-C15 organic substituents comprising from 0 to 15 heteroatoms or hydrogen, and X is S, Se or Te, thiourea, thioacetamide, selenoacetamide, selenourea, H2S, H2Se, H2Te, or LXH wherein L is a Cn organic substituent comprising heteroatoms and X?S, Se, or Te. The substrate comprises PEDOT:PSS, and may further comprise a layered glass/ITO/PEDOT:PSS structure. A passivating layer is applied to the PEDOT:PSS layer, and a top electrode may be applied over the perovskite film.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 8, 2018
    Assignee: The United States of America, as represented by the Secretary of the Air Force
    Inventors: Santanu Bag, Michael F. Durstock
  • Patent number: 9966494
    Abstract: A method for manufacturing a polycrystalline silicon ingot includes steps of: a) melting a silicon material in a container disposed in a thermal field to form a molten silicon; b) controlling the thermal field to provide heat to the molten silicon from above the container and to solidify a portion of the molten silicon contacting a base part and at least a portion of a wall part proximate to the base part of the container to form a solid silicon crystalline isolation layer; and c) controlling the thermal field to continuously provide heat to the rest of the molten silicon from above the container and to solidify the rest of the molten silicon gradually from a bottom to a top of the rest of the molten silicon to form a polycrystalline silicon ingot.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: May 8, 2018
    Assignee: AUO CRYSTAL CORPORATION
    Inventors: Kuo-Chen Ho, Ya-Lu Tsai, Chien-Chia Tseng, Chia-Ying Yang
  • Patent number: 9960287
    Abstract: A passivation layer is deposited on a first portion of a region of the solar cell. A grid line is deposited on a second portion of the region. The passivation layer is annealed to drive chemical species from the passivation layer to deactivate an electrical activity of a dopant in the first portion of the region of the solar cell.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: May 1, 2018
    Assignee: PICASOLAR, INC.
    Inventors: Seth Daniel Shumate, Douglas Arthur Hutchings, Hafeezuddin Mohammed, Matthew Young, Scott Little
  • Patent number: 9954128
    Abstract: The present disclosure generally relates to a solar cell device that a first Bragg reflector disposed below a first solar cell and a second Bragg reflector disposed below the first Bragg reflector, wherein the first solar cell comprises a dilute nitride composition and has a first bandgap, wherein the first Bragg reflector is operable to reflect a first range of radiation wavelengths back into the first solar cell and the second Bragg reflector is operable to reflect a third range of wavelengths back into the first solar cell, and the first Bragg reflector and the second Bragg reflector are operable to cool the solar cell device by reflecting a second range of radiation wavelengths that are outside the photogeneration wavelength range of the first solar cell or that are weakly absorbed by the first solar cell.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: April 24, 2018
    Assignee: THE BOEING COMPANY
    Inventors: Richard R. King, Moran Haddad, Philip T. Chiu, Xingquan Liu, Christopher M. Fetzer
  • Patent number: 9938153
    Abstract: Embodiments herein provide a method of preparing Silicon (Si) from sand (SiO2).The method includes preparing sand particles with a size less than 50 microns. Further, the method includes obtaining Magnesium (Mg) particles with a size in range of 105-150 microns. Further, the method includes mixing sand and Mg particles in a predefined ratio to obtain a Sand-Magnesium (SM) mixture. Further, the method includes subjecting the SM mixture to heating at a temperature for a predefined time to obtain Si sample. Further, the method includes identifying un-reacted portion of Mg and sand particles. Furthermore, the method includes purifying byproducts of magnesium as well as un-reacted-magnesium and silica to obtain pure Si.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: April 10, 2018
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY
    Inventors: Mohammad Furquan, Savithri Vijayalakshmi, Sagar Mitra
  • Patent number: 9939511
    Abstract: A method of preparing an iron-implanted semiconductor wafer for use in surface photovoltage iron mapping and other evaluation techniques. A semiconductor wafer is implanted with iron through the at least two different regions of the front surface of the semiconductor at different iron implantation densities, and the iron-implanted semiconductor wafer is annealed at a temperature and duration sufficient to diffuse implanted iron into the bulk region of the semiconductor wafer.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 10, 2018
    Assignee: SunEdison Semiconductor Limited
    Inventors: Igor Rapoport, Robert James Crepin, Patrick Alan Taylor
  • Patent number: 9935296
    Abstract: A display device includes: light emitting units; a light absorbing unit that surrounds each of the light emitting units; and a low-reflection layer provided on the surfaces of the light emitting units and the surface of the light absorbing unit. The surface of the light absorbing unit is a corrugated surface that diffuses light, and the low-reflection layer is formed along the corrugated surface.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: April 3, 2018
    Assignee: Sony Corporation
    Inventors: Eigo Kubota, Jianglin Yue
  • Patent number: 9929297
    Abstract: A solar cell and a method for manufacturing the same are discussed. The solar cell includes a substrate containing impurities of a first conductive type, an emitter region which is positioned at a front surface of the substrate and contains impurities of a second conductive type opposite the first conductive type, a back passivation layer which is positioned on a back surface of the substrate and has openings, a back surface field region containing impurities of the first conductive type, a first electrode connected to the emitter region, and a second electrode connected to the back surface field region. The back surface field region includes a first back surface field region positioned on the back passivation layer and a second back surface field region, which is positioned at the back surface of the substrate exposed by the openings of the back passivation layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 27, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Eunhye Youn, Sangwook Park, Seunghwan Shim, Yujin Lee
  • Patent number: 9923161
    Abstract: A high-efficiency solar cell including an Indium, Gallium, Aluminum and Nitrogen (in a combination comprising InGaN, or InAlN, or InGaAlN) alloy which may be blended with a polyhedral oligomeric silsesquioxane (POSS) material, and which may include an absorption-enhancing layer including one of more of carbon nanotubes, quantum dots, and undulating or uneven surface topography.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 20, 2018
    Assignee: Lockheed Martin Corporation
    Inventors: Gregory T. Daly, Michael P. Whelan, Robert C. Bowen, Jr.
  • Patent number: 9911893
    Abstract: A method for manufacturing a polycrystalline silicon ingot includes steps of: a) melting a silicon material in a container disposed in a thermal field to form a molten silicon; b) controlling the thermal field to provide heat to the molten silicon from above the container and to solidify a portion of the molten silicon contacting a base part and at least a portion of a wall part proximate to the base part of the container to form a solid silicon crystalline isolation layer; and c) controlling the thermal field to continuously provide heat to the rest of the molten silicon from above the container and to solidify the rest of the molten silicon gradually from a bottom to a top of the rest of the molten silicon to form a polycrystalline silicon ingot.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: March 6, 2018
    Assignee: AUO CRYSTAL CORPORATION
    Inventors: Kuo-Chen Ho, Ya-Lu Tsai, Chien-Chia Tseng, Chia-Ying Yang
  • Patent number: 9871156
    Abstract: A method of manufacturing a solar cell, including the steps of: forming an SiNx film over a second principal surface of an n-type semiconductor substrate; forming a p-type diffusion layer over a first principal surface of the n-type semiconductor substrate after the SiNx film forming step; and forming an SiO2 film or an aluminum oxide film over the p-type diffusion layer.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: January 16, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Takenori Watabe, Hiroyuki Otsuka
  • Patent number: 9853180
    Abstract: A multijunction solar cell including an upper first solar subcell; a second solar subcell adjacent to the first solar subcell; a first graded interlayer adjacent to the second solar subcell; a third solar subcell adjacent to the first graded interlayer such that the third subcell is lattice mismatched with respect to the second subcell. A second graded interlayer is provided adjacent to the third solar subcell, and a lower fourth solar subcell is provided adjacent to the second graded interlayer, such that the fourth subcell is lattice mismatched with respect to the third subcell. An encapsulating layer composed of silicon nitride or titanium oxide disposed on the top surface of the solar cell, and an antireflection coating layer disposed over the encapsulating layer.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: December 26, 2017
    Assignee: SolAero Technologies Corp.
    Inventor: Arthur Cornfeld
  • Patent number: 9837575
    Abstract: The present invention provides a boron diffusion layer forming method capable of sufficiently oxidizing a boron silicide layer formed on a silicon substrate to remove it and obtaining a high-quality boron silicate glass layer. The present invention is a boron diffusion layer forming method of forming a boron diffusion layer on a silicon substrate by a boron diffusion process, the process including a first step of thermally diffusing boron on the silicon substrate and a second step of oxidizing a boron silicide layer formed on the silicon substrate at the first step, wherein the second step has a state at a temperature of 900° C. or higher and a treatment temperature at the first step or lower, for 15 minutes or more.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: December 5, 2017
    Assignee: PANASONIC PRODUCTION ENGINEERING CO., LTD.
    Inventors: Takayuki Ogino, Shinobu Gonsui, Futoshi Kato, Shogo Tasaka, Ryota Aono, Ryosuke Oku, Yasuyuki Kano, Shinji Goda, Naoki Ishikawa
  • Patent number: 9754980
    Abstract: An imaging device with excellent imaging performance is provided. An imaging device that easily performs imaging under a low illuminance condition is provided. A low power consumption imaging device is provided. An imaging device with small variations in characteristics between its pixels is provided. A highly integrated imaging device is provided. A photoelectric conversion element includes a first electrode, and a first layer, a second layer, and a third layer. The first layer is provided between the first electrode and the third layer. The second layer is provided between the first layer and the third layer. The first layer contains selenium. The second layer contains a metal oxide. The third layer contains a metal oxide and also contains at least one of a rare gas atom, phosphorus, and boron. The selenium may be crystalline selenium. The second layer may be a layer of an In—Ga—Zn oxide including c-axis-aligned crystals.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: September 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Riho Kataishi, Hiroshi Ohki, Yuichi Sato, Daisuke Matsubayashi
  • Patent number: 9735365
    Abstract: The present disclosure relates to a novel polymer compound and a method for preparing the same. More particularly, the present disclosure relates to a novel conductive low band gap electron donor polymer compound having high photon absorptivity and improved hole mobility, a method for preparing the same and an organic photovoltaic cell containing the same. Since the conductive polymer compound as a low band gap electron donor exhibits high photon absorptivity and superior hole mobility, it can be usefully used as a material for an organic optoelectronic device such as an organic photodiode (OPD), an organic thin-film transistor (OTFT), an organic light-emitting diode (OLED), an organic photovoltaic cell, etc. as well as in the development of a n-type material.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 15, 2017
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Bong Soo Kim, Hyo Sang Lee, Hong Gon Kim, Min Jae Ko, Doh-Kwon Lee, Jin Young Kim, Hae Jung Son
  • Patent number: 9692209
    Abstract: In a method of forming a photonic device, a first silicon electrode is formed, and then a germanium active layer is formed on the first silicon electrode while including n-type dopant atoms in the germanium layer, during formation of the layer, to produce a background electrical dopant concentration that is greater than an intrinsic dopant concentration of germanium. A second silicon electrode is then formed on a surface of the germanium active layer. The formed germanium active layer is doped with additional dopant for supporting an electrically-pumped guided mode as a laser gain medium with an electrically-activated n-type electrical dopant concentration that is greater than the background dopant concentration to overcome electrical losses of the photonic device.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: June 27, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Jonathan T. Bessette, Yan Cai, Rodolfo E. Camacho-Aguilera, Jifeng Liu, Lionel Kimerling, Jurgen Michel
  • Patent number: 9666738
    Abstract: A semifinished product of a multi-junction solar cell includes a first semiconductor body that is designed as a first partial solar cell and has a first band gap, a second semiconductor body that is designed as a second partial solar cell and has a second band gap. The first semiconductor body and the second semiconductor body form a bonded connection to a tunnel diode and the first band gap is different from the second band gap. A first substrate material is adapted as a substrate layer, wherein a sacrificial layer is formed between the first substrate material and the first partial solar cell and the first substrate material is removed from the first semiconductor body, the sacrificial layer being destroyed in the process.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: May 30, 2017
    Assignee: Azur Space Solar Power GmbH
    Inventor: Daniel Fuhrmann
  • Patent number: 9614169
    Abstract: A method is provided for forming a back contact perovskite solar cell. A substrate is coated with a positive electrode layer. The positive electrode layer is then conformally coated with a first insulator. A plurality of negative electrode segments are selectively deposited overlying the first insulator layer, and a second insulator layer is conformally deposited overlying the negative electrode segments and first insulator layer. The second insulator layer is selectively etched to expose the negative electrode segments, and an n-type semiconductor is selectively deposited overlying each exposed negative electrode segment to form n-type contacts. The first and second insulator layers are then selectively etched to expose positive electrode segments. A p-type semiconductor is selectively deposited over each exposed positive electrode segment to form p-type contacts. Finally, a hybrid organic/inorganic perovskite (e.g., CH3NH3Pbl3-XClX) layer is conformally deposited overlying the p-type and n-type contacts.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: April 4, 2017
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Alexey Koposov, Wei Pan
  • Patent number: 9589736
    Abstract: A dye-sensitized solar cell (DSC) element includes at least one DSC, and the DSC includes a first electrode, a second electrode facing the first electrode, and an oxide semiconductor layer provided on the first electrode. The oxide semiconductor layer includes a light absorbing layer provided on the first electrode and a reflecting layer as a layer contacting a portion of a first surface of a side opposite to the first electrode among surfaces of the light absorbing layer and being arranged at a position farthest from the first electrode. The first surface of the light absorbing layer includes a second surface contacting the reflecting layer, and a surface area S1 of the first surface and a surface area S2 of the second surface satisfy the following formula: 0.7?S2/S1<1 The reflecting layer is arranged in an inner side of the first surface of the light absorbing layer.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 7, 2017
    Assignee: FUJIKURA LTD.
    Inventor: Daisuke Matsumoto
  • Patent number: 9576799
    Abstract: Disclosed herein is a method for doping a substrate, comprising disposing a coating of a composition comprising a copolymer, a dopant precursor and a solvent on a substrate; where the copolymer is capable of phase segregating and embedding the dopant precursor while in solution; and annealing the substrate at a temperature of 750 to 1300° C. for 0.1 second to 24 hours to diffuse the dopant into the substrate. Disclosed herein too is a semiconductor substrate comprising embedded dopant domains of diameter 3 to 30 nanometers; where the domains comprise Group 13 or Group 15 atoms, wherein the embedded spherical domains are located within 30 nanometers of the substrate surface.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: February 21, 2017
    Assignees: DOW GLOBAL TECHNOLOGIES, LLC, ROHM AND HAAS ELECTRONIC MATERIALS LLC, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Rachel A. Segalman, Peter Trefonas, III, Bhooshan C. Popere, Andrew T. Heitsch
  • Patent number: 9508880
    Abstract: It is an object to provide a method for processing a silicon substrate that can reduce surface reflectance as much as possible. The method includes a first step of forming a thin film including a metal having higher electronegativity than silicon and having a plurality of openings on a silicon substrate, a second step of soaking the silicon substrate subjected to the first step in a hydrofluoric acid solution containing oxidizer, and a third step of soaking the silicon substrate subjected to the second step in an ammonia aqueous solution containing oxidizer. By performing the steps in the above order, a minute uneven structure is formed on a surface of the silicon substrate to reduce the reflectance.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: November 29, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takashi Hirose, Ryosuke Motoyoshi
  • Patent number: 9490454
    Abstract: A method for producing high efficiency organic light emitting devices, that have an organic semiconductor active layer sandwiched between electrodes where at least one of the electrodes is a film of conductive nanowires, carbon nanoparticles, light scattering nanoparticles and a polymer support. The light scattering nanoparticles can be incorporated in the conductive nanowires, carbon nanoparticle or polymer support elements of the electrode. The second electrode can be identical to the first to provide a symmetrical device or can be a conductive paste or metal layer. The entire process, including the formation of both of the electrodes, the emissive polymer layer, and the substrate, may be carried out by solution processing.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: November 8, 2016
    Assignee: The Regents of the University of California
    Inventor: Qibing Pei
  • Patent number: 9416446
    Abstract: Provided is a semiconductor device manufacturing method of forming a film of less than one atomic layer on a substrate. The method includes (a) supplying a source gas into a processing chamber accommodating the substrate to adsorb the source gas on the substrate; (b) supplying a reactive gas different from the source gas into the processing chamber to cause a reaction of the reactive gas with the source gas adsorbed on the substrate before the source gas is saturatively adsorbed on the substrate; (c) removing an inner atmosphere of the processing chamber; and (d) supplying a modifying gas into the processing chamber to modify the source gas adsorbed on the substrate.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: August 16, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tatsuyuki Saito, Masanori Sakai, Yukinao Kaga, Takashi Yokogawa
  • Patent number: 9412897
    Abstract: A method of hydrogenation of a silicon photovoltaic junction device is provided, the silicon photovoltaic junction device comprising p-type silicon semiconductor material and n-type silicon semiconductor material forming at least one p-n junction. The method comprises: i) ensuring that any silicon surface phosphorus diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1020 atoms/cm3 or less and silicon surface boron diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1019 atoms/cm3 or less; ii) providing one or more hydrogen sources accessible by each surface of the device; and iii) heating the device, or a local region of the device to at least 40° C.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: August 9, 2016
    Assignee: NEWSOUTH INNOVATIONS PTY LIMITED
    Inventors: Stuart Ross Wenham, Phillip George Hamer, Brett Jason Hallam, Adeline Sugianto, Catherine Emily Chan, Lihui Song, Pei Hsuan Lu, Alison Maree Wenham, Ly Mai, Chee Mun Chong, GuangQi Xu, Matthew Edwards
  • Patent number: 9391287
    Abstract: A semiconductor device and a method for fabrication of the semiconductor device are described that include a perovskite layer formed using a solution process with lead iodine and methylammonium halide. In an implementation, a semiconductor device that employs example techniques in accordance with the present disclosure includes a cathode layer; an anode layer; and an active layer disposed between the cathode layer and the anode layer, where the active layer includes a perovskite layer including an interdiffused and annealed lead iodine (PbI2) film and methylammonium halide (CH3NH3X) film. In implementations, a process for fabricating a continuous-perovskite semiconductor device that employs example techniques in accordance with the present disclosure includes spinning a PbI2 layer onto an ITO-covered glass; spinning an MAI layer onto the PbI2 layer; annealing the PbI2 layer and the MAI layer; spinning a PCBM layer onto a resulting perovskite layer; and depositing an Al layer.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 12, 2016
    Assignee: THE BOARD OF REGENTS OF THE UNIVERSITY OF NEBRASKA
    Inventors: Jinsong Huang, Qingfeng Dong, Rui Dong, Yuchuan Sao, Cheng Bi, Qi Wang, Zhengguo Xiao
  • Patent number: 9356184
    Abstract: A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 31, 2016
    Assignee: SunPower Corporation
    Inventors: Ratson Morad, Gilad Almogy, Itai Suez, Jean Hummel, Nathan Beckett, Yafu Lin, Dan Maydan, John Gannon
  • Patent number: 9337367
    Abstract: A multiple-junction photoelectric device includes sequentially, a substrate, a first conducting layer, at least two elementary photoelectric devices, at least one of the elementary photoelectric devices being made of microcrystalline silicon, and a second conducting layer. The first conducting layer has a surface facing the microcrystalline silicon elementary photoelectric device such that the surface: has a lateral feature size bigger than 100 nm, and a root-element-square roughness bigger than 40 nm, includes inclined elementary surfaces such that ?50 is greater than 20°, where ?50 is the angle for which 50% of the elementary surfaces of the surface of the first conducting layer have an inclination equal to or less than this angle, and includes valleys formed between two elementary surfaces and having a radius of curvature smaller than 100 nm.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: May 10, 2016
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE
    Inventors: Peter Cuony, Matthieu Despeisse, Christophe Ballif, Gaetano Parascandolo
  • Patent number: 9318319
    Abstract: A method of performing a radical-enhanced atomic-layer deposition process on a surface of a substrate that resides within an interior of a reactor chamber is disclosed. The method includes forming plasma from a gas mixture consisting of CF4 and O2, wherein the CF4 is present in a concentration in the range from 0.1 vol % to 10 vol %. The plasma formed from the gas mixture generates oxygen radicals O* faster than if there were no CF4 present in the gas mixture. The method also includes feeding the oxygen radicals and a precursor gas sequentially into the interior of the reactor chamber to form an oxide film on the surface of the substrate. A system for performing the radical-enhanced atomic-layer deposition process using the rapidly formed oxygen radicals is also disclosed.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 19, 2016
    Assignee: Ultratech, Inc.
    Inventors: Arthur W. Zafiropoulo, Mark J. Sowa
  • Patent number: 9249257
    Abstract: A copolymer containing a repeating unit having a dioxopyrrole condensed ring skeleton and a repeating unit having a dithieno condensed ring skeleton and also having a specific substituent is provided.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: February 2, 2016
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Junya Kawai, Rieko Fujita, Wataru Sato, Mitsunori Furuya, Kenichi Satake, Maki Oba
  • Patent number: 9246114
    Abstract: Various embodiments may relate to an organic optoelectronic component with a layer structure for generating and separating charge carriers of a first charge carrier type and charge carriers of a second charge carrier type, the layer structure including a hole-conducting transparent inorganic semiconductor.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: January 26, 2016
    Assignee: OSRAM OLED GmbH
    Inventors: Carola Diez, Thilo Reusch
  • Patent number: 9224892
    Abstract: A method of increasing the haze of a coating stack having a top layer and an undercoating layer using a chemical vapor deposition coating process includes at least one of: increasing a precursor flow rate; decreasing a carrier gas flow rate; increasing a substrate temperature; increasing a water flow rate; decreasing an exhaust flow rate; and increasing a thickness of at least one of the top layer or undercoating layer.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: December 29, 2015
    Assignee: PPG Industries Ohio, Inc.
    Inventor: Songwei Lu
  • Patent number: 9224886
    Abstract: A silicon thin film solar cell is discussed. The silicon thin film solar cell includes a substrate on which light is incident, a first electrode positioned on the substrate at a surface opposite a surface of the substrate on which the solar light is incident, a second electrode positioned on the first electrode, at least one photoelectric conversion unit positioned between the first electrode and the second electrode, and a back reflection layer positioned between the at least one photoelectric conversion unit and the second electrode. The back reflection layer includes a first reflection layer formed of a material having an absorption coefficient equal to or less than 400 cm?1 with respect to light having a wavelength equal to or greater than 700 nm.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: December 29, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Suntae Hwang, Sehwon Ahn, Seungyoon Lee
  • Patent number: 9212254
    Abstract: A copolymer containing a repeating unit having a dioxopyrrole condensed ring skeleton and a repeating unit having a dithieno condensed ring skeleton and also having a specific substituent is provided.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: December 15, 2015
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Junya Kawai, Rieko Fujita, Wataru Sato, Mitsunori Furuya, Kenichi Satake, Maki Oba
  • Patent number: 9214577
    Abstract: Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a work function that falls substantially in a middle of a barrier formed between the transparent electrode and the p-type layer to provide a greater resistance to light induced degradation. An intrinsic layer and an n-type layer are formed over the p-type layer.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: December 15, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana