Having Glow Discharge Electrode Gas Energizing Means Patents (Class 156/345.43)
  • Publication number: 20080236752
    Abstract: A plasma processing apparatus capable of, over a prolonged period of time, controlling a decrease in the value of a DC current flowing within an accommodating compartment. The plasma processing apparatus comprises an accommodating compartment adapted to accommodate a substrate and perform a plasma treatment thereon, a high-frequency power source adapted to supply high-frequency power to the inside of the accommodating compartment; a DC electrode adapted to apply a DC voltage to the inside of the accommodating compartment, a ground electrode provided within the accommodating compartment and used for the applied DC voltage, and an exhaust unit adapted to evacuate the inside of the accommodating compartment.
    Type: Application
    Filed: March 24, 2008
    Publication date: October 2, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Masanobu HONDA
  • Patent number: 7426900
    Abstract: An integrated electrostatic inductively-coupled (i-ESIC) device is provided for plasma processing that may be used as a primary or secondary source for generating a plasma to prepare substrates for, and to process substrates by applying, dielectric and conductive coatings. The i-ESIC device is practical for processing advanced semiconductor devices and integrated circuits that require uniform and dense plasma. The invention may be embodied in an apparatus that contains a substrate support, typically including an electrostatic chuck, that controls ion energy by capacitively coupling RF power to the plasma and generating voltage bias on the wafer relative to the plasma potential. An integrated inductive coupling element is provided at the perimeter of the substrate support that increases plasma density at the perimeter of the wafer, compensating for the radial loss of charged particles toward chamber walls, to produce uniform plasma density above the processed wafer.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: September 23, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Jozef Brcka
  • Publication number: 20080206998
    Abstract: A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 28, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Woo Lee, Jin-Sung Kim, Joo-Byoung Yoon, Yeong-Cheol Lee, Sang-Jun Park, Hee-Kyeong Jeon
  • Publication number: 20080202689
    Abstract: A plasma processing apparatus includes: a chamber; an insulating member disposed in an upper portion of the chamber; a ground electrode formed at a side wall of the chamber, a ground potential being applied to the ground electrode; and a lower electrode disposed in a lower portion of the chamber, a substrate being placed on the lower electrode, wherein the lower electrode is divided into a plurality of electrodes. According to an aspect of the present invention, particles accumulated in the central portion on a lower surface, an edge area of an upper surface, a side, and an edge area of the lower surface of the substrate can be effectively removed.
    Type: Application
    Filed: May 1, 2008
    Publication date: August 28, 2008
    Applicant: TES CO., LTD.
    Inventor: Sung Ryul Kim
  • Patent number: 7415940
    Abstract: This invention includes a first filter (27) connected between a susceptor (21) and ground and having a variable impedance, a sensor (28) for detecting an electrical signal based on the state of a plasma (P) generated in a process chamber (11), and a control means (36) for controlling the impedance of the first filter (27) on the basis of a detection result output from the sensor (28). Thus, a preferable plasma distribution to match the object of the plasma process can be realized.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: August 26, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Chishio Koshimizu, Yohei Yamazawa
  • Publication number: 20080185105
    Abstract: Positional relationships are established in a process chamber. An upper electrode is configured with a first surface to support a wafer, and an electrode has a second surface. A linear drive is mounted on the base and a linkage connected between the drive and the upper electrode. Linkage adjustment defines a desired orientation between the surfaces. The linear drive and linkage maintain the desired orientation while the assembly moves the upper electrode with the surfaces moving relative to each other. An annular etching region defined between the electrodes enables etching of a wafer edge exclusion region extending along a top and bottom of the wafer. Removable etch defining rings are configured to define unique lengths along each of the top and bottom of the wafer to be etched. Positional relationships of the surfaces enable limiting the etching to those unique lengths of the exclusion region.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 7, 2008
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Andrew D. Bailey, Jack Chen, Yunsang Kim, Gregory S. Sexton
  • Publication number: 20080182412
    Abstract: A device for cleaning a bevel edge of a semiconductor substrate. The device includes: a lower support having a cylindrical top portion; a lower plasma-exclusion-zone (PEZ) ring surrounding the outer edge of the top portion and adapted to support the substrate; an upper dielectric component opposing the lower support and having a cylindrical bottom portion; an upper PEZ ring surrounding the outer edge of the bottom portion and opposing the lower PEZ ring; and at least one radiofrequency (RF) power source operative to energize process gas into plasma in an annular space defined by the upper and lower PEZ rings, wherein the annular space encloses the bevel edge.
    Type: Application
    Filed: January 26, 2007
    Publication date: July 31, 2008
    Applicant: Lam Research Corporation
    Inventors: Andrew D. Bailey III, Alan M. Schoepp, Gregory Sexton, Yunsang Kim, William S. Kennedy
  • Publication number: 20080179010
    Abstract: A bevel etcher incorporating a vacuum chuck used for cleaning the bevel edge and for reducing the bending curvature of a semiconductor substrate. The bevel etcher includes a vacuum chuck and a plasma generation unit which energizes process gas into a plasma state. The vacuum chuck includes a chuck body and a support ring. The top surface of the chuck body and inner periphery of the support ring form a vacuum region enclosed by the bottom surface of a substrate mounted on the support ring. A vacuum pump evacuates the vacuum region during operation. The vacuum chuck is operative to hold the substrate in place by the pressure difference between the top and bottom surfaces of the substrate. The pressure difference also generates a bending force to reduce the bending curvature of the substrate.
    Type: Application
    Filed: January 26, 2007
    Publication date: July 31, 2008
    Applicant: Lam Research Corporation
    Inventors: Andrew D. Bailey III, Alan M. Schoepp, Gregory Sexton, William S. Kennedy
  • Publication number: 20080179011
    Abstract: A plasma reactor includes an electrostatic chuck in the chamber for supporting the workpiece, a ceiling electrode facing the electrostatic chuck and an ESC electrode in the electrostatic chuck with an electrostatic clamping voltage supply coupled to the ESC electrode. The reactor further includes at least a first RF bias source of an LF or HF frequency coupled to the pedestal electrode, and first and second VHF power sources of different frequencies coupled to the same or to different ones of the electrodes. The first and second VHF power sources are of sufficiently high and sufficiently low frequencies, respectively, to produce center-high and center-low plasma distribution non-uniformities, respectively, in the chamber.
    Type: Application
    Filed: April 11, 2007
    Publication date: July 31, 2008
    Inventors: KENNETH S. COLLINS, Hiroji Hanawa, Kartik Ramaswamy, Douglas A. Buchberger, Shahid Rauf, Kallol Bera, Lawrence Wong, Walter R. Merry, Matthew L. Miller, Steven C. Shannon, Andrew Nguyen, James P. Cruse, James Carducci, Troy S. Detrick, Subhash Deshmukh, Jennifer Y. Sun
  • Patent number: 7404874
    Abstract: Method and apparatus for treating an edge region of a wafer. A toroidal shaped plasma cavity has an inner diameter which is slightly less than the diameter of the wafer being treated so that only the edge region of the wafer extends into the toroidal plasma cavity. An inert gas is flowed across a front and back side of the wafer into the plasma cavity. A reactive gas is flowed directly into the plasma cavity. The gases exit the plasma cavity without flowing over the surface of the wafer.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: July 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: William George America, Steven Hilton Johnston
  • Publication number: 20080156771
    Abstract: An etching apparatus using a neutral beam includes an electron emission unit to convert an ion beam, extracted from plasma by a plurality of grids, into a neutral beam by colliding the ion beam with electrons to prevent the ion beam from physically colliding with the electron emission unit, thus preventing the damage to a neutralization unit and generation of foreign substances with a simple structure. Further, the etching apparatus converts the ion beam into the neutral beam at a high neutralizing efficiency without causing directionality and energy losses, and generates a neutral beam having a large area, thus uniformly etching a semiconductor wafer.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 3, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yun Kwang JEON, Jin Seok Lee, Yung Hee Lee, Gi Tae Kim
  • Publication number: 20080156441
    Abstract: In a plasma apparatus 1 for performing plasma processing on a substrate W to be processed, an upper electrode 21, which faces opposite a susceptor 5 which is a lower electrode, has an electrode supporting body 22 and an electrode plate 23. In the center on the side of the electrode supporting body at the boundary between the two, a hollow 62, the dimensions of which are determined such that a resonance is generated at a frequency of supplied high-frequency electric power and an electric field orthogonal to the electrode plate 23 is generated inside, is provided. Furthermore, a shield ring which surrounds the electrode plate 23 has a shape in which the lower surface is in the same level as the electrode plate 23, and it is made of a material that is not easily eroded by the plasma. By this, processing small features becomes possible with uniform distribution of plasma and in less degradation due to change over time.
    Type: Application
    Filed: February 29, 2008
    Publication date: July 3, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Ogasawara, Kazuya Kato, Toshifumi Nagaiwa, Kosuke Imafuku, Koichi Kazama
  • Publication number: 20080142481
    Abstract: A plasma-processing chamber is configured with a particle collection conductor to remove charged particles from the chamber during plasma processing of substrates. The particle collection conductor is positioned in a processing region of the chamber and a power supply applies a DC bias to the conductor when plasma is present in the processing region. The conductor may comprise aluminum, and the power supply may be controlled by a plasma controller of the plasma-processing chamber. In one aspect, the conductor may be configured to translate through the processing region during substrate processing. A method is also provided for removing particles from the processing region of a plasma-processing chamber, comprising positioning a substrate in a processing chamber, flowing a processing gas into the processing chamber, generating a plasma in the processing chamber, and applying a DC bias to a particle collection conductor positioned in the processing chamber.
    Type: Application
    Filed: December 18, 2006
    Publication date: June 19, 2008
    Inventors: John M. White, Soo Young Choi
  • Patent number: 7387081
    Abstract: A device for forming an ion sheath in a plasma to deposit coatings on a non-conducting substrate. The device comprises a tubular reaction chamber having an outer surface wound helically with a first electrode having a first width. Helical winding of the first electrode provides a plurality of first wraps around the outer surface of the tubular reaction chamber. The device further includes a second electrode having a second width that is larger than the first width. Helical winding of the second electrode provides a plurality of second wraps alternating with the first wraps around the outer surface of the tubular reaction chamber. An ion sheath in a plasma forms to a thickness extending at least to the longitudinal axis of the tubular reaction chamber when the first electrode has a connection to a source of radio-frequency power and the second electrode provides a path to ground.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: June 17, 2008
    Assignee: 3M Innovative Properties Company
    Inventors: Moses M. David, Michael C. Gifford
  • Publication number: 20080135177
    Abstract: A plasma processing apparatus includes: a chamber; an insulating member disposed in an upper portion of the chamber; a ground electrode formed at a side wall of the chamber, a ground potential being applied to the ground electrode; and a lower electrode disposed in a lower portion of the chamber, a substrate being placed on the lower electrode, wherein the lower electrode is divided into a plurality of electrodes. According to an aspect of the present invention, particles accumulated in the central portion on a lower surface, an edge area of an upper surface, a side, and an edge area of the lower surface of the substrate can be effectively removed.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 12, 2008
    Applicant: TES CO., LTD.
    Inventor: Sung Ryul Kim
  • Patent number: 7381291
    Abstract: A dual-chamber plasma processing apparatus comprises two reaction spaces which are equipped with different gas inlet lines and different RF systems. Each reaction space is provided with an RF wave entry path and an RF wave return path to supply RF power from an RF power source and return RF power to the same RF power source.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: June 3, 2008
    Assignee: ASM Japan K.K.
    Inventors: Yasuhiro Tobe, Yoshinori Morisada, Shingo Ikeda, Baiei Kawano
  • Publication number: 20080121344
    Abstract: A plasma processing method for processing a sample by reducing a pressure within a processing chamber, including mounting the sample on a sample holder disposed in the processing chamber, and processing using a plasma generated in the processing chamber above the sample holder while supplying a gas for heat transfer to a space between a surface of the sample holder having the sample mounted thereon and a rear surface of the sample. The sample holder has a plurality of substantially ring-shaped depressed portions at the surface where the sample is mounted. A pressure in a space between the depressed portions arranged at a central portion of the sample holder with respect to outer circumferential portion and the sample is set to be lower than a pressure in a space between the depressed portions at the outer circumferential portion and the sample.
    Type: Application
    Filed: January 31, 2008
    Publication date: May 29, 2008
    Inventors: Tooru Aramaki, Tsunehiko Tsubone, Ryujiro Udo, Motohiko Yoshigai, Takashi Fujii
  • Publication number: 20080119049
    Abstract: A plasma etching method and apparatus. In the plasma etching apparatus, pluralities of RF power supplies are respectively connected to upper and lower electrode via relevant matching networks to enable generation of various ion densities and ion energies of plasma by individually changing RF powers applied to the upper and lower electrodes through control of the RF power supplies, so that the plasma etching apparatus can perform all processes which includes a process requiring a low ion density and a low ion energy, a process requiring the low ion density and a high ion energy, a process requiring a high ion density and the low ion energy, and a process requiring the high ion density and the high ion energy, thereby realizing various plasma etching processes.
    Type: Application
    Filed: April 24, 2007
    Publication date: May 22, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Doug Yong SUNG, Tae Yong Kwon
  • Patent number: 7347915
    Abstract: A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: March 25, 2008
    Assignee: LAM Research Corporation
    Inventors: Douglas L. Keil, Wan-Lin Chen, Eric A. Hudson, S. M. Reza Sadjadi, Mark H. Wilcoxson, Andrew D. Bailey, III
  • Publication number: 20080066679
    Abstract: A processing system is used for processing an object by a first fluid. The processing system includes a base and a plasma generation device. The base supports the object and the plasma generation device ionizes the first fluid. The plasma generation device includes at least one guiding element comprising a path guiding the first fluid to sequentially flow through a first position and a second position and at least one electrode element including a first electrode corresponding to the first position and a second electrode corresponding to the second position. The first and second electrodes energize the first fluid located between the first and second electrodes to form a second fluid, to thereby utilize the second fluid to perform surfacing, activating, cleaning, photoresist ashing or etching process on the object supported by the base.
    Type: Application
    Filed: November 29, 2006
    Publication date: March 20, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chi-Hung Liu, Wen-Tzong Hsieh, Chen-Der Tsai, Chun-Hsien Su, Chih Wei Chen, Chun-Hung Lin
  • Publication number: 20080066866
    Abstract: Some embodiments discussed relate to an apparatus for etching a semiconductor wafer and method for fabricating it, comprising a plurality of electrodes coupled to a power supply for generating a plasma stream and at least one electromagnetic radiation source and a wafer support to position a wafer for etching using the plasma stream and the wafer support having a plurality of apertures to allow passage of electromagnetic radiation from an electromagnetic radiation source through the wafer support to impinge on a surface of the wafer during etching.
    Type: Application
    Filed: September 14, 2006
    Publication date: March 20, 2008
    Inventor: Martin Kerber
  • Patent number: 7337745
    Abstract: A susceptor 24 includes a heater 38 disposed in a planar state, upper and lower ceramic-metal composites 40A and 40B disposed so as to sandwich the heater 38 from above and from below, and a ceramic electrostatic chuck 28 for attracting and holding an object to be treated, W. The electrostatic chuck is joined to an upper surface of the upper ceramic-metal composite 40A. The electrostatic chuck 28 has nearly the same coefficient of linear thermal expansion as that of the upper ceramic-metal composite 40A. Thus, peeling or cracking of the electrostatic chuck 28 due to the difference in thermal expansion and contraction between the electrostatic chuck 28 and the upper ceramic-metal composite 40A can be prevented.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: March 4, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuaki Komino, Hideaki Amano, Shosuke Endo, Toshiaki Fujisato, Yasuharu Sasaki
  • Publication number: 20080023139
    Abstract: The invention relates to a plasma processing apparatus and a plasma processing method and particularly relates to a plasma processing apparatus suitable for executing an etching processing of a work by using plasma.
    Type: Application
    Filed: August 30, 2006
    Publication date: January 31, 2008
    Inventors: Naoki Yasui, Hiroho Kitada
  • Publication number: 20080020574
    Abstract: A device for inductively confining capacitively coupled RF plasma formed in a plasma processing apparatus. The apparatus includes an upper electrode and a lower electrode that is adapted to support a substrate and to generate the plasma between the substrate and the upper electrode. The device includes a dielectric support ring that concentrically surrounds the upper electrode and a plurality of coil units mounted on the dielectric support ring. Each coil unit includes a ferromagnetic core positioned along a radial direction of the dielectric support ring and at least one coil wound around each ferromagnetic core. The coil units generate, upon receiving RF power from an RF power source, electric and magnetic fields that reduce the number of charged particles of the plasma diffusing away from the plasma.
    Type: Application
    Filed: July 18, 2006
    Publication date: January 24, 2008
    Applicant: Lam Research Corporation
    Inventors: Alexei Marakhtanov, Rajinder Dhindsa, Eric Hudson, Andreas Fischer
  • Publication number: 20080017318
    Abstract: In a semiconductor device manufacturing apparatus which is equipped with: a process chamber; a unit for supplying gas to said process chamber; a exhausting unit to reduce pressure in said process chamber; a high frequency power source for plasma generation; a coil for generating a magnetic field; and a mounted electrode for mounting a substance to be processed, particles were transported in the circumference direction of said substance to be processed by thermo-phoretic force, by changing the magnetic field distribution, so as to make a plasma distribution at the surface of said substance to be processed, in a convex form, in ignition of the plasma or after completion of a predetermined processing, compared with the plasma distribution during said predetermined processing to said substance to be processed, and thus to generate temperature gradient of processing gas just above said substance to be processed.
    Type: Application
    Filed: January 29, 2007
    Publication date: January 24, 2008
    Inventors: Hiroyuki Kobayashi, Kenji Maeda, Kenetsu Yokogawa, Masaru Izawa
  • Publication number: 20080017111
    Abstract: Wafer contamination is prevented, while preventing damage to a high-frequency electrode and a susceptor. A main body 41 of the susceptor 40 of an MMT apparatus is composed of a heater arranging plate 42, an electrode arranging plate 48, and a supporting plate 56 all made from quartz. A circular electrode arranging hole 49 with a fixed depth is concentrically formed on the upper surface of the electrode arranging plate 48, and quadrangular pillars 50 are formed protruding in a matrix on the bottom of the electrode arranging hole 49. Multiple insertion holes 52 are formed in a disk-shaped high-frequency electrode 51, and the high-frequency electrode 51 is installed in the electrode arranging hole 49 by inserting each pillar 50 into each insertion hole 52. The gaps Sa and Sb are provided between the high-frequency electrode 51 and the electrode arranging plate 48. The pillar 50 boosts the strength of the electrode arranging plate 48.
    Type: Application
    Filed: March 4, 2005
    Publication date: January 24, 2008
    Inventors: Mitsunori Ishisaka, Toshimitsu Miyata
  • Patent number: 7318879
    Abstract: An apparatus to manufacture a semiconductor includes a plasma-limiting device to limit a plasma region in a reaction chamber. The plasma-limiting device includes a first limiting device to limit the plasma region in the reaction chamber to a first plasma region, a second limiting device to limit the plasma region in the reaction chamber to a second plasma region having an area larger than an area of the first plasma region, and a driving device to simultaneously move the first and second limiting devices to vary the plasma region.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: January 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yong Kwon, Jung Wook Kim
  • Patent number: 7316761
    Abstract: Apparatus for plasma etching a layer of material upon a substrate comprising an anode having a first region protruding from a second region, wherein the second region defines a plane and the first region extends from said plane. In one embodiment, at least one solenoid is disposed near the apparatus to magnetize the plasma.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: January 8, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Kenny L. Doan, Yunsang Kim, Mahmoud Dahimene, Jingbao Liu, Bryan Pu, Hongqing Shan, Don Curry
  • Publication number: 20070284045
    Abstract: Techniques and apparatus for substantially reducing and/or preventing the occurrence of plasma un-confinement events, including one or more of shielding a gap disposed between chamber components and along a RF current path with a dielectric shielding structure, shielding a sharp component structure with a dielectric shielding structure, and keeping the gap between adjacent pairs of plasma confinement rings smaller than the worst-case DeBye length for the plasma.
    Type: Application
    Filed: September 29, 2006
    Publication date: December 13, 2007
    Inventors: Andreas Fischer, Rajinder Dhindsa
  • Patent number: 7306707
    Abstract: The present invention presents an adaptable processing element for use in a processing system having multiple configurations. The processing element comprises a primary component and at least one detachable component, wherein the at least one detachable component can be retained for one configuration and removed for another configuration. For example, the detachable component may include a punch-out or knock-out located on a right-hand side and a left-hand side of a processing element in order to permit access of a gas supply line to a processing chamber for either a right-hand orientation or a left-hand orientation, respectively. Additionally, for example, the detachable component, whether retained or removed, can permit flexible use with different size processing chambers.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: December 11, 2007
    Assignee: Tokyo Electron Limited
    Inventors: John Lawson, Rodger Eckerson, Michael Landis
  • Publication number: 20070281491
    Abstract: A method for forming features in a polysilicon layer is provided. A hardmask layer is formed over the polysilicon layer. A photoresist mask is formed over the hardmask layer. The hardmask layer is etched through the photoresist mask to form a patterned hardmask. The patterned hardmask is trimmed by providing a non-carbon containing trim gas comprising oxygen and a fluorine containing compound, forming a plasma from the trim gas, and trimming the hardmask. Features are etched into the polysilicon layer through the hardmask.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 6, 2007
    Inventor: Tom A. Kamp
  • Patent number: 7296534
    Abstract: The present invention uses hybrid ball-lock devices as an alternate for threaded fasteners. Parts of the fastener exposed directly to the plasma act as a shield for the remaining pieces of the fastener or are used as a material to actually enhance plasma characteristics. The present invention also provides consistent electrical and mechanical contact between parts, without the use of any tools.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: November 20, 2007
    Assignee: Tokyo Electron Limited
    Inventor: Steven T. Fink
  • Patent number: 7294283
    Abstract: The preferred embodiments described herein provide a Penning discharge plasma source. The magnetic and electric field arrangement, similar to a Penning discharge, effectively traps the electron Hall current in a region between two surfaces. When a substrate (10) is positioned proximal to at least one of the electrodes (11, 12) and is moved relative to the plasma, the substrate (10) is plasma treated, coated or otherwise modified depending upon the process gas used and the process pressure. This confinement arrangement produces dramatic results not resembling known prior art. Using this new source, many applications for PECVD, plasma etching, plasma treating, sputtering or other plasma processes will be substantial improved or made possible. In particular, applications using flexible webs (10) are benefited.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: November 13, 2007
    Assignee: Applied Process Technologies, Inc.
    Inventor: John Madocks
  • Patent number: 7288166
    Abstract: A plasma processing apparatus for manufacturing a semiconductor device includes an apparatus for applying bias powers to a substrate to be processed and a material adjacent to the substrate, an apparatus for adjusting a feeding impedance for the bias power applied to the material, and an apparatus for adjusting feeding impedances for the bias powers to a plurality of positions on the substrate so as to make electrons projected to the substrate from the plasma uniform within a surface of the substrate.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: October 30, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Ohmoto, Hironobu Kawahara, Ken Yoshioka, Kazue Takahashi, Saburou Kanai
  • Patent number: 7282111
    Abstract: Provided is a particle monitoring system capable of detecting a level of polymer particle contamination on inner walls of a process chamber. Also disclosed is a method of monitoring the level of polymer particle contamination on inner walls of a process chamber.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: October 16, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong-Jin Park
  • Patent number: 7281491
    Abstract: A dielectric-coated electrode having a conductive base material coated with a dielectric on a surface thereof, the dielectric including a first metal atom and a second metal atom. As for an ionic strength of the first metal atom and an ionic strength of the second metal atom according to a dynamic SIMS measurement, the ionic strength of the second metal atom is larger than the ionic strength of the first metal atom from the most surface of the dielectric toward a predetermined depth of the dielectric, and the ionic strength of the first metal atom is larger than the ionic strength of the second metal atom from the predetermined depth toward the surface of the conductive base material.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: October 16, 2007
    Assignee: Konica Corporation
    Inventor: Shunichi Iwamaru
  • Patent number: 7273533
    Abstract: An inductively coupled plasma source is provided with a peripheral ionization source for producing a high-density plasma in a vacuum chamber for semiconductor wafer coating or etching. The source includes a segmented configuration having high and low radiation segments and produces a generally ring-shaped array of energy concentrations in the plasma around the periphery of the chamber. Energy is coupled from a segmented low inductance antenna through a dielectric window or array of windows and through a segmented shield or baffle.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: September 25, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Jozef Brcka, Rodney Lee Robison
  • Publication number: 20070218698
    Abstract: A plasma etching method includes the step of performing a plasma etching on a SiCN layer, which is formed on a substrate to be processed having a SiOCH layer and the SiCN layer, by using a plasma of an etching gas. A gaseous mixture including CF4 and NF3 is employed as the etching gas, and the SiCN layer is selectively etched against the SiOCH layer. In the plasma etching method, a selectivity of the SiCN layer against the SiOCH layer (an etching rate of the SiCN layer/an etching rate of the SiOCH layer) is equal to or greater than about 1.1 and a flow rate ratio of the NF3 to the CF4 is equal to or greater than about 6%.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 20, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Ryoichi YOSHIDA
  • Patent number: 7270713
    Abstract: A gas distribution plate assembly and a method for distributing gas in a processing chamber are provided. In one embodiment, a gas distribution plate assembly includes a tuning plate coupled to a diffuser plate. The tuning plate has a plurality of orifice holes formed therethrough that align with a plurality of apertures formed through the diffuser plate, where the apertures each have a greater sectional area than the holes in the tuning plate. Each aperture is aligned with a respective hole to define gas passages through the gas distribution plate assembly. The tuning plate may be interchanged with a replacement tuning plate to change the gas flow characteristics through the gas distribution plate assembly.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: September 18, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Wendell T. Blonigan, John M. White, William A. Bagley
  • Patent number: 7255773
    Abstract: A plasma processing apparatus having an evacuation ring with high plasma resistance and capable of minimizing abnormal discharge is provided. A processing chamber 100 includes a ceiling unit 110 at which an upper electrode 112 is provided and a container unit 120 having a lower electrode 122 provided to face opposite the upper electrode 112, on which a substrate can be placed. An evacuation ring 126 is provided around the lower electrode 122 so as to divide the space in the processing chamber 100 into a plasma processing space 102 and an evacuation space 104. At the evacuation ring 126, through holes 126a and blind holes 126b which are fewer than the through holes 126a and open toward the plasma processing space 102 are formed. An insulation coating constituted of Y2O3 is applied onto the surface of the evacuation ring 126 towards the plasma processing space 102.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: August 14, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Masahiro Ogasawara, Kazuya Kato
  • Patent number: 7217337
    Abstract: The present invention relates to a plasma process chamber, which includes: an upper housing having a gas inlet connected to a gas source, and a gas shower head placed in the upper housing; and a lower housing having a gas outlet connected to a vacuum pump, and a substrate provided on the inner bottom of the lower housing. On the substrate is placed a wafer. A plasma reactor is provided between the upper housing and the lower housing of the plasma process chamber. The plasma reactor is provided on the outer circumference of its main body with at least one reactor tube of horseshoe shape. A closed magnetic core is attached to the reactor tube, and a coil is wound on said magnetic core. The coil is connected electrically to an A.C. power. The plasma reactor is placed in the middle area of the plasma process chamber and a plurality of the reactor tubes are provided on the outer circumference of the plasma reactor so that plasma reaction is generated and distributed evenly in the plasma process chamber.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: May 15, 2007
    Inventor: Dae-Kyu Choi
  • Patent number: 7204913
    Abstract: A semiconductor processing chamber having a silicon containing pre-coat is provided. The chamber includes a top electrode in communication with a power supply and a processing chamber defined within a base, a sidewall extending from the base, and a top disposed on the sidewall. The processing chamber has an outlet enabling removal of fluids within the processing chamber and includes a substrate support where an outer surface of the substrate support coated with the removable silicon containing coating, wherein the silicon containing coating is a compound consisting essentially of silicon and one of bromine and chlorine. The chamber includes an inner surface defined by the base, the sidewall and the top, where the inner surface is coated with a removable silicon containing coating.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: April 17, 2007
    Assignee: Lam Research Corporation
    Inventors: Harmeet Singh, Saurabh J. Ullal, Shibu Gangadharan
  • Patent number: 7182842
    Abstract: A device (1) for amplifying the current of an abnormal electrical discharge, characterized in that it comprises an electrode which is positively polarized (2) and associated with a magnetic circuit (3) producing a magnetic field (4) which is uniformly divergent, whereby the intensity on the surface of the electrode is more than approximately 6.102 Tesla, the electrode being positioned in the region where the magnetic field is at its most intense.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: February 27, 2007
    Assignee: Tecmachine
    Inventors: Christophe Heau, Jean-Paul Terrat
  • Patent number: 7176402
    Abstract: An electronic part processing method for peeling off a resin coating of an electronic part having a terminal section. The method includes a step of irradiating, with plasma, a coated wire having copper as a principal constituent and a surface coated with a resin.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomohiro Okumura, Kenichiro Suetsugu, Hiroshi Kawazoe, Mitsuo Saitoh, Akio Furusawa
  • Patent number: 7165506
    Abstract: In an ion etching method for reducing a substrate thickness, an electric arc is generated in a vacuum chamber such that the electric arc is locally separated from the substrate and circulates about the substrate. A plasma of a supplied etching gas is produced by the electric arc, and the ions of the etching gas are accelerated onto the substrate by an electric potential. The employed device has a vacuum chamber, an etching gas supply, and first and second electrodes supplied with direct or alternating voltage for generating the electric arc that produces the plasma of the etching gas. The first electrode is ring-shaped and the second electrode is arranged centrally to the ring of the first electrode. A magnetic coil creates a migrating magnetic field such that the electric arc is locally separated from the substrate and circulates about the substrate in a carousel fashion.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: January 23, 2007
    Assignee: Cobes GmbH Nachrichten- und Datentechnik
    Inventor: Johannes Stollenwerk
  • Patent number: 7153444
    Abstract: Provided is a method and apparatus for controlling a bias voltage over a wide range and for de-coupling dual radio frequency (RF) currents to allow for independent control of plasma density and ion energy of a plasma for processing a substrate. An exemplary apparatus provides a plasma processing chamber which includes a bottom electrode configured to hold a substrate and first and second RF power supplies being connected to the bottom electrode. Also included is a top electrode which is electrically isolated from a top ground extension. A filter array defining a set of filter settings is included. A switch is coupled to the top electrode and the switch is configured to interconnect the top electrode to one of the filter settings. The filter settings are configured to enable or disable RF current generated from one or both of the RF power supplies from passing through the top electrode.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: December 26, 2006
    Assignee: Lam Research Corporation
    Inventor: Andreas Fischer
  • Patent number: 7147749
    Abstract: The present invention presents an improved upper electrode for a plasma processing system, wherein the design and fabrication of an electrode plate with a deposition shield coupled to the upper electrode advantageously provides gas injection of a process gas with substantially minimal erosion of the upper electrode while providing protection to a chamber interior.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: December 12, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Shinya Nishimoto, Kouji Mitsuhashi, Hiroyuki Nakayama
  • Patent number: 7138034
    Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: November 21, 2006
    Assignees: Matsushita Electric Industrial Co., Ltd., Krosaki Harima Corporation
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi, Taiji Matano, Nobuhiro Satou
  • Patent number: 7104217
    Abstract: The present invention provides a plasma processing apparatus having an electrode plate arranging therein, an upper electrode to which a dielectric member or a cavity portion is provided, a dimension or a dielectric constant of which is determined in such a manner that resonance is generated at a frequency of high-frequency power supplied to the center of the back side and an electric field orthogonal to the electrode plate is generated, and a susceptor as a lower electrode so as to be opposed to each other, in order to reduce unevenness of an electric field distribution on the surface of the electrode in a plasma processing using a high-density plasma capable of coping with further refinement.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: September 12, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Shinji Himori, Toshiki Takahashi, Takumi Komatsu
  • Patent number: 7102872
    Abstract: An ESC (Electrostatic Chuck) to chuck an object by electrostatic force, having an ESC main body supporting the object; a guide ring supported by the ESC main body and encircling the object; a dielectric material layer interposed between the guide ring and the ESC main body; a media gas supplier to supply a media gas to the guide ring; and a power supplier to supply power to the ESC main body. With this configuration, the ESC provides an apparatus to chuck a guide ring to an ESC main body, while maintaining the guide ring and an object, such as a wafer, at the same or similar temperature, thereby enhancing uniformity of the object during a semiconductor manufacturing process such as etching, deposition, or the like.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: September 5, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yong Cho, Byeong-sun An, Jin-man Kim, Kyung-sun Kim