Abstract: A method of fabricating a multilayer electronic support structure comprising electroplating copper substructures, laying a dielectric pre-preg comprising a polymer resin over the copper substructures, and pressing to pressures of 200 to 600 PSI against a release film having a higher hardness than the resin of the prepreg but a lower hardness than the cured resin, and heating through a curing cycle whilst maintaining pressure.

Abstract: Disclosed herein is a multi-layer type printed circuit board, including; a first insulating layer including at least one first pillar; a plurality of insulating layers laminated in a both surfaces direction of the first insulating layer, each including at least one circuit layer and at least another pillar connected to the circuit layer; and a plurality of outermost circuit layers disposed on an outer surface of the outermost insulating layer, while contacting an outermost pillar disposed on an outermost insulating layer among the plurality of insulating layers, wherein the circuit layer and another pillar each formed in a both surfaces direction of the first insulating layer are disposed in a symmetrical form to each other based on the first insulating layer.

Abstract: Disclosed herein is a multi-layer type coreless substrate, including: a first insulating layer including at least one first pillar; a plurality of insulating layers laminated on one surface or both surfaces of the first insulating layer, each including at least one circuit layer and at least another pillar connected to the circuit layer; and a plurality of outermost circuit layers contacting a pillar disposed on an outermost insulating layer of the plurality of insulating layers.

Abstract: A hermetic interconnect for medical devices is disclosed. In one embodiment, the interconnect includes platinum leads co-fired between alumina substrates to form a monolithic composite that is subsequently bonded into a titanium alloy flange. Both methodology for forming these interconnects as well as specific geometries and compositions are disclosed. Interconnects formed in this fashion enable significant reductions in overall size of the interconnect relative to the number of feedthrough leads as well as substantial improvements in robustness versus currently available technology.

Abstract: One aspect of the present invention resides in a method of producing a circuit board, including a film-forming step of forming a resin film on a surface of an insulative substrate; a circuit pattern-forming step of forming a circuit pattern portion by forming a recessed portion having a depth equal to or greater than a thickness of the resin film, with an outer surface of the resin film serving as a reference; a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on a surface of the circuit pattern portion and a surface of the resin film; a film-separating step of removing the resin film from the insulative substrate; and a plating step of forming an electroless plating film only in a region where the plating catalyst or the precursor thereof remains after the resin film is separated.

Abstract: A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Abstract: This present invention pertains to: a conductive laminate body, a touch panel, and a display device. In the present invention, the relative refractive index of a substrate with respect to a first protective sheet, and/or the relative refractive index of the substrate with respect to a second protective sheet is 0.86-1.15. The relative refractive index of a first substrate with respect to the first protective sheet, and/or the relative refractive index of a second substrate with respect to the second protective sheet is 0.86-1.15.

Abstract: A three-dimensional structure in which a wiring and a pad part are provided on a surface is provided. A recessed gutter for wiring and a hole for the pad part having a depth that is greater than a thickness of the recessed gutter for wiring are provided on the surface of the three-dimensional structure. The hole for the pad part is provided in succession with the recessed gutter for wiring. At least a part of a wiring conductor is embedded in the recessed gutter for wiring and in the hole for the pad part.

Abstract: A printed wiring board includes multiple insulating layers laminated on each other and each including resin and core, the insulating layers having first-surface sides and second-surface sides on the opposite side, respectively, and including multiple first insulating and second insulating layers, multiple first-surface-side conductive layers formed on the first-surface sides of the first insulating layers, respectively, multiple second-surface-side conductive layers formed on the second-surface sides of the second insulating layers, respectively.

Abstract: A printed circuit board includes a first trace layer, a first dielectric layer, a second trace layer, a second dielectric layer, a third trace layer, a third dielectric layer and a fourth trace layer arranged in that order. A cavity is defined in the printed circuit board running through from the fourth trace layer to the second dielectric layer. Portion of the second dielectric layer is exposed in the cavity. Surfaces of the fourth trace layer combining with the second dielectric layer, and surfaces of the second trace layer combining with the first dielectric layer, are all roughened to increase the strength of adhesion.

Abstract: A printed wiring board includes an outermost interlayer resin insulation layer, n outermost conductive layer formed on the outermost interlayer resin insulation layer and including multiple alignment marks, a connection wiring structure connecting the alignment marks, and a solder-resist layer formed on the outermost interlayer resin insulation layer and the outermost conductive layer. The solder-resist layer has openings exposing the alignment marks, respectively, and each of the alignment marks has an electroless plated film formed on each of the alignment marks.

Abstract: There is provided a wiring substrate. The wiring substrate includes: a first wiring layer; a first insulating layer on the first wiring layer; a first coupling agent layer on the first insulating layer; a first copper/tin alloy layer on the first coupling agent layer; a first via hole formed through the first copper/tin alloy layer, the first coupling agent layer, and the first insulating layer to reach the first wiring layer; a metal catalyst provided on only a sidewall of the first via hole; a seed layer provided on the metal catalyst and formed only on the sidewall of the first via hole; and a metal plating layer formed on the first copper/tin alloy layer and the seed layer and filled in the first via hole to contact the first wiring layer.

Abstract: A chip packaging substrate includes a dielectric layer, a first inner wiring layer embedded in the dielectric layer, an outer wiring layer, and many conductive connection points. The outer wiring layer is formed at one side of the dielectric layer, and is electrically connected to the first inner wiring layer through many first conductive vias in the dielectric layer. The conductive connection points are formed at the other side of the dielectric layer, and are electrically connected to the first inner wiring layer through many second conductive vias in the dielectric layer.

Abstract: A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements.

Abstract: A wiring substrate includes a first insulating layer, an adhesion insulating layer formed under the first insulating layer and an outer face of the adhesion insulating layer is made to a roughened face, a first wiring layer formed on the first insulating layer, a second insulating layer formed on the first insulating layer, and in which a first via hole reaching the first wiring layer is provided, a second wiring layer formed on the second insulating layer, and connected to the first wiring layer through the first via hole, a second via hole formed in the adhesion insulating layer and the first insulating layer, and reaching the first wiring layer, and a third wiring layer formed on the outer face of the adhesion insulating layer, and connected to the first wiring layer through the second via hole.

Abstract: A device-embedded flexible printed circuit board (FPCB) and a method of manufacturing the device-embedded FPCB are provided. The device-embedded FPCB includes: a first conductive layer; a first insulating layer which is disposed on the first conductive layer and includes at least one bump hole and at least one groove; a first plating layer which is formed in the at least one groove of the first insulating layer; and a device which includes at least one bump which is inserted into the at least one bump hole to be connected to the first conductive layer.

Abstract: A circuit board includes a circuit pattern formed on a substrate, a first solder resist layer formed on the circuit pattern, an electroless plating layer formed on the circuit pattern on which the first solder resist layer is opened, and a second solder resist layer formed on the first solder resist layer, and a method for manufacturing the same. According to certain embodiments, it is possible to cover a portion which has vulnerable plating quality due to solder resist residue or insufficient wetting around an edge of an existing solder resist layer by including an additional solder resist layer on a surface-treated plating layer. Further, it is possible to protect an undercut portion under the solder resist layer by forming the additional solder resist layer.

Abstract: The present invention deals with a novel multi-layer article useful for preparing flexible printed wiring boards, the multi-layer article comprising discrete conductive pathways contacting a novel curable composition comprising bis-benzoxazine and an amino-functionalized triazine, especially a di-isoimide, and the preparation of encapsulated printed wiring boards, especially flexible printed wiring boards, therefrom. The multi-layer article hereof allows the benefits of bis-benzoxazine as a crosslinkable encapsulant for flexible printed wiring boards to be realized at cure temperatures compatible with existing commercial processes.

Abstract: In this conductive sheet and touch panel, a first conductive pattern has a band-shaped section extending in the y-direction; a second conductive pattern has a plurality of electrode sections that are each connected in the x-direction by a connection section; the first conductive pattern and the second conductive pattern are both configured combining a first lattice and a second lattice (having a size larger than that of the first lattice); the facing portions of each of the band-shaped section of the first conductive pattern and the connection section of the second conductive pattern are configured from a plurality of second lattices; and when seen from the upper surface, the facing portions of the band-shaped section and the connection section have a form combining a plurality of first lattices.

Abstract: A flexible wiring board includes an electric insulating base material including an incompressible member having bendability and a thermosetting member having bendability; a first wiring and a second wiring formed with the electric insulating base material interposed therebetween; and a via-hole conductor penetrating the electric insulating base material, and electrically connecting the first wiring and the second wiring to each other. The via-hole conductor includes a resin portion and a metal portion. The metal portion includes a first metal region mainly composed of Cu; a second metal region mainly composed of a Sn—Cu alloy; and a third metal region mainly composed of Bi. The second metal region is larger than the first metal region, and larger than the third metal region.

Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer. The via includes a first part, a second part below the first part, and a third part between the first and second parts, and the third part includes a metal different from a metal of the first and second parts. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

Abstract: A wired circuit board includes a first insulating layer, a first wire formed on the first insulating layer, a second insulating layer formed on the first insulating layer so as to cover the first wire, and a second wire placed opposite to the first wire in a thickness direction and formed in a smaller width than that of the first wire.

Abstract: A printed wiring board includes a core substrate including resin and inorganic fiber, a first buildup layer formed on a first surface of the substrate and including resin insulating layers and first conductive layers, and a second buildup layer formed on a second surface of the substrate on the opposite side of the core substrate with respect to the first surface and including resin insulating layers and second conductive layers. The first conductive layers in the first buildup have sum V1 of volumes which is greater than sum V2 of volumes of the second conductive layers in the second buildup, and the substrate has a first-surface side portion which has resin amount greater than resin amount of a second-surface side portion of the substrate where boundary between the first-surface and second-surface side portions is set with respect to the center line in the thickness direction of the substrate.

Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the core insulating layer, and the first width is larger than the second width. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

Abstract: A signal line is a linear conductor provided within a laminated body. A first ground conductor is provided on a positive direction side in a z axis direction within the laminated body, compared with the signal line, and overlaps with the signal line in a planar view seen from the z axis direction. A second ground conductor is provided on a negative direction side in the z axis direction within the laminated body, compared with the signal line, and overlaps with the signal line in the planar view seen from the z axis direction. Via hole conductors connect the ground conductors to each other. In the first ground conductor, a plurality of opening portions are arranged along the signal line in the planar view seen from the z axis direction. The via hole conductors are provided between the opening portions adjacent to one another, in an x axis direction.

Abstract: A wired circuit board includes a first insulating layer, a conductive pattern formed on its surface at one side in a thickness direction, and a second insulating layer formed on the surface of the first insulating layer at the one side in the thickness direction so as to cover the conductive pattern. An outer end surface of the first insulating layer in a perpendicular direction to the thickness direction is formed to be inclined outwardly gradually from the one side toward the other side in the thickness direction. An outer end surface of the second insulating layer in the perpendicular direction has an end edge at the other side in the thickness direction which is located between both end edges of the outer end surface of the first insulating layer in the perpendicular direction which are located at the one side and the other side in the thickness direction.

Abstract: A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.

Abstract: A compliable unit in an compliable network comprises a first layer including at least one device component at a first region of the first layer, and a second layer including at least one compliable element at a first region of the second layer to transfer the at least one device component to a desired location. The first layer and the second layer are arranged in a stack.

Abstract: Provided are surfaces comprising particles, which particles may possess, for example, antimicrobial or biosensing properties. Also provided are related methods for fabrication of the inventive articles. Also provided are systems and methods for treating fluids, objects, and targets with the inventive surfaces.

Abstract: Disclosed herein is a printed circuit board, including: a base substrate on which a circuit layer is formed; and multi-layer insulating layers formed in a plurality of layers on the base substrate, including the circuit layer, each of the plurality of layers being formed to have a step structure, wherein the multi-layer insulating layer is formed of heterogeneous materials.

Abstract: A method of fabricating a two-layer capacitive touch sensor panel comprising the following steps: a) depositing a first transparent electrically conductive layer on a transparent cover sheet; b) forming a pattern in the transparent electrically conductive layer to create a first set of discrete electrode structures; c) depositing a transparent dielectric layer over the discrete electrode structures; d) depositing a second transparent electrically conductive layer onto the transparent dielectric layer; e) forming a pattern in the transparent electrically conductive layer to create further discrete electrode structures by laser ablation, this pattern either not penetrating or penetrating only part way through the dielectric layer so as to avoid damaging the first set of discrete electrode structures; f) forming electrical connections or vias between the two transparent electrically conductive layers through the dielectric layer; and g) forming electrical connections between the transparent electrically conducti

Abstract: A printed circuit board structure includes a plurality of circuit layer plates stacked together in which each of the stacked circuit layer plates includes an epoxy resin plate body and a fabric structure completely encapsulated in the epoxy resin plate body, and each circuit layer plate stacked between two circuit layer plates is further provided with filler particles distributed in its epoxy resin plate body, and the two opposite and outermost circuit layer plates thereof have metal soldering pads on the outer surfaces of the epoxy resin plate body thereof, and the two opposite and outermost circuit layer plates do not have the filler particles in its epoxy resin plate body thereof.

Abstract: Disclosed is a structure for precision control of electrical impedance of signal transmission circuit board. A substrate forms thereon a plurality of first signal transmission lines, and a first covering insulation layer is formed on a first surface of the substrate to cover a surface of each first signal transmission lines and each spacing section formed between adjacent first signal transmission lines. Each first signal transmission lines can transmit a differential mode signal or a common mode signal.

Abstract: A wiring substrate includes differential wirings; a first insulating layer adjacent to one side of the differential wirings, including first fiber bundles parallel to the differential wirings; a second insulating layer adjacent to another side of the differential wirings, including second fiber bundles parallel to the differential wirings and disposed by the same pitch as the first fiber bundles; a third insulating layer on the first insulating layer on a side opposite to the differential wirings, including third fiber bundles in parallel to the differential wirings; and a fourth insulating layer on the second insulating layer on a side opposite to the differential wirings, including fourth fiber bundles in parallel to the differential wirings. Intervals of the third and fourth fiber bundles are respectively narrower than intervals of the first and second fiber bundles. The differential wirings are disposed between adjacent first fiber bundles, and between adjacent second fiber bundles.

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Abstract: A printed circuit board disclosed. One embodiment of the present invention provides a printed circuit board that includes: an insulation layer having multiple layers of circuit wirings formed therein; a via formed along a perimeter of the insulation layer and configured for connecting circuit wirings formed on different layers of the insulation layer, the via being formed in such a way that an inside thereof is hollow; and an electromagnetic wave absorbing part contained in the via.

Abstract: Disclosed herein are an electrode pattern and a method of manufacturing the same, and a printed circuit board applied with the electrode pattern and a method of manufacturing the same. In order to increase a heat dissipation effect, disclosed herein are an electrode pattern including electrode layers with a predetermined pattern; and insulators insulating the electrode layers from each other, in which the insulators are made of metal oxide, a method of manufacturing the same, and a printed circuit board applied with the electrode pattern and a method of manufacturing the same.

Abstract: A circuit board including a circuit substrate, a dielectric layer, a first conductive layer and a second conductive layer is provided. The circuit substrate has a first surface and a first circuit layer. The dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The dielectric layer has a second surface, at least a blind via extended from the second surface to the first circuit layer and an intaglio pattern. The first conductive layer is disposed inside the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer through the first conductive layer.

Abstract: Disclosed herein is a printed circuit board including a base substrate, a photosensitive insulating layer formed on an upper portion of the base substrate, and a circuit pattern formed to be buried within the photosensitive insulating film.

Abstract: A ceramic multilayer substrate includes stacked ceramic layers; internal conductors which are stacked with one of the ceramic layers therebetween, and are arranged such that at least a portion of the internal conductors overlap each other in a stacking direction; and a constraining layer which is arranged on a layer different from layers on which the internal conductors are located. The constraining layer overlaps, in the stacking direction, an internal conductor-overlapping region where at least two of the internal conductors overlapping each other in the stacking direction, has a planar area not more than twice the planar area of the internal conductor-overlapping region, and contains an unsintered inorganic material powder. The constraining layer has a planar area not more than one-half the planar area of the ceramic layers. The constraining layer is arranged so as to entirely cover the internal conductor-overlapping region.

Abstract: A conductive member containing: a base material; a conductive layer provided on the base material, wherein the conductive layer includes a metallic nanowire having an average short axis length of 150 nm or less and a matrix; and a protective layer including a three-dimensional crosslinked structure represented by the following Formula (I), sequentially in this order, and which has a surface resistivity measured at a surface of the protective layer of 1,000 ?/? or less, a production method of the conductive member, and a touch panel and a solar cell, each of which uses the conductive member. The conductive member may provide high resistance against scratches and abrasion, excellent conductivity, excellent transparency, excellent heat resistance, excellent moisture and heat resistance, and excellent bendability. -M1-O-M1-??Formula (I): In the Formula (I), M1 represents an element selected from the group consisting of Si, Ti Zr and Al.

Abstract: A conductor layer is formed on one surface of a base insulating layer. The conductor layer is composed of a pair of rectangular collector portions and drawn-out conductor portions extending in long-sized shapes from the collector portions, respectively. Cover layers are formed on the base insulating layer to cover respective given portions of the conductor layer. A paste composition containing a compound represented by the formula (1) is used as a material for the cover layer.

Abstract: Disclosed herein is a method of manufacturing a multilayer type coreless substrate, the method including: (A) preparing a carrier substrate including at least one copper foil formed on one surface or both surfaces of an insulating surface; (B) forming a coreless printed circuit precursor on one surface or both surfaces of the carrier substrate; (C) separating the carrier substrate; (D) performing a polishing cutting process on the coreless printed circuit precursor; and (E) laminating a plurality of other insulating layers on a flat outer surface of the coreless printed circuit precursor, the plurality of other insulating layers sequentially including other circuit layers and other pillars.

Abstract: A printed circuit board (PCB) includes a first dielectric layer and a differential cable structure embedded in the dielectric layer. The differential cable structure includes a first inner conductor, a second inner conductor, a dielectric surrounding portions of the first inner conductor and portions of the second inner conductor, and a ground shield surrounding the dielectric.

Abstract: The present invention relates to a conducting substrate and a touch screen comprising the same, and the conducting substrate according to the present invention comprises a board, an electric conducting pattern provided on at least one surface of the board, and a darkening layer provided on at least one surface of the electric conducting pattern and in a region corresponding to the electric conducting pattern, wherein a reflective diffraction intensity of a reflective diffraction image obtained by radiating light emitted from a point light source on one surface from which the darkening layer is visible is reduced by 60% or more as compared to the conducting substrate having the same constitution except that the electric conducting pattern is formed of Al and does not comprise the darkening layer.

Abstract: The purpose of the present invention is to provide a printed circuit board wherein a resin layer exhibits excellent adhesion and a method for manufacturing said printed circuit board. This printed circuit board is provided with an insulating substrate, metal wiring laid out on said insulating substrate, and an insulating layer disposed on top of said metal wiring. A layer consisting of a thiol compound having at least four functional groups represented by formula (1) is interposed between the metal wiring and the insulating layer at the interface therebetween.

Abstract: A wiring substrate includes an insulating layer including a reinforcement member and having a first surface and a second surface positioned on an opposite side of the first surface, an electrode pad exposed from the first surface, a layered body including first insulating layers and being formed on the second surface, the first insulating layers having a first insulating material as a main component, another layered body including second insulating layers and being formed on the layered body, the second insulating layers having a second insulating material as a main component, and another electrode pad exposed from a surface of the another layered body that is opposite to the layered body. The number of the first insulating layers is equal to that of the second insulating layers. The first insulating layers have a thermal expansion coefficient that is greater than that of the second insulating layers.

Abstract: A circuit board includes an insulating layer with a surface on which a semiconductor element is to be mounted and wiring portions that are located on the insulating layer. The wiring portions includes upper wiring portions, lower wiring portions, and interlayer wiring portions. The upper wiring portions, the lower wiring portions, and the interlayer wiring portions are integrally defined by a single copper sheet. With this configuration, a circuit board capable of withstanding a large current and a method of manufacturing the circuit board are provided.

Abstract: Intersection structures are provided to reduce a strain in a conformable electronic system that includes multi-level arrangements of stretchable interconnect structures. Bypass regions are formed in areas of the stretchable interconnect structures that may ordinarily cross or pass each other. The bypass regions of the stretchable interconnects are disposed relative to each other such that the intersection structure encompasses at least a portion of the bypass regions of each stretchable interconnect structure. The intersection structure has elastic properties that relieve a mechanical strain on the bypass regions during stretching at least one of the stretchable interconnect structures.

Abstract: A resistance-formed substrate includes a first insulating layer, a first wiring formed on a first surface of the first insulating layer, a thin-film resistance layer formed on a second surface of the first insulating layer, and a first via-hole conductor. The first via-hole conductor penetrates through the first insulating layer, and is electrically connected to the first wiring and the thin-film resistance layer. The first via-hole conductor includes a metal part including a low-melting point metal and a high-melting point metal, and a paste resin part. The low-melting point metal includes tin and bismuth, and has a melting point of 300° C. or lower. The high-melting point metal includes at least one of copper and silver, and has a melting point of 900° C. or higher. The first via-hole conductor is in contact with the thin-film resistance layer at both the paste resin part and the metal part.