Insulating Patents (Class 174/258)
  • Patent number: 11367627
    Abstract: The present invention relates to a method for manufacturing a semiconductor device in which a circuit element including a semiconductor chip, and a through conductor connecting an insulation layer in a thickness direction are embedded in the insulation layer. A wiring structure in which a predetermined pattern of wiring conductors is formed along a planar direction on an insulation part is created, and thereafter the wiring structure is sealed in the insulation layer in a state where the wiring structure is erected vertically. Consequently, the wiring conductor of the wiring conductor is caused to function as the through conductor in the insulation layer.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 21, 2022
    Assignee: NAGASE & CO., LTD.
    Inventors: Tadashi Takano, Michihiro Sato
  • Patent number: 11359047
    Abstract: Compositions and methods for forming epoxy resin systems are provided. In one embodiment, a composition is provided for an epoxy resin system including an epoxy resin blend comprising an epoxy resin, a first curing agent selected from the group of a polyarylene alkylphosphonate, a polyarylene arylphosphonate, and combinations thereof, and a second curing agent.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 14, 2022
    Assignee: HEXION INC.
    Inventors: Amitabh Bansal, Larry Steven Corley, Diana Sepulveda-Camarena, Jennifer W. Chung, Leeanne Taylor, Alla Hale
  • Patent number: 11327587
    Abstract: In various embodiments, bilayers are formed in electronic devices at least in part by anodization of metal-alloy base layers.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 10, 2022
    Assignee: H.C. STARCK INC.
    Inventors: Helia Jalili, Francois Dary, Barbara Cox
  • Patent number: 11312858
    Abstract: Provided is a resin composition containing: a modified polyphenylene ether compound terminally modified with a substituent having an unsaturated carbon-carbon double bond; a cross-linking curing agent having an unsaturated carbon-carbon double bond in its molecule; a silane coupling agent having a phenylamino group in its molecule; and silica. A content of the silica is 60 to 250 parts by mass with respect to a total of 100 parts by mass of the modified polyphenylene ether compound and the cross-linking curing agent.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: April 26, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tatsuya Arisawa, Fumito Suzuki, Shunji Araki, Hirohisa Goto, Yuki Inoue
  • Patent number: 11310922
    Abstract: A board-to-board connecting structure which adds no significant thickness to a single printed circuit board includes a first circuit board and a second circuit board. The first circuit board includes first circuit substrate, adhesive layer, and second circuit substrate. The first circuit substrate includes first base layer, first inner wiring layer with first pad, and first outer wiring layer defining a receiving space. The second circuit substrate includes insulating layer and two second outer wiring layers. A conductive via in the second circuit substrate connects the two second outer wiring layers. The second circuit board includes second base layer and also two third outer wiring layers each with a second pad. The second circuit board is laterally disposed in the receiving space and one second pad connects to the conductive via and the other to the first pad.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 19, 2022
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD
    Inventors: Rui-Wu Liu, Man-Zhi Peng
  • Patent number: 11264332
    Abstract: Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Owen Fay, Chan H. Yoo
  • Patent number: 11264967
    Abstract: A multi-piece wiring substrate includes a matrix substrate including first and second insulating layers, and interconnection substrate regions arranged in a matrix. The matrix substrate includes dividing grooves opposing each other and disposed along boundaries between the interconnection substrate regions, and through-holes penetrating the matrix substrate in a thickness direction at positions where the dividing grooves are disposed. The inner surface conductor gradually decreases in thickness from a thick portion in a middle of the inner surface conductor, to thin portions disposed on a side of a boundary between the first and second insulating layers and on a first main surface side, and includes inclination portions each of which gradually increases in thickness from a boundary between corresponding one of the dividing grooves and the inner surface conductor to an inner surface of the inner surface conductor, in vertical sectional view.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 1, 2022
    Assignee: KYOCERA CORPORATION
    Inventor: Yoshitomo Onitsuka
  • Patent number: 11227824
    Abstract: A chip carrier and a manufacturing method thereof are provided. The chip carrier includes a first structure layer and a second structure layer. The first structure layer has at least one opening and includes at least one first insulating layer. A thermal expansion coefficient of the first insulating layer is between 2 ppm/° C. and 5 ppm/° C. The second structure layer is disposed on the first structure layer and defines at least one cavity with the first structure layer. The second structure layer includes at least one second insulating layer, and a thermal expansion coefficient of the second insulating layer is equal to or greater than the thermal expansion coefficient of the first insulating layer.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 18, 2022
    Inventor: Chung W. Ho
  • Patent number: 11217394
    Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes and external electrodes disposed on external surfaces of the body and electrically connected to the internal electrodes, wherein in the body, corners of cover portions include curved surfaces, and 10 ?m?R?T/4 in which R is a radius of curvature of the curved surface corners and T is a thickness of the body, and when a distance from a surface of the body to an internal electrode closest to the surface of the body among the plurality of internal electrodes is a margin, a margin (?) of each of the corners formed as the curved surfaces in the cover portions is greater than or equal to a margin (Wg) of the body in a width direction.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byeong Gyu Park, So Ra Kang, Yong Jin Yun, Jea Yeol Choi, Jung Min Park
  • Patent number: 11195790
    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Akihisa Kuroyanagi, Jun Woo Myung, Eun Sil Kim, Yeong A Kim
  • Patent number: 11177294
    Abstract: An array substrate, a manufacturing method thereof and a display device are provided. A display unit is disposed on a first surface of a base substrate, and a driving circuit is disposed on a second surface of the base substrate opposite to the first surface, the driving circuit is electrically connected with the display unit through a signal connection structure in at least one via structure, a longitudinal section of the at least one via hole is a trapezoid, and a length of a bottom edge of the trapezoid at one side of the trapezoid close to the display unit is larger than a length of a bottom edge of the trapezoid at one side of the trapezoid away from the display unit.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dongni Liu, Minghua Xuan, Li Xiao, Detao Zhao, Liang Chen, Hao Chen
  • Patent number: 11172567
    Abstract: An assembly method and device for a circuit structural member, and a circuit structural member. The assembly method comprises: measuring a depth and path of a channel between at least one chip and a printed circuit board (PCB), the at least one chip being arranged on the PCB; determining a thickness and path of a heat dissipation reinforcement material according to the depth and path of the channel between the at least one chip and the PCB and a predetermined heat dissipation parameter, so as to configure a dispensing parameter and a dispensing path; coating the heat dissipation reinforcement material in the channel between the at least one chip and the PCB according to the dispensing parameter and dispensing path; and heating the heat dissipation reinforcement material to a first predetermined temperature, such that the heat dissipation reinforcement material permeates into the chip and the PCB.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: November 9, 2021
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventor: Zhulin Huang
  • Patent number: 11152291
    Abstract: A multilayer substrate includes a plurality of plates laminated in a thickness direction of the multilayer substrate, a resin layer provided between the plurality of plates adjacent in the thickness direction, an internal conductive layer provided between the plurality of plates adjacent in the thickness direction, and an external conductive layer provided over an outer surface of each plate of the plurality of plates located at both ends in the thickness direction, wherein a total thickness of the internal conductive layer and the external conductive layer is equal to or less than 25% of a total thickness of the plurality of plates.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 19, 2021
    Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Toshiki Iwai, Taiji Sakai
  • Patent number: 11135825
    Abstract: According to the present invention, a surface of a prepreg (104), said surface being provided with a partially fused structure (102A), and a surface of a metal member (110) are brought into contact with each other, and heat and pressure are subsequently applied thereto. After completely melting a resin containing a thermoplastic resin and adhering to the prepreg (104) so that a reinforcing fiber substrate (101) is impregnated with the molten resin, the resin is cured to obtain a matrix resin (105), thereby forming a CFRP layer (120) that serves as a fiber-reinforced resin material, and the CFRP layer is simultaneously compression-bonded to the metal member (110), so that a metal-CFRP composite body (100) in which the CFRP layer (120) and the metal member (110) are firmly bonded to each other is formed.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: October 5, 2021
    Assignee: NIPPON STEEL Chemical & Material Co., Ltd.
    Inventors: Hiroyuki Takahashi, Hideki Andoh
  • Patent number: 11134568
    Abstract: Provided is a high-frequency circuit laminate that can reduce the transmission loss of electrical signals in high-frequency circuits and produce circuit boards with excellent smoothness. The high-frequency circuit laminate according to the present invention includes a metal layer and a resin layer which are laminated in contact with each other, the resin layer having an elastic modulus from 0.1 to 3 GPa, and the resin layer having an dielectric loss tangent from 0.001 to 0.01 and a relative permittivity from 2 to 3 at a frequency of 10 GHz at 23° C.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 28, 2021
    Assignee: JSR CORPORATION
    Inventors: Isao Nishimura, Nobuyuki Miyaki, Toshiaki Kadota, Shintarou Fujitomi, Tomotaka Shinoda
  • Patent number: 11121020
    Abstract: A method for manufacturing a printed wiring board which includes: Step (A) of laminating an adhesive sheet including a support and a resin composition layer bonded to the support to an inner layer board so that the resin composition layer is bonded to the inner layer board; Step (B) of thermally curing the resin composition layer to form an insulating layer; and Step (C) of removing the support, in this order, in which the support satisfies a condition (MD1): a maximum expansion coefficient EMD in an MD direction at 120° C. or more is less than 0.2% and a condition (TD1): a maximum expansion coefficient ETD in a TD direction at 120° C. or more is less than 0.2% below, when being heated under predetermined heating conditions, does not lower the yield even when the insulating layer is formed by thermally curing the resin composition layer with a support attached to the resin composition layer.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: September 14, 2021
    Assignee: Ajinomoto Co., Inc.
    Inventors: Masanori Ohkoshi, Hirohisa Narahashi, Eiichi Hayashi
  • Patent number: 11099669
    Abstract: A conductive structure is provided. The conductive structure includes a template including a skeleton and a pore therein and having flexibility, and a conductive material aggregated and formed on the skeleton and in the pore.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: August 24, 2021
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Wanjun Park, Sungwoo Chun
  • Patent number: 11071213
    Abstract: In one or more embodiments, a method of manufacturing a high impedance surface (HIS) apparatus comprises patterning a first conducting layer on a core to form a first set of conducting pads, and patterning a second conducting layer on the core to form a second set of conducting pads. The method further comprises applying solder paste to each of the conducting pads of the second set of conducting pads. Also, the method comprises placing chip capacitors on the solder paste on the second set of conducting pads. In addition, the method comprises applying underfill between the chip capacitors. Also, the method comprises applying solder paste to each of the conducting pads of the first set of conducting pads. In addition, the method comprises placing chip inductors on the solder paste on the first set of conducting pads. Further, the method comprises applying underfill between the chip inductors.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: July 20, 2021
    Assignee: The Boeing Company
    Inventors: Charles Muwonge, Kyu-Pyung Hwang, Terry Vogler, Young Kyu Song
  • Patent number: 11053593
    Abstract: Disclosed is a copper alloy article including: a substrate 10 made of a copper alloy; a polyester-based resin body 40; and a compound layer 20 for bonding the substrate 10 and the polyester-based resin body 40, wherein the compound layer 20 contains; a compound having a nitrogen-containing functional group and a silanol group, and an alkane type amine-based silane coupling agent.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 6, 2021
    Assignee: ADVANCED TECHNOLOGIES, INC.
    Inventors: Kinji Hirai, Isamu Akiyama, Tsukasa Takahashi, Takutaka Sugaya, Yuka Muto
  • Patent number: 11049661
    Abstract: A multilayer electronic component includes a body including a dielectric layer and first and second internal electrodes, and including first to sixth surfaces, a first external electrode including a first electrode layer extending to a portion of each of the first, second, fifth, and sixth surfaces and a first conductive resin layer, and a second external electrode including a second electrode layer extending to a portion of each of the first, second, fifth, and sixth surfaces and a second conductive resin layer. R1 and R2 satisfy R1>R2, in which R1 is defined as a surface roughness of each of the first, second, fifth, and sixth surfaces in contact with the first and second electrode layers, and R2 is defined as a surface roughness of each of the first, second, fifth, and sixth surfaces in contact with the first and second conductive resin layers.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Je Jung Kim, Seung Ryeol Lee, Su Kyoung Cha
  • Patent number: 11049795
    Abstract: A power electronic module (1) including at least one semiconductor (5) that is connected to connection conductors (6, 7), and including a dielectric carrier (10) having both a fixed layer (9), on which at least one of said connection conductors (6) is mounted, and a movable layer (11), the fixed layer (9) and the movable layer (11) exhibiting similar dielectric permittivities and being superposed along at least one surface facing the at least one connection conductor (6).
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: June 29, 2021
    Assignees: Supergrid Institute, Universite Claude Bernard Lyon 1, Ecole Centrale De Lyon, Institut National Des Sciences Appliquees De Lyon, Centre National De La Recherche Scientifique
    Inventor: Cyril Buttay
  • Patent number: 11046051
    Abstract: A metal-on-ceramic substrate comprises a ceramic layer, a first metal layer, and a bonding layer joining the ceramic layer to the first metal layer. The bonding layer includes thermoplastic polyimide adhesive that contains thermally conductive particles. This permits the substrate to withstand most common die attach operations, reduces residual stress in the substrate, and simplifies manufacturing processes.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 29, 2021
    Assignee: Materion Corporation
    Inventor: Richard J. Koba
  • Patent number: 11039533
    Abstract: A printed wiring board includes: a first insulating layer having a first surface and a second surface opposite from the first surface; a second insulating layer stacked on the first surface of the first insulating layer; and a conductor wiring interposed between the first insulating layer and the second insulating layer. The first insulating layer contains a liquid crystal polymer. The second insulating layer contains a cured product of a thermosetting composition, containing an inorganic filler and a thermosetting component, and a fibrous base member. A temperature, at which a decrease in the mass of the second insulating layer that has had its temperature increased at a temperature increase rate of 10° C./min from an initial-state temperature of 25° C. reaches 5% of its initial-state mass, is equal to or higher than 355° C.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: June 15, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroaki Takahashi, Masaya Koyama, Kiyotaka Komori, Yutaka Tashiro, Hiroki Morikawa
  • Patent number: 10998250
    Abstract: A bonded body is formed to configured to join a ceramic member formed of a Si-based ceramic and a copper member formed of copper or a copper alloy, in which, in a joint layer formed between the ceramic member and the copper member, a crystalline active metal compound layer formed of a compound including an active metal is formed on the ceramic member side.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 4, 2021
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventor: Nobuyuki Terasaki
  • Patent number: 10985118
    Abstract: A method and a high-frequency module that includes (a) a high frequency die that includes multiple die pads, (b) a substrate that comprises a first buildup layer, a second buildup layer and a core that is positioned between the first buildup layer and a second buildup layer, (c) a heat sink and coupling module that comprises a heat sink and multiple first conductors that pass through the heat sink and extend outside the heat sink; (d) a line card that comprises multiple line card pads that are coupled to external ends of the multiple first conductors; (e) coupling elements that are coupled to internal end of the multiple first conductors; and (f) multiple second conductors that pass through the substrate without reaching a majority of a depth of the core, and couple the multiple die pads to the coupling elements. The high frequency it not lower than fifty gigabits per second.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 20, 2021
    Assignees: XSIGHT LABS LTD., DustPhotonics
    Inventors: Guy Koren, Ben Rubovitch
  • Patent number: 10980112
    Abstract: A multilayer wiring board includes first and second insulating layers, a first conductive wiring layer on the first insulating layer, a second conductive wiring layer on a surface of the second insulating layer facing the first insulating layer, an interlayer connection conductor including an intermetallic compound and penetrating through the first insulating layer to interconnect the first and second conductive wiring layers, a first intermetallic compound layer between the first conductive wiring layer and the interlayer connection conductor, and a second intermetallic compound layer between the second conductive wiring layer and the interlayer connection conductor, wherein the intermetallic compounds in the first and second intermetallic compound layers have a composition different from that of the intermetallic compound in the interlayer connection conductor, and the first intermetallic compound layer is located at a level different from a level of an interface between the first conductive wiring layer an
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: April 13, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takako Sato, Takeshi Osuga, Masanori Okamoto
  • Patent number: 10971308
    Abstract: A multilayer capacitor includes a body and external electrodes on external surfaces of the body. The body includes a plurality of internal electrodes alternately laminated with dielectric layers. The external electrodes are electrically connected to the internal electrodes. Edges of cover portions of the body are rounded. The rounded edges have a radius of curvature R and the body has a thickness T, such that R and T satisfy 10 ?m?R?T/4. Among the plurality of internal electrodes, an internal electrode in each of the cover portions has a width less than that of an internal electrode of the central portion.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD
    Inventors: Byeong Gyu Park, Yong Jin Yun, So Ra Kang, Jae Yeol Choi
  • Patent number: 10966312
    Abstract: An apparatus includes a substrate and an electronic circuit comprising a plurality of conductive tracts forming a printed litz line on the substrate for distributing a signal therebetween in order to increase effective conductance relative to a single conductive line not divided into tracts. The plurality of conductive tracts may be formed by printing a pattern on the substrate and removing portions of the pattern to leave the plurality of conductive tracts. The removing portions of the pattern may be performed by a removal process such as laser cutting, milling, etching, or masking. For example, the removal may be performed by applying ultrashort laser pulses. The printing may be performed by a jetting process, a spray process, an extrusion process, a dispensing process, and/or other types of processes for applying materials.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 30, 2021
    Assignees: Sciperio, Inc, University of South Florida
    Inventors: Thomas Weller, Kenneth H. Church, Ramiro A Ramirez, Paul I. Deffenbaugh, Casey W. Perkowski
  • Patent number: 10943714
    Abstract: A cable has an outer sheath made from fluoropolymer and a conductor core having several individual elements which are surrounded by an inner sheath which penetrates into an intermediate chamber between the individual elements. A heat resistant film is disposed between the inner sheath and the outer sheath and is formed of a metal layer and a support layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 9, 2021
    Assignee: LEONI Kabel GmbH
    Inventors: Michael Dreiner, Jens Mosebach, Holger Winkelmann
  • Patent number: 10940674
    Abstract: The present invention provides a resin varnish, a prepreg, a laminate and a printed wiring board, using a thermosetting resin composition having high heat resistance, low relative permittivity, high metal foil adhesion, high glass transition temperature and low thermal expansion and excellent in moldability and platability. Specifically, the resin varnish contains (A) a maleimide compound, (B) an epoxy resin, (C) a copolymer resin having a structural unit derived from an aromatic vinyl compound and a structural unit derived from a maleic anhydride, (D) a silica treated with an aminosilane coupling agent, and (G) an organic solvent.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: March 9, 2021
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Yoshikatsu Shiraokawa, Minoru Kakitani, Hiroshi Shimizu, Keisuke Kushida, Tatsunori Kaneko
  • Patent number: 10913879
    Abstract: Provided herein are thermally conductive underfill compositions which have a combination of melt viscosity, glass transition temperature (Tg), coefficient of thermal expansion, and/or transparency that renders such materials useful for the preparation of a variety of electronic devices, such as flip chip packages, stacked dies, hybrid memory cubes, through-silica via (TSV) devices, and the like. In certain embodiments of the invention, there are provided assemblies comprising a first article permanently adhered to a second article by a cured aliquot of a formulation as described herein. In certain embodiments of the invention, there are provided methods for adhesively attaching a first article to a second article. In certain embodiments of the present invention, there are provided methods for improving heat dissipation by electronic devices assembled employing thermally conductive, but electrically non-conductive adhesive.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 9, 2021
    Assignee: Henkel IP & Holding GmbH
    Inventors: Jie Bai, Ly Do, Hung Chau, Younsang Kim, Julissa Eckenrode
  • Patent number: 10881000
    Abstract: A printed circuit board includes a core layer having a first surface and a second surface opposing the first surface; a first built-up structure disposed on the first surface of the core layer; a second built-up structure disposed on the second surface of the core layer; and a first penetration portion penetrating the first built-up structure and the core layer and penetrating a portion of the second built-up structure. The first penetration portion has a step portion on at least a portion of a wall of the first penetration portion in the region of the first penetration portion penetrating the second built-up structure, and a region including the first penetration portion on a plane is configured as a flexible region.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yang Je Lee, Hyun Kyung Park, Jung Hoon Jang
  • Patent number: 10864698
    Abstract: A treated liquid crystal polymer resin sheet includes a main surface, a non-fiberized portion in which fibrous crystalline portions and a non-crystalline portion filling a gap between the crystalline portions are provided, and a fiberized portion in which the fibrous crystalline portions is exposed at the main surface with a gap between the crystalline portions that is unfilled.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 15, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Syota Chino, Hiroyuki Ohata
  • Patent number: 10861788
    Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yuan Ting, Chung-Wen Wu
  • Patent number: 10840021
    Abstract: A multilayer ceramic electronic component includes a multilayer body that includes a second main surface defining and functioning as a mounting surface. Outer electrodes include underlying electrode layers including a conductive metal and a glass component and conductive resin layers including a thermosetting resin and a metal component. The underlying electrode layers extend from first and second end surfaces onto at least the second main surface. The conductive resin layers extend onto the underlying electrode layers provided on the second main surface, portions of the second main surface, and portions of the underlying electrode layers provided on the first end surface and the second end surface and cover portions of the first and second end surfaces, the portions including areas corresponding to about 9% or more and about 82% or less of areas of the first and the second end surfaces.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: November 17, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Mayumi Yamada
  • Patent number: 10806029
    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 13, 2020
    Assignee: CATLAM, LLC
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Patent number: 10806031
    Abstract: There is provided an organic insulating body which contains a cyclic olefin copolymer as a main component and a peroxide having a benzene ring, and has such a property that a loss tangent peak appears at 120° C. or higher in a dynamic mechanical analysis.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 13, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Tadashi Nagasawa, Chie Chikara, Satoshi Kajita
  • Patent number: 10772215
    Abstract: A triggering condition is applied to a conductive polymer positioned in a drilled hole in a printed circuit board. The applied triggering condition causes the polymer to vertically expand within the drilled hole such that the expanded polymer creates an electrically conductive path between contact pads located in different layers of the printed circuit board.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joseph Kuczynski, Timothy Tofil, Jeffrey N. Judd, Matthew Doyle, Scott D. Strand
  • Patent number: 10755994
    Abstract: A semiconductor package structure includes a patterned conductive layer with a front surface, a back surface, and a side surface connecting the front surface and the back surface. The semiconductor package structure further includes a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer, a first encapsulant covering at least the back surface of the patterned conductive layer, and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 25, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: You-Lung Yen
  • Patent number: 10727081
    Abstract: A method for manufacturing a package substrate for mounting a semiconductor device, including a substrate forming step (a) of forming a supporting substrate for circuit formation including a first insulating resin layer, a release layer including at least a silicon compound, and ultrathin copper foil having a thickness of 1 ?m to 5 ?m, in this order; a first wiring conductor forming step (b) of forming a first wiring conductor on the ultrathin copper foil of the supporting substrate for circuit formation by pattern copper electroplating; a lamination step (c) of disposing a second insulating resin layer so as to be in contact with the first wiring conductor, and heating and pressurizing the second insulating resin layer for lamination; a second wiring conductor forming step (d) of forming in the second insulating resin layer a non-through hole reaching the first wiring conductor and connecting an inner wall of the non-through hole.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Syunsuke Hirano, Yoshihiro Kato, Takaaki Ogashiwa, Kazuaki Kawashita, Youichi Nakajima
  • Patent number: 10720279
    Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric layer and a plurality of internal electrodes disposed to face each other with the dielectric layer interposed therebetween and external electrodes disposed on external surfaces of the ceramic body and electrically connected to the internal electrodes, respectively. The external electrode includes electrode layers electrically connected to the internal electrodes, and plating layers disposed on the electrode layers. At least one point, at which slopes of tangent lines of one of the electrode layers and the plating layers are opposite to each other, is disposed in a region within a range of ±0.2 BW around a point (0.5 BW) that is a halfway point of an overall width BW of the electrode layers disposed on the first surface or the second surface of the ceramic body.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Bum Soo Kim, Jang Yeol Lee, Jong Ho Lee
  • Patent number: 10703070
    Abstract: A resin composite film comprising a cellulose microfiber sheet and a resin, the resin composite film satisfying the following: (1) in a modulus mapping obtained by an examination of a cross-section with an AFM along the thickness direction, the fibers constituting the cellulose microfiber sheet have an average fiber diameter and a maximum fiber diameter, both calculated through image analysis, of 0.01-2.0 ?m and 15 ?m or smaller, respectively; and (2) at least one surface of the resin composite film has an overcoat resin layer having an average thickness, determined from the modulus mapping, of 0.3-100 ?m.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: July 7, 2020
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventors: Yamato Saito, Masayuki Nakatani, Hiroko Kawaji, Yoko Fujimoto, Hirofumi Ono, Kazufumi Kawahara
  • Patent number: 10699993
    Abstract: A wiring board includes an insulating substrate that is rectangular in a plan view, a plurality of mount electrodes arranged to face each other on a first main surface of the insulating substrate along a pair of opposing sides of the insulating substrate in a plan view, a plurality of terminal electrodes arranged to face each other on a second main surface of the insulating substrate along the pair of opposing sides of the insulating substrate in a perspective plan view, and an inner metal layer arranged inside the insulating substrate and extending in a direction perpendicular to the pair of opposing sides of the insulating substrate in a perspective plan view.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 30, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Michio Imayoshi, Yousuke Moriyama
  • Patent number: 10684734
    Abstract: A transparent high-conductivity layer for providing electrostatic feedback to a user of an electronic device. The transparent high-conductivity layer is positioned over a capacitive input sensor and has a resistivity sufficiently high to prevent interference with the capacitive input sensor. As one example, the transparent high-conductivity layer can be formed from a layer of geometrically-separated regions of high-conductivity material. The average distance between geometrically-separated regions can substantially define the resistivity of the transparent high-conductivity layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 16, 2020
    Assignee: Apple Inc.
    Inventors: Alan Kleiman-Schwarsctein, Senem E. Emgin, Terrence L. Van Ausdall, Xianwei Zhao, Yuxi Zhao, Soyoung Kim
  • Patent number: 10679961
    Abstract: The invention provides a circuit pin positioning structure, a fabrication method of soldered circuit elements and a method of forming circuit pins of a stacked package, applicable to a semiconductor package structure. A positioning rack and a plurality of conductor elements are used. A plurality of positioning holes are provided on a bottom surface of the positioning rack to form a conductor positioning area, and an operational portion is formed on an opposing surface away from the conductor positioning area, for being mounted with pick and place equipment. The conductor elements are positioned in the positioning holes. When the pick and place equipment loads and moves the positioning rack to preformed circuit contacts of the stacked package, the conductor elements are soldered to the preformed circuit contacts and then the positioning rack is removed.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 9, 2020
    Assignee: TARNG YU ENTERPRISE CO., LTD.
    Inventors: Tsung-Chi Chen, Mu-Jung Huang
  • Patent number: 10672722
    Abstract: Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: June 2, 2020
    Assignee: DAI NIPPON PRINTING Co., Ltd.
    Inventors: Ryohei Kasai, Tsuyoshi Tsunoda, Yuichi Yamamoto, Shuji Sagara, Masaya Tanaka
  • Patent number: 10672729
    Abstract: A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Ting-Ting Kuo, Yu-Chih Huang, Chih-Wei Lin, Hsiu-Jen Lin, Chih-Hua Chen, Ming-Da Cheng, Ching-Hua Hsieh, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 10667391
    Abstract: A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. Each build-up layer includes a first insulating layer including reinforcing material, a second resin insulating layer not containing reinforcing material, a first via conductor through the first insulating layer, and a second via conductor through the second insulating layer such that the top diameter of the first via conductor is substantially equal to the top diameter of the second via conductor and that the bottom diameter of the first via conductor is smaller than the bottom diameter of the second via conductor. The conductor layer on the first insulating layer includes a metal foil, a seed layer and an electrolytic plating film. The conductor layer on the second insulating-layer includes a seed layer and an electrolytic plating film and has thickness substantially equal to thickness of the conductor layer on the first insulating-layer.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 26, 2020
    Assignee: IBIDEN CO., LTD.
    Inventors: Naohito Ishiguro, Takamitsu Hattori
  • Patent number: 10655209
    Abstract: There is provided an inexpensive electromagnetic shield that can achieve exceptional shielding and display visibility characteristics, and provide high environmental resistance as necessary. In an electromagnetic shield (1), an intermediate layer (3) is formed on a glass substrate (2) comprising soda lime glass, an electroconductive layer (4) of Al is formed thereon, and openings (5) are formed by wet etching on the intermediate layer (3) and the electroconductive layer (4) after these layers have been formed by sputtering or vacuum deposition. Furthermore, an ITO layer (6) is formed on the entire glass surface including the intermediate layer (3) and the electroconductive layer (4) after the openings (5) are formed. In this configuration, the intermediate layer (3) comprises a mixture of at least one metal selected from chromium, molybdenum, and tungsten, and at least one oxide selected from oxides of silicon, oxides of aluminum, and oxides of titanium.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 19, 2020
    Assignees: NORITAKE CO., LIMITED, NORITAKE ITRON CORPORATION
    Inventors: Hitoshi Tsuji, Tadami Maeda, Isamu Kanda
  • Patent number: 10658655
    Abstract: Disclosed is a copper foil including a copper layer having a matte surface and a shiny surface, wherein the copper foil has a first surface of a direction of the matte surface of the copper layer and a second surface of a direction of the shiny surface of the copper layer, wherein a dynamic friction coefficient of the first surface is designated by ?k1 and a dynamic friction coefficient of the second surface is designated by ?k2. A ratio of three-dimensional surface area to two-dimensional surface area of the first surface is designated by Fs1, a ratio of three-dimensional surface area to two-dimensional surface area of the second surface is designated by Fs2.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 19, 2020
    Assignee: KCF TECHNOLOGIES CO., LTD.
    Inventors: Young Wook Chae, Young Hyun Kim, Shan Hua Jin