Insulating Patents (Class 174/258)
  • Patent number: 11903146
    Abstract: A printed wiring board is provided with: a core substrate corresponding to a stack area in which an interlayer connection conductor constituting an inner via is continuous; and a build-up layer comprising a resin layer stacked on the core substrate and a conductor layer on said resin layer. A via inner space inside the interlayer connection conductor constituting the inner via is hollow, and said via inner space communicates to the outside via a hole section provided in the build-up layer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 13, 2024
    Assignee: Kyocera Corporation
    Inventors: Tomoya Nagase, Takashi Ishioka
  • Patent number: 11827770
    Abstract: Provided is a glass fiber-reinforced resin molded article having high dimension stability and low dielectric characteristics. In the glass fiber-reinforced resin molded article, the fiber diameter D of glass fiber included in the glass fiber-reinforced resin molded article is in the range of 5.0 to 15.0 ?m, the dielectric constant Dk at a measurement frequency of 1 GHz of the glass fiber is in the range of 4.0 to 7.0, the linear expansion coefficient C of the glass fiber is in the range of 2.0 to 6.0 ppm/K, the number average fiber length L of the glass fiber is in the range of 150 to 400 ?m, and the D, Dk, C, and L satisfy the following formula (1): 57.9?Dk×C1/4×L1/2/D1/4?70.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: November 28, 2023
    Assignee: Nitto Bosekl Co., Ltd.
    Inventor: Yosuke Nukui
  • Patent number: 11830806
    Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Chang, Hsuan-Ming Huang, Jian-Hong Lin, Ming-Hong Hsieh, Mingni Chang, Ming-Yih Wang
  • Patent number: 11721482
    Abstract: A method of producing a ceramic electronic component includes baking a first electrode paste containing a metal powder at a first temperature to form a first electrode layer at a first region of a ceramic body, baking a second electrode paste containing a metal powder of the same type as the metal powder in the first electrode paste at a second temperature lower than the first temperature to form a second electrode layer at a second region different from the first region of the ceramic body, and applying a physical shock treatment to a surface of the second electrode layer to densify a surface layer portion of the second electrode layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 8, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi Sawada, Kenichi Togo
  • Patent number: 11723153
    Abstract: A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: August 8, 2023
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Yun Mi Bae, Soon Gyu Kwon, Sang Hwa Kim, Sang Young Lee, Jin Hak Lee, Han Su Lee, Dong Hun Jeong, In Ho Jeong, Dae Young Choi, Jung Ho Hwang
  • Patent number: 11705284
    Abstract: A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes each provided at one of two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers provided on both sides in a length direction of a surface of the capacitor main body. The two interposers each include a protrusion extending from one of the two interposers to another of the two interposers.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 18, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Yokomizo, Shinobu Chikuma, Yohei Mukobata
  • Patent number: 11700758
    Abstract: A display device includes: a light-emitting element at a display area; a driving element electrically connected to the light-emitting element; an encapsulation layer covering the light-emitting element; a touch sensor on the encapsulation layer; a connection pad at a bonding area, the connection pad including a lower conductive layer, an intermediate conductive layer on the lower conductive layer, and an upper conductive layer on the intermediate conductive layer; a cladding layer covering at least a side surface of the intermediate conductive layer and including an organic material; a passivation layer covering an upper surface of the cladding layer and including an inorganic material, a portion of the passivation layer being located under the upper conductive layer; and a driving circuit attached to the connection pad.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: July 11, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Yup Kim, Deukjong Kim, Hagyeong Song
  • Patent number: 11670577
    Abstract: A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu Jeng, Po-Hao Tsai, Po-Yao Chuang, Feng-Cheng Hsu, Shuo-Mao Chen, Techi Wong
  • Patent number: 11636977
    Abstract: A multilayer ceramic capacitor includes a multilayer body, a first internal electrode layer extending to opposing end surfaces of the multilayer body, a second internal electrode layer extending to opposing side surfaces of the multilayer body, first and second external electrodes connected to the first internal electrode layer and provided on the opposing end surfaces, and third and fourth external electrodes connected to the second internal electrode layer and provided on the opposing side surfaces. The second internal electrode layer includes a central section in a central portion of the dielectric layer and an extending section extending to the opposing side surfaces. The first internal electrode layer is larger in number than the second internal electrode layer, at least two first internal electrode layers are successively layered, and the extending section is larger in thickness than the central section located in the central portion of the dielectric layer.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: April 25, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tomohiro Sasaki
  • Patent number: 11610738
    Abstract: A passive component includes a body including a dummy portion and a device portion. The dummy portion and the device portion extend in a first direction and are arranged such that a longitudinal axis of the device portion is offset from a longitudinal axis of the body in a second direction perpendicular to the first direction. The passive component further includes first and second electrical contacts on at least one surface of the body.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 21, 2023
    Assignee: Avago Technologies International Sales Pte, Limited
    Inventors: Michael Howard Leary, Chris Chung, Ah Ron Lee
  • Patent number: 11587737
    Abstract: A multilayer ceramic capacitor includes a ceramic main including first internal electrodes each drawn out to and reaching a pair of end surfaces and second internal electrodes each drawn out to and reaching a pair of side surfaces. A pair of end-surface external electrodes are respectively provided on the pair of end surfaces to be connected to the first internal electrodes, and a pair of side-surface external electrodes are respectively provided on the pair of side surfaces to be connected to the second internal electrodes. Each of the second internal electrodes has drawn-out parts that extend from an electrode main part and reach the pair of side surfaces, and with respect to each of the pair of side surfaces, two or more of the drawn-out parts are provided to extend from the electrode main part and reach the side surface.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Takashi Sasaki, Tomohiko Zaima
  • Patent number: 11581685
    Abstract: The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: February 14, 2023
    Assignee: COMMSCOPE TECHNOLOGIES LLC
    Inventors: Bernard Harold Hammond, Jr., David Patrick Murray, Ian Robert George
  • Patent number: 11577960
    Abstract: The invention concerns a method of forming a graphene device, the method comprising: forming a graphene film (100) over a substrate; depositing, by gas phase deposition, a polymer material covering a surface of the graphene film (100); and removing the substrate from the graphene film (100), wherein the polymer material forms a support (102) for the graphene film (100).
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 14, 2023
    Assignees: Centre National de la Recherche Scientifique, UNIVERSITE GRENOBLE ALPES
    Inventors: Dipankar Kalita, Vincent Bouchiat, Laetitia Marty, Nedjma Bendiab
  • Patent number: 11570882
    Abstract: A substrate for mounting electronic element includes: a first substrate including a first surface and a second surface opposite to the first surface; a second substrate including a third surface and a fourth surface opposite to the third surface; and heat dissipation bodies each including a fifth surface and a sixth surface opposite to the fifth surface. The first substrate includes at least one mounting portion for at least one electronic element at the first surface. Heat conduction of the heat dissipation bodies in a direction perpendicular to a longitudinal direction of the at least one mounting portion and perpendicular to a direction along opposite sides of the second substrate is greater than heat conduction of the heat dissipation bodies in the longitudinal direction of the at least one mounting portion and in the direction along opposite sides of the second substrate in a transparent plan view of the substrate.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: January 31, 2023
    Assignee: KYOCERA CORPORATION
    Inventors: Yukio Morita, Noboru Kitazumi, Yousuke Moriyama
  • Patent number: 11569019
    Abstract: An electronic component includes: a first substrate having a first surface; a second substrate having a second surface facing the first surface across an air gap; a first coil pattern that is located on the first surface so as to face the second surface across the air gap; a second coil pattern that is located in a second region on the second surface and faces the first surface across the air gap, at least a part of the second region overlapping with a first region in plan view, the first region being formed of a region in which the first coil pattern is located and a region surrounded by the first coil pattern; and a connection terminal connecting the first coil pattern and the second coil pattern.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: January 31, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hitoshi Tsukidate, Takuma Kuroyanagi
  • Patent number: 11510320
    Abstract: A method of the invention is a method of processing a wiring substrate that includes a configuration in which conductors locally disposed on a substrate are coated with resin having inorganic members that form a filler and are dispersed in an organic member, the method including: removing the organic member from a surface layer side of the resin by use of an ashing method; and removing, by use of a wet cleaning method, the inorganic members remaining the surface layer side of the resin from which the organic member is removed.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 22, 2022
    Assignee: ULVAC, INC.
    Inventors: Muneyuki Sato, Yasuhiro Morikawa, Minoru Suzuki
  • Patent number: 11488778
    Abstract: A multilayer electronic component includes a multilayer capacitor including a capacitor body and a plurality of external electrodes spaced apart from each other on a mounting surface of the capacitor body, and a connection terminal including a plurality of land portions disposed on the plurality of external electrodes, respectively. When a thickness of the multilayer capacitor is defined as T1 and a distance from an uppermost end of the plurality of external electrodes to a bottom of the connection terminal is defined as T2, T1/T2 is 0.6 to 0.9.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 1, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Se Hun Park, Hun Gyu Park, Woo Chul Shin, Ji Hong Jo
  • Patent number: 11476204
    Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 18, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
  • Patent number: 11476291
    Abstract: There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 18, 2022
    Assignee: SONY CORPORATION
    Inventors: Satoru Wakiyama, Naoki Jyo, Kan Shimizu, Toshihiko Hayashi, Takuya Nakamura
  • Patent number: 11439022
    Abstract: A printed circuit board includes a coreless substrate including an insulating body and a plurality of core wiring layers disposed on or within the insulating body, a build-up insulating layer covering at least a portion of each of an upper surface and a lower surface of the coreless substrate, and a build-up wiring layer disposed on at least one of an upper surface and a lower surface of the build-up insulating layer. A through-opening penetrates through the insulating body and is configured to receive an electronic component therein, and the first build-up insulating layer extends into the through-opening to embed the electronic component.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Il Cho, Yong Ho Baek, Sang Min Lee, Jae Min Choi, Tae Seong Kim
  • Patent number: 11437304
    Abstract: Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: September 6, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Roger Paul Stout, Chee Hiong Chew, Sadamichi Takakusaki, Francis J. Carney
  • Patent number: 11426970
    Abstract: A laminated uncured sheet of the present disclosure has a structure in which resin sheet layers and resin layers are alternately laminated and a through hole penetrating in the laminating direction is formed, wherein the resin sheet layers are formed with a thermosetting resin composition containing a thermosetting resin as a main component, the resin layers are formed with a thermoplastic resin composition containing a thermoplastic resin, and the thermoplastic resin composition is adhered to the inner wall surface of the resin sheet layer part in the through hole.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: August 30, 2022
    Assignee: KYOCERA CORPORATION
    Inventors: Tadashi Nagasawa, Satoshi Yoshiura, Chie Chikara, Satoshi Kajita, Yasuhide Tami
  • Patent number: 11410921
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee
  • Patent number: 11411370
    Abstract: A Cu—Si—Cu substrate having a silicon substrate, copper plating on opposite sides of the silicon substrate, and copper vias extending thru the silicon substrate to electrically and thermally connect the copper platings together. The thicknesses of the silicon substrate and the copper platings are selected so that a coefficient of thermal expansion (CTE) of the Cu—Si—Cu substrate is substantially the same as a CTE of a material to be mounted on the Cu—Si—Cu substrate.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 9, 2022
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Susant Patra, Robert J. Deri, John W. Elmer
  • Patent number: 11393747
    Abstract: A substrate structure and a method for manufacturing the same are provided. The substrate structure includes a first conductive layer, a dielectric layer, a second conductive layer and a connection layer. The dielectric layer is disposed on the first conductive layer. The dielectric layer defines an opening exposing the first conductive layer. The second conductive layer is disposed on the dielectric layer. The connection layer extends from an upper surface of the first conductive layer to a lateral surface of the second conductive layer. A surface roughness of an upper surface of the second conductive layer ranges from about 0.5 ?m to about 1.25 ?m.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 19, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11367627
    Abstract: The present invention relates to a method for manufacturing a semiconductor device in which a circuit element including a semiconductor chip, and a through conductor connecting an insulation layer in a thickness direction are embedded in the insulation layer. A wiring structure in which a predetermined pattern of wiring conductors is formed along a planar direction on an insulation part is created, and thereafter the wiring structure is sealed in the insulation layer in a state where the wiring structure is erected vertically. Consequently, the wiring conductor of the wiring conductor is caused to function as the through conductor in the insulation layer.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 21, 2022
    Assignee: NAGASE & CO., LTD.
    Inventors: Tadashi Takano, Michihiro Sato
  • Patent number: 11359047
    Abstract: Compositions and methods for forming epoxy resin systems are provided. In one embodiment, a composition is provided for an epoxy resin system including an epoxy resin blend comprising an epoxy resin, a first curing agent selected from the group of a polyarylene alkylphosphonate, a polyarylene arylphosphonate, and combinations thereof, and a second curing agent.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 14, 2022
    Assignee: HEXION INC.
    Inventors: Amitabh Bansal, Larry Steven Corley, Diana Sepulveda-Camarena, Jennifer W. Chung, Leeanne Taylor, Alla Hale
  • Patent number: 11327587
    Abstract: In various embodiments, bilayers are formed in electronic devices at least in part by anodization of metal-alloy base layers.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 10, 2022
    Assignee: H.C. STARCK INC.
    Inventors: Helia Jalili, Francois Dary, Barbara Cox
  • Patent number: 11312858
    Abstract: Provided is a resin composition containing: a modified polyphenylene ether compound terminally modified with a substituent having an unsaturated carbon-carbon double bond; a cross-linking curing agent having an unsaturated carbon-carbon double bond in its molecule; a silane coupling agent having a phenylamino group in its molecule; and silica. A content of the silica is 60 to 250 parts by mass with respect to a total of 100 parts by mass of the modified polyphenylene ether compound and the cross-linking curing agent.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: April 26, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tatsuya Arisawa, Fumito Suzuki, Shunji Araki, Hirohisa Goto, Yuki Inoue
  • Patent number: 11310922
    Abstract: A board-to-board connecting structure which adds no significant thickness to a single printed circuit board includes a first circuit board and a second circuit board. The first circuit board includes first circuit substrate, adhesive layer, and second circuit substrate. The first circuit substrate includes first base layer, first inner wiring layer with first pad, and first outer wiring layer defining a receiving space. The second circuit substrate includes insulating layer and two second outer wiring layers. A conductive via in the second circuit substrate connects the two second outer wiring layers. The second circuit board includes second base layer and also two third outer wiring layers each with a second pad. The second circuit board is laterally disposed in the receiving space and one second pad connects to the conductive via and the other to the first pad.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 19, 2022
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD
    Inventors: Rui-Wu Liu, Man-Zhi Peng
  • Patent number: 11264967
    Abstract: A multi-piece wiring substrate includes a matrix substrate including first and second insulating layers, and interconnection substrate regions arranged in a matrix. The matrix substrate includes dividing grooves opposing each other and disposed along boundaries between the interconnection substrate regions, and through-holes penetrating the matrix substrate in a thickness direction at positions where the dividing grooves are disposed. The inner surface conductor gradually decreases in thickness from a thick portion in a middle of the inner surface conductor, to thin portions disposed on a side of a boundary between the first and second insulating layers and on a first main surface side, and includes inclination portions each of which gradually increases in thickness from a boundary between corresponding one of the dividing grooves and the inner surface conductor to an inner surface of the inner surface conductor, in vertical sectional view.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 1, 2022
    Assignee: KYOCERA CORPORATION
    Inventor: Yoshitomo Onitsuka
  • Patent number: 11264332
    Abstract: Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Owen Fay, Chan H. Yoo
  • Patent number: 11227824
    Abstract: A chip carrier and a manufacturing method thereof are provided. The chip carrier includes a first structure layer and a second structure layer. The first structure layer has at least one opening and includes at least one first insulating layer. A thermal expansion coefficient of the first insulating layer is between 2 ppm/° C. and 5 ppm/° C. The second structure layer is disposed on the first structure layer and defines at least one cavity with the first structure layer. The second structure layer includes at least one second insulating layer, and a thermal expansion coefficient of the second insulating layer is equal to or greater than the thermal expansion coefficient of the first insulating layer.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 18, 2022
    Inventor: Chung W. Ho
  • Patent number: 11217394
    Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes and external electrodes disposed on external surfaces of the body and electrically connected to the internal electrodes, wherein in the body, corners of cover portions include curved surfaces, and 10 ?m?R?T/4 in which R is a radius of curvature of the curved surface corners and T is a thickness of the body, and when a distance from a surface of the body to an internal electrode closest to the surface of the body among the plurality of internal electrodes is a margin, a margin (?) of each of the corners formed as the curved surfaces in the cover portions is greater than or equal to a margin (Wg) of the body in a width direction.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byeong Gyu Park, So Ra Kang, Yong Jin Yun, Jea Yeol Choi, Jung Min Park
  • Patent number: 11195790
    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Akihisa Kuroyanagi, Jun Woo Myung, Eun Sil Kim, Yeong A Kim
  • Patent number: 11177294
    Abstract: An array substrate, a manufacturing method thereof and a display device are provided. A display unit is disposed on a first surface of a base substrate, and a driving circuit is disposed on a second surface of the base substrate opposite to the first surface, the driving circuit is electrically connected with the display unit through a signal connection structure in at least one via structure, a longitudinal section of the at least one via hole is a trapezoid, and a length of a bottom edge of the trapezoid at one side of the trapezoid close to the display unit is larger than a length of a bottom edge of the trapezoid at one side of the trapezoid away from the display unit.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dongni Liu, Minghua Xuan, Li Xiao, Detao Zhao, Liang Chen, Hao Chen
  • Patent number: 11172567
    Abstract: An assembly method and device for a circuit structural member, and a circuit structural member. The assembly method comprises: measuring a depth and path of a channel between at least one chip and a printed circuit board (PCB), the at least one chip being arranged on the PCB; determining a thickness and path of a heat dissipation reinforcement material according to the depth and path of the channel between the at least one chip and the PCB and a predetermined heat dissipation parameter, so as to configure a dispensing parameter and a dispensing path; coating the heat dissipation reinforcement material in the channel between the at least one chip and the PCB according to the dispensing parameter and dispensing path; and heating the heat dissipation reinforcement material to a first predetermined temperature, such that the heat dissipation reinforcement material permeates into the chip and the PCB.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: November 9, 2021
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventor: Zhulin Huang
  • Patent number: 11152291
    Abstract: A multilayer substrate includes a plurality of plates laminated in a thickness direction of the multilayer substrate, a resin layer provided between the plurality of plates adjacent in the thickness direction, an internal conductive layer provided between the plurality of plates adjacent in the thickness direction, and an external conductive layer provided over an outer surface of each plate of the plurality of plates located at both ends in the thickness direction, wherein a total thickness of the internal conductive layer and the external conductive layer is equal to or less than 25% of a total thickness of the plurality of plates.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 19, 2021
    Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Toshiki Iwai, Taiji Sakai
  • Patent number: 11135825
    Abstract: According to the present invention, a surface of a prepreg (104), said surface being provided with a partially fused structure (102A), and a surface of a metal member (110) are brought into contact with each other, and heat and pressure are subsequently applied thereto. After completely melting a resin containing a thermoplastic resin and adhering to the prepreg (104) so that a reinforcing fiber substrate (101) is impregnated with the molten resin, the resin is cured to obtain a matrix resin (105), thereby forming a CFRP layer (120) that serves as a fiber-reinforced resin material, and the CFRP layer is simultaneously compression-bonded to the metal member (110), so that a metal-CFRP composite body (100) in which the CFRP layer (120) and the metal member (110) are firmly bonded to each other is formed.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: October 5, 2021
    Assignee: NIPPON STEEL Chemical & Material Co., Ltd.
    Inventors: Hiroyuki Takahashi, Hideki Andoh
  • Patent number: 11134568
    Abstract: Provided is a high-frequency circuit laminate that can reduce the transmission loss of electrical signals in high-frequency circuits and produce circuit boards with excellent smoothness. The high-frequency circuit laminate according to the present invention includes a metal layer and a resin layer which are laminated in contact with each other, the resin layer having an elastic modulus from 0.1 to 3 GPa, and the resin layer having an dielectric loss tangent from 0.001 to 0.01 and a relative permittivity from 2 to 3 at a frequency of 10 GHz at 23° C.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 28, 2021
    Assignee: JSR CORPORATION
    Inventors: Isao Nishimura, Nobuyuki Miyaki, Toshiaki Kadota, Shintarou Fujitomi, Tomotaka Shinoda
  • Patent number: 11121020
    Abstract: A method for manufacturing a printed wiring board which includes: Step (A) of laminating an adhesive sheet including a support and a resin composition layer bonded to the support to an inner layer board so that the resin composition layer is bonded to the inner layer board; Step (B) of thermally curing the resin composition layer to form an insulating layer; and Step (C) of removing the support, in this order, in which the support satisfies a condition (MD1): a maximum expansion coefficient EMD in an MD direction at 120° C. or more is less than 0.2% and a condition (TD1): a maximum expansion coefficient ETD in a TD direction at 120° C. or more is less than 0.2% below, when being heated under predetermined heating conditions, does not lower the yield even when the insulating layer is formed by thermally curing the resin composition layer with a support attached to the resin composition layer.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: September 14, 2021
    Assignee: Ajinomoto Co., Inc.
    Inventors: Masanori Ohkoshi, Hirohisa Narahashi, Eiichi Hayashi
  • Patent number: 11099669
    Abstract: A conductive structure is provided. The conductive structure includes a template including a skeleton and a pore therein and having flexibility, and a conductive material aggregated and formed on the skeleton and in the pore.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: August 24, 2021
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Wanjun Park, Sungwoo Chun
  • Patent number: 11071213
    Abstract: In one or more embodiments, a method of manufacturing a high impedance surface (HIS) apparatus comprises patterning a first conducting layer on a core to form a first set of conducting pads, and patterning a second conducting layer on the core to form a second set of conducting pads. The method further comprises applying solder paste to each of the conducting pads of the second set of conducting pads. Also, the method comprises placing chip capacitors on the solder paste on the second set of conducting pads. In addition, the method comprises applying underfill between the chip capacitors. Also, the method comprises applying solder paste to each of the conducting pads of the first set of conducting pads. In addition, the method comprises placing chip inductors on the solder paste on the first set of conducting pads. Further, the method comprises applying underfill between the chip inductors.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: July 20, 2021
    Assignee: The Boeing Company
    Inventors: Charles Muwonge, Kyu-Pyung Hwang, Terry Vogler, Young Kyu Song
  • Patent number: 11053593
    Abstract: Disclosed is a copper alloy article including: a substrate 10 made of a copper alloy; a polyester-based resin body 40; and a compound layer 20 for bonding the substrate 10 and the polyester-based resin body 40, wherein the compound layer 20 contains; a compound having a nitrogen-containing functional group and a silanol group, and an alkane type amine-based silane coupling agent.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 6, 2021
    Assignee: ADVANCED TECHNOLOGIES, INC.
    Inventors: Kinji Hirai, Isamu Akiyama, Tsukasa Takahashi, Takutaka Sugaya, Yuka Muto
  • Patent number: 11049661
    Abstract: A multilayer electronic component includes a body including a dielectric layer and first and second internal electrodes, and including first to sixth surfaces, a first external electrode including a first electrode layer extending to a portion of each of the first, second, fifth, and sixth surfaces and a first conductive resin layer, and a second external electrode including a second electrode layer extending to a portion of each of the first, second, fifth, and sixth surfaces and a second conductive resin layer. R1 and R2 satisfy R1>R2, in which R1 is defined as a surface roughness of each of the first, second, fifth, and sixth surfaces in contact with the first and second electrode layers, and R2 is defined as a surface roughness of each of the first, second, fifth, and sixth surfaces in contact with the first and second conductive resin layers.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Je Jung Kim, Seung Ryeol Lee, Su Kyoung Cha
  • Patent number: 11046051
    Abstract: A metal-on-ceramic substrate comprises a ceramic layer, a first metal layer, and a bonding layer joining the ceramic layer to the first metal layer. The bonding layer includes thermoplastic polyimide adhesive that contains thermally conductive particles. This permits the substrate to withstand most common die attach operations, reduces residual stress in the substrate, and simplifies manufacturing processes.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 29, 2021
    Assignee: Materion Corporation
    Inventor: Richard J. Koba
  • Patent number: 11049795
    Abstract: A power electronic module (1) including at least one semiconductor (5) that is connected to connection conductors (6, 7), and including a dielectric carrier (10) having both a fixed layer (9), on which at least one of said connection conductors (6) is mounted, and a movable layer (11), the fixed layer (9) and the movable layer (11) exhibiting similar dielectric permittivities and being superposed along at least one surface facing the at least one connection conductor (6).
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: June 29, 2021
    Assignees: Supergrid Institute, Universite Claude Bernard Lyon 1, Ecole Centrale De Lyon, Institut National Des Sciences Appliquees De Lyon, Centre National De La Recherche Scientifique
    Inventor: Cyril Buttay
  • Patent number: 11039533
    Abstract: A printed wiring board includes: a first insulating layer having a first surface and a second surface opposite from the first surface; a second insulating layer stacked on the first surface of the first insulating layer; and a conductor wiring interposed between the first insulating layer and the second insulating layer. The first insulating layer contains a liquid crystal polymer. The second insulating layer contains a cured product of a thermosetting composition, containing an inorganic filler and a thermosetting component, and a fibrous base member. A temperature, at which a decrease in the mass of the second insulating layer that has had its temperature increased at a temperature increase rate of 10° C./min from an initial-state temperature of 25° C. reaches 5% of its initial-state mass, is equal to or higher than 355° C.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: June 15, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroaki Takahashi, Masaya Koyama, Kiyotaka Komori, Yutaka Tashiro, Hiroki Morikawa
  • Patent number: 10998250
    Abstract: A bonded body is formed to configured to join a ceramic member formed of a Si-based ceramic and a copper member formed of copper or a copper alloy, in which, in a joint layer formed between the ceramic member and the copper member, a crystalline active metal compound layer formed of a compound including an active metal is formed on the ceramic member side.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 4, 2021
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventor: Nobuyuki Terasaki
  • Patent number: 10985118
    Abstract: A method and a high-frequency module that includes (a) a high frequency die that includes multiple die pads, (b) a substrate that comprises a first buildup layer, a second buildup layer and a core that is positioned between the first buildup layer and a second buildup layer, (c) a heat sink and coupling module that comprises a heat sink and multiple first conductors that pass through the heat sink and extend outside the heat sink; (d) a line card that comprises multiple line card pads that are coupled to external ends of the multiple first conductors; (e) coupling elements that are coupled to internal end of the multiple first conductors; and (f) multiple second conductors that pass through the substrate without reaching a majority of a depth of the core, and couple the multiple die pads to the coupling elements. The high frequency it not lower than fifty gigabits per second.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 20, 2021
    Assignees: XSIGHT LABS LTD., DustPhotonics
    Inventors: Guy Koren, Ben Rubovitch