Insulating Patents (Class 174/258)
  • Patent number: 10772215
    Abstract: A triggering condition is applied to a conductive polymer positioned in a drilled hole in a printed circuit board. The applied triggering condition causes the polymer to vertically expand within the drilled hole such that the expanded polymer creates an electrically conductive path between contact pads located in different layers of the printed circuit board.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joseph Kuczynski, Timothy Tofil, Jeffrey N. Judd, Matthew Doyle, Scott D. Strand
  • Patent number: 10755994
    Abstract: A semiconductor package structure includes a patterned conductive layer with a front surface, a back surface, and a side surface connecting the front surface and the back surface. The semiconductor package structure further includes a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer, a first encapsulant covering at least the back surface of the patterned conductive layer, and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 25, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: You-Lung Yen
  • Patent number: 10727081
    Abstract: A method for manufacturing a package substrate for mounting a semiconductor device, including a substrate forming step (a) of forming a supporting substrate for circuit formation including a first insulating resin layer, a release layer including at least a silicon compound, and ultrathin copper foil having a thickness of 1 ?m to 5 ?m, in this order; a first wiring conductor forming step (b) of forming a first wiring conductor on the ultrathin copper foil of the supporting substrate for circuit formation by pattern copper electroplating; a lamination step (c) of disposing a second insulating resin layer so as to be in contact with the first wiring conductor, and heating and pressurizing the second insulating resin layer for lamination; a second wiring conductor forming step (d) of forming in the second insulating resin layer a non-through hole reaching the first wiring conductor and connecting an inner wall of the non-through hole.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Syunsuke Hirano, Yoshihiro Kato, Takaaki Ogashiwa, Kazuaki Kawashita, Youichi Nakajima
  • Patent number: 10720279
    Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric layer and a plurality of internal electrodes disposed to face each other with the dielectric layer interposed therebetween and external electrodes disposed on external surfaces of the ceramic body and electrically connected to the internal electrodes, respectively. The external electrode includes electrode layers electrically connected to the internal electrodes, and plating layers disposed on the electrode layers. At least one point, at which slopes of tangent lines of one of the electrode layers and the plating layers are opposite to each other, is disposed in a region within a range of ±0.2 BW around a point (0.5 BW) that is a halfway point of an overall width BW of the electrode layers disposed on the first surface or the second surface of the ceramic body.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Bum Soo Kim, Jang Yeol Lee, Jong Ho Lee
  • Patent number: 10703070
    Abstract: A resin composite film comprising a cellulose microfiber sheet and a resin, the resin composite film satisfying the following: (1) in a modulus mapping obtained by an examination of a cross-section with an AFM along the thickness direction, the fibers constituting the cellulose microfiber sheet have an average fiber diameter and a maximum fiber diameter, both calculated through image analysis, of 0.01-2.0 ?m and 15 ?m or smaller, respectively; and (2) at least one surface of the resin composite film has an overcoat resin layer having an average thickness, determined from the modulus mapping, of 0.3-100 ?m.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: July 7, 2020
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventors: Yamato Saito, Masayuki Nakatani, Hiroko Kawaji, Yoko Fujimoto, Hirofumi Ono, Kazufumi Kawahara
  • Patent number: 10699993
    Abstract: A wiring board includes an insulating substrate that is rectangular in a plan view, a plurality of mount electrodes arranged to face each other on a first main surface of the insulating substrate along a pair of opposing sides of the insulating substrate in a plan view, a plurality of terminal electrodes arranged to face each other on a second main surface of the insulating substrate along the pair of opposing sides of the insulating substrate in a perspective plan view, and an inner metal layer arranged inside the insulating substrate and extending in a direction perpendicular to the pair of opposing sides of the insulating substrate in a perspective plan view.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 30, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Michio Imayoshi, Yousuke Moriyama
  • Patent number: 10684734
    Abstract: A transparent high-conductivity layer for providing electrostatic feedback to a user of an electronic device. The transparent high-conductivity layer is positioned over a capacitive input sensor and has a resistivity sufficiently high to prevent interference with the capacitive input sensor. As one example, the transparent high-conductivity layer can be formed from a layer of geometrically-separated regions of high-conductivity material. The average distance between geometrically-separated regions can substantially define the resistivity of the transparent high-conductivity layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 16, 2020
    Assignee: Apple Inc.
    Inventors: Alan Kleiman-Schwarsctein, Senem E. Emgin, Terrence L. Van Ausdall, Xianwei Zhao, Yuxi Zhao, Soyoung Kim
  • Patent number: 10679961
    Abstract: The invention provides a circuit pin positioning structure, a fabrication method of soldered circuit elements and a method of forming circuit pins of a stacked package, applicable to a semiconductor package structure. A positioning rack and a plurality of conductor elements are used. A plurality of positioning holes are provided on a bottom surface of the positioning rack to form a conductor positioning area, and an operational portion is formed on an opposing surface away from the conductor positioning area, for being mounted with pick and place equipment. The conductor elements are positioned in the positioning holes. When the pick and place equipment loads and moves the positioning rack to preformed circuit contacts of the stacked package, the conductor elements are soldered to the preformed circuit contacts and then the positioning rack is removed.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 9, 2020
    Assignee: TARNG YU ENTERPRISE CO., LTD.
    Inventors: Tsung-Chi Chen, Mu-Jung Huang
  • Patent number: 10672729
    Abstract: A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Ting-Ting Kuo, Yu-Chih Huang, Chih-Wei Lin, Hsiu-Jen Lin, Chih-Hua Chen, Ming-Da Cheng, Ching-Hua Hsieh, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 10672722
    Abstract: Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: June 2, 2020
    Assignee: DAI NIPPON PRINTING Co., Ltd.
    Inventors: Ryohei Kasai, Tsuyoshi Tsunoda, Yuichi Yamamoto, Shuji Sagara, Masaya Tanaka
  • Patent number: 10667391
    Abstract: A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. Each build-up layer includes a first insulating layer including reinforcing material, a second resin insulating layer not containing reinforcing material, a first via conductor through the first insulating layer, and a second via conductor through the second insulating layer such that the top diameter of the first via conductor is substantially equal to the top diameter of the second via conductor and that the bottom diameter of the first via conductor is smaller than the bottom diameter of the second via conductor. The conductor layer on the first insulating layer includes a metal foil, a seed layer and an electrolytic plating film. The conductor layer on the second insulating-layer includes a seed layer and an electrolytic plating film and has thickness substantially equal to thickness of the conductor layer on the first insulating-layer.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 26, 2020
    Assignee: IBIDEN CO., LTD.
    Inventors: Naohito Ishiguro, Takamitsu Hattori
  • Patent number: 10655209
    Abstract: There is provided an inexpensive electromagnetic shield that can achieve exceptional shielding and display visibility characteristics, and provide high environmental resistance as necessary. In an electromagnetic shield (1), an intermediate layer (3) is formed on a glass substrate (2) comprising soda lime glass, an electroconductive layer (4) of Al is formed thereon, and openings (5) are formed by wet etching on the intermediate layer (3) and the electroconductive layer (4) after these layers have been formed by sputtering or vacuum deposition. Furthermore, an ITO layer (6) is formed on the entire glass surface including the intermediate layer (3) and the electroconductive layer (4) after the openings (5) are formed. In this configuration, the intermediate layer (3) comprises a mixture of at least one metal selected from chromium, molybdenum, and tungsten, and at least one oxide selected from oxides of silicon, oxides of aluminum, and oxides of titanium.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 19, 2020
    Assignees: NORITAKE CO., LIMITED, NORITAKE ITRON CORPORATION
    Inventors: Hitoshi Tsuji, Tadami Maeda, Isamu Kanda
  • Patent number: 10658655
    Abstract: Disclosed is a copper foil including a copper layer having a matte surface and a shiny surface, wherein the copper foil has a first surface of a direction of the matte surface of the copper layer and a second surface of a direction of the shiny surface of the copper layer, wherein a dynamic friction coefficient of the first surface is designated by ?k1 and a dynamic friction coefficient of the second surface is designated by ?k2. A ratio of three-dimensional surface area to two-dimensional surface area of the first surface is designated by Fs1, a ratio of three-dimensional surface area to two-dimensional surface area of the second surface is designated by Fs2.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 19, 2020
    Assignee: KCF TECHNOLOGIES CO., LTD.
    Inventors: Young Wook Chae, Young Hyun Kim, Shan Hua Jin
  • Patent number: 10631448
    Abstract: Provided is a portable electronic device with an embedded electric shock protection function. A portable electronic device with an embedded electric shock protection function according to an exemplary embodiment of the present invention comprises: a circuit board; a camera module mounted on the circuit board; a conductive cover disposed to cover a part of an upper side of the camera module; a conductive connecting part mounted on the circuit board and configured to come into electrical contact with the conductive cover; and an electric shock protection element mounted on the circuit board to be connected in series to the conductive connecting part and configured to pass static electricity introduced from the conductive cover and block a leakage current of an external power source introduced into a ground of the circuit board.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 21, 2020
    Assignee: AMOTECH CO., LTD.
    Inventors: Jae Su Ryu, Byung Guk Lim, Kyu Hwan Park, Jun-Suh Yu
  • Patent number: 10600838
    Abstract: There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: March 24, 2020
    Assignee: SONY CORPORATION
    Inventors: Satoru Wakiyama, Naoki Jyo, Kan Shimizu, Toshihiko Hayashi, Takuya Nakamura
  • Patent number: 10577515
    Abstract: A dielectric ink composition includes at least one (meth)acrylate compound selected from the group consisting of (meth)acrylate monomers, (meth)acrylate oligomers and combinations thereof; a sensitizing photoinitiator; an amine synergist photoinitiator; and a phosphine oxide photoinitiator. A device including a dielectric layer formed by printing the dielectric ink composition described herein is also disclosed.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 3, 2020
    Assignee: XEROX CORPORATION
    Inventors: Naveen Chopra, Sarah J. Vella, Biby Esther Abraham, Cuong Vong
  • Patent number: 10573610
    Abstract: Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu++ to Cu. Metal traces are formed in trace channels within the first layer of catalytic adhesive. The trace channels extend below a surface of the first layer of the catalytic material. The trace metals traces are also in contact with integrated circuit pads on the surface of the wafer.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: February 25, 2020
    Assignee: CATLAM, LLC
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Patent number: 10575401
    Abstract: A dielectric composite is provided. The dielectric composite includes: at least one first dielectric layer; and at least one second dielectric layer, wherein the first dielectric layer has a thermal coefficient of dielectric constant (TCDk) not higher than ?150 ppm/° C., and the second dielectric layer has a TCDK not lower than 50 ppm/° C.; and the dielectric composite has a dielectric constant (Dk) not lower than 4, and a TCDk ranging from 0 to ?150 ppm/° C.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 25, 2020
    Assignee: TAIWAN UNION TECHNOLOGY CORPORATION
    Inventors: Shur-Fen Liu, Chin-Hsien Hung, Wei-Jung Yang, Chang-Chih Liu
  • Patent number: 10568205
    Abstract: A ceramic and polymer composite including: a first continuous phase comprising a sintered porous ceramic having a solid volume of from 50 to 85 vol % and a porosity or a porous void space of from 50 to 15 vol %, based on the total volume of the composite; and a second continuous polymer phase situated in the porous void space of the sintered porous ceramic. Also disclosed is a composite article, a method of making the composite, and a method of using the composite.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: February 18, 2020
    Assignee: Corning Incorporated
    Inventors: Weiguo Miao, Manuela Ocampo, Michael Lesley Sorensen, James William Zimmermann
  • Patent number: 10568233
    Abstract: A thermally conductive article including a polymeric layer comprising a nonwoven polymeric material. In particular, a flexible thermally conductive polymeric layer comprising an epoxy resin and a long-strand polymeric nonwoven material embedded in the epoxy resin. The polymeric nonwoven material may be heat stable at about 280 C.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 18, 2020
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Rui Yang, Hui Luo, Carl E. Fisher
  • Patent number: 10561025
    Abstract: A method of manufacturing a polymer printed circuit board contains steps of: A. providing a material layer consisting of polymer; B. forming circuit pattern on the material layer; C. depositing metal nanoparticles on the LIG of the circuit pattern so as to use as a metal seed; D. pressing the circuit pattern; and E. forming a metal layer on the LIG of the circuit pattern. In the step of B, the circuit pattern includes laser induced graphene, and the laser induced graphene is porous. Thereby, the circuit pattern is adhered on the material layer securely and has outstanding electric conductivity after being pressed in the step D.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: February 11, 2020
    Assignee: BGT MATERIALS LIMITED
    Inventors: Kuo-Hsin Chang, Jia-Cing Chen, We-Jei Ke, Jingyu Zhang, Chung-Ping Lai
  • Patent number: 10542626
    Abstract: A multilayer electronic component includes a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes and having first to sixth surfaces, the first and second internal electrodes being exposed through the third and fourth surfaces, respectively; first and second external electrodes including first and second connected portions respectively disposed on the third and fourth surfaces of the capacitor body and first and second band portions respectively extending from the first and second connected portions to portions of the first surface of the capacitor body, respectively; a first connection terminal disposed on the first band portion; and a second connection terminal disposed on the second band portion, wherein 0.05?A1/A1?0.504, where A1 is an area of the first or second connection terminal in a thickness-width direction, and A2 is an area of the first or second band portion in a width-length direction.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Yoon Kim, Kyung Hwa Yu, Man Su Byun, Dae Heon Jeong, Min Kyoung Cheon, Soo Hwan Son
  • Patent number: 10526252
    Abstract: A joined body according to the invention is a ceramic/aluminum joined body including: a ceramic member; and an aluminum member made of aluminum or an aluminum alloy, in which the ceramic member and the aluminum member are joined to each other, the ceramic member is formed of silicon nitride containing magnesium, and a joining layer in which magnesium is contained in an aluminum-silicon-oxygen-nitrogen compound is formed at a joining interface between the ceramic member and the aluminum member.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: January 7, 2020
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Nobuyuki Terasaki, Yoshiyuki Nagatomo
  • Patent number: 10510640
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes an insulating substrate, a semiconductor chip, a plate member, and a cooler. The insulating substrate includes insulating ceramics serving as an insulating plate, and conductive plates provided on opposite surfaces of the insulating ceramics. The semiconductor chip is provided on an upper surface of the insulating substrate. The plate member is bonded to a lower surface of the insulating substrate. The cooler is bonded to a lower surface of the plate member. At least one of bonding between a lower surface of the insulating substrate and the plate member and bonding between a lower surface of the plate member and the cooler is performed via a bonding member composed mainly of tin. Also, a cyclic stress of the plate member is smaller than a tensile strength of the bonding member.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: December 17, 2019
    Assignee: Miitsubishi Electric Corporation
    Inventors: Hiroshi Kobayashi, Shinnosuke Soda, Yohei Omoto, Komei Hayashi
  • Patent number: 10510489
    Abstract: A mounting structure includes a circuit board including one principal surface on which a multilayer capacitor is mounted. The circuit board includes a first insulating layer, and a second insulating layer having a Young's modulus smaller than that of the first insulating layer. The second insulating layer is closer to the one principal surface than the first insulating layer. A multilayer capacitor built-in substrate includes a circuit board, a multilayer capacitor on one principal surface of the circuit board, and a resin layer on the one principal surface of the circuit board and embedding the multilayer capacitor. The circuit board includes a first insulating layer, and a second insulating layer having a Young's modulus smaller than that of the first insulating layer. The second insulating layer is closer to the one principal surface than the first insulating layer.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 17, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tadateru Yamada, Isamu Fujimoto, Kazuo Hattori, Masaru Takahashi
  • Patent number: 10510486
    Abstract: A multilayer ceramic electronic component includes a multilayer body that includes a second main surface defining and functioning as a mounting surface. Outer electrodes include underlying electrode layers including a conductive metal and a glass component and conductive resin layers including a thermosetting resin and a metal component. The underlying electrode layers extend from first and second end surfaces onto at least the second main surface. The conductive resin layers extend onto the underlying electrode layers provided on the second main surface, portions of the second main surface, and portions of the underlying electrode layers provided on the first end surface and the second end surface and cover portions of the first and second end surfaces, the portions including areas corresponding to about 9% or more and about 82% or less of areas of the first and the second end surfaces.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 17, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Mayumi Yamada
  • Patent number: 10504652
    Abstract: An electronic component having excellent reliability includes a first lateral surface and two external electrodes on an outermost side in a length direction among three or more external electrodes on the first lateral surface that are thicker than the other external electrode. On a second lateral surface, two external electrodes that are located on the outermost side in the length direction among three or more external electrodes disposed on the second lateral surface are thicker than the other external electrode.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: December 10, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirotaka Nakazawa, Takashi Sawada
  • Patent number: 10503067
    Abstract: A photosensitive resin composition comprising (A) a silicone-modified polybenzoxazole resin and (B) a photoacid generator which is decomposed to generate an acid upon exposure to radiation of 190-500 nm is coated onto a substrate to form a thick coating, which is exposed to radiation, baked, and developed to form a pattern. The resin coating is capable of forming a fine pattern and has improved crack resistance and other film properties, and reliability.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 10, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hitoshi Maruyama, Kazunori Kondo, Hideyoshi Yanagisawa
  • Patent number: 10499491
    Abstract: An obfuscated radio frequency circuit may be manufactured to include a metallization layer, and a dielectric layer under the metallization layer. The dielectric layer may be made up of a plurality of dielectric substrates having different dielectric constants to obfuscate functions of the circuit.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 3, 2019
    Assignee: THE BOEING COMPANY
    Inventor: Robert Tilman Worl
  • Patent number: 10499506
    Abstract: A composite substrate that is composed of a resin layer including an interlayer connection metal conductor and multiple ceramic layers that each include interlayer connection metal conductor, such that the resin layer is interposed between the ceramic layers, and the interlayer connection metal conductor in the resin layer is integrated with the interlayer connection metal conductors in the ceramic layers.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 3, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masaaki Hanao, Tsuyoshi Katsube, Hiromichi Kawakami, Mitsuyoshi Nishide
  • Patent number: 10483194
    Abstract: The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 19, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Shih-Ping Hsu
  • Patent number: 10468183
    Abstract: An inductor includes a body including a coil, the coil including a plurality of coil patterns connected by a via, is disposed, wherein the via includes a first conductive layer and a second conductive layer, formed on the first conductive layer, and the second conductive layer includes a conductive powder and an organic material.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Se Woong Paeng, Soo Hyun Lyoo, Jong Seok Bae
  • Patent number: 10457842
    Abstract: The present invention relates to a curable composition and an adhesive film including the same, and provides a curable composition and an adhesive film which may prevent damage to an element from moisture contained in the composition, ionic substances, and other foreign substances, and effectively block electrochemical corrosion, thereby improving a lifespan and durability of an organic electronic device.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: October 29, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Yoon Gyung Cho, Hyun Jee Yoo, Seung Min Lee, Suk Ky Chang, Jung Sup Shim
  • Patent number: 10453888
    Abstract: In a semiconductor apparatus including: a semiconductor substrate in which a plurality of semiconductor elements are provided; a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided; a second semiconductor layer that is arranged between the semiconductor substrate and the first semiconductor layer; a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer; a second wiring structure that is arranged between the second semiconductor layer and the semiconductor substrate; and a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, widths of a plurality of through electrodes are different from each other.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 22, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masahiro Kobayashi
  • Patent number: 10448502
    Abstract: An electronic component includes a body including a dielectric material and internal electrodes embedded in the dielectric material; external electrodes connected to the internal electrodes and disposed on the body; a first substrate connected to the external electrodes and disposed on one side of the body; and a second substrate connected to the first substrate and disposed on one side of the first substrate. The first and second substrates have different Young's modulus.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Yoon Kim, Kyoung Jin Jun, Min Kyoung Cheon
  • Patent number: 10424561
    Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Islam A. Salama, Ram S. Viswanath, Robert L. Sankman, Babak Sabi, Sri Chaitra Jyotsna Chavali
  • Patent number: 10412788
    Abstract: Provided are a heating element, which includes: a transparent substance; a conductive heating line that is provided on at least one side of the transparent substance; bus bars that is electrically connected to the conductive heating line; and a power portion that is connected to the bus bars, wherein 30% or more of the entire area of the transparent substance has a conductive heating line pattern in which, when the straight line that intersects the conductive heating line is drawn, a ratio (distance distribution ratio) of standard deviation in respects to an average value of distances between adjacent intersection points of the straight line and the conductive heating line is 5% or more, and a method for manufacturing the same.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: September 10, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Hyeon Choi, Su-Jin Kim, Ji-Young Hwang, Seung-Tae Oh, Ki-Hwan Kim, Sang-Ki Chun, Young-Jun Hong, In-Seok Hwang, Dong-Wook Lee
  • Patent number: 10399295
    Abstract: A passive electrical article including a dielectric layer having a nonwoven material.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: September 3, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Rui Yang, Guoping Mao, Dipankar Ghosh, Ji-Hwa Lee, Seungbae Min, Justine A. Mooney
  • Patent number: 10385203
    Abstract: Provided is a highly versatile heat-curable resin composition for semiconductor encapsulation that exhibits a favorable water resistance and abradability when used to encapsulate a semiconductor device; and a superior fluidity and a small degree of warpage even when used to perform encapsulation on a large-sized wafer. The heat-curable resin composition for semiconductor encapsulation comprises: (A) a cyanate ester compound having not less than two cyanato groups in one molecule, and containing a particular cyanate ester compound that has a viscosity of not higher than 50 Pa·s; (B) a phenol curing agent containing a resorcinol-type phenolic resin; (C) a curing accelerator; (D) an inorganic filler surface-treated with a silane coupling agent; and (E) an ester compound.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 20, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Kazuaki Sumita, Tomoaki Nakamura, Naoyuki Kushihara
  • Patent number: 10386961
    Abstract: Disclosed is a touch window which includes a substrate; a plurality of sensing electrodes on the substrate; and an opening part between the sensing electrodes.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: August 20, 2019
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hyun Soo Kim, Chan Kyu Koo, Jun Sik Shin, Joon Hyuk Yang, In Seok Kang, Byung Youl Moon, Jun Phill Eom, June Roh, Dong Mug Seong
  • Patent number: 10373934
    Abstract: There is provided a semiconductor device and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a second wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: August 6, 2019
    Assignee: Sony Corporation
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Patent number: 10368440
    Abstract: A printed wiring board includes: a core substrate having a core layer, conductor layers on the core layer, and through-hole conductors; a first build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer; and a second build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer. Each of the conductor layers, inner side conductor layers, and outermost conductor layers has a metal foil, a seed layer and an electrolytic plating film, and that each inner side conductor layer has the smallest thickness among the conductor layers, inner side conductor layers and outermost conductor layers.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: July 30, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Toshihide Makino, Hidetoshi Noguchi
  • Patent number: 10368438
    Abstract: A printed wiring board includes a laminated base material including an insulating layer and a conductor layer formed on the insulating layer, and a solder resist layer laminated on the laminated material and including photosensitive resin. The resist layer has surface portion and portion in contact with the laminated material, the conductor layer has pattern including conductor pads in contact with the resist layer such that the pads are positioned in openings in the resist layer, and the resist layer satisfies a first condition that a chemical species derived from a photopolymerization initiator has concentration higher in the portion in contact with the laminated material than concentration in the surface portion and/or a second condition that the chemical species derived from the initiator in the portion in contact with the laminated material has photopolymerization initiating ability higher than a chemical species derived from a photopolymerization initiator in the surface portion.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: July 30, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroyuki Nishioka, Shinsuke Ishikawa
  • Patent number: 10362667
    Abstract: A circuit board is disclosed. In addition to insulating layers, the circuit board includes a structure for heat transfer that includes a first layer that is formed of graphite or graphene, a second layer that is formed of metallic material and disposed on one surface of the first layer, and a third layer that is formed of metallic material and disposed on the other surface of the first layer, and at least a portion of the structure for heat transfer is inserted into an insulation layer. Such a circuit board provides improved heat management. Also disclosed is a method of manufacturing the circuit board.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae-Hong Min, Myung-Sam Kang, Jung-Han Lee, Young-Gwan Ko
  • Patent number: 10355139
    Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Keerti Shukla, Fei Zhou, Somesh Peri
  • Patent number: 10342073
    Abstract: The invention relates to a connection arrangement for an electrically conductive contact between at least one electrical conductor (17) provided on a screen (16), in particular for a motor vehicle, and an electrical coupling element (18), wherein at least one contact point (20) between the coupling element (18) and the electrical conductor (17) is provided on a coupling point (15) for the at least one electrical conductor (17) and wherein the electrical coupling element (18) and the electrical conductor (17) are connected to each other by means of an electrically conductive compound (19), and wherein the at least one contact point (20) of the coupling point (15) is at least partially surrounded by a casting compound (24), and a method for producing such a connection arrangement (10).
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: July 2, 2019
    Inventor: Michael Schoen
  • Patent number: 10325842
    Abstract: A substrate for packaging a semiconductor device includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer. The first patterned conductive layer includes a first portion and a second portion. Each of the first portion and the second portion is embedded in the first dielectric layer and protrudes relative to the first surface of the first dielectric layer toward a direction away from the second surface of the first dielectric layer. A thickness of the first portion of the first patterned conductive layer is greater than a thickness of the second portion of the first patterned conductive layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 18, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Cheng Lee, Yuan-Chang Su
  • Patent number: 10316187
    Abstract: A resin composition of the present disclosure contains an ingredient (A) that is a polyphenylene ether whose hydroxyl group bonded to a terminal of a main chain is modified with an ethylenically unsaturated compound, an ingredient (B) that is an olefin resin containing a hydroxyl group or carboxyl group, an ingredient (C) that is at least one kind selected from among triallyl isocyanurate and triallyl cyanurate, and an ingredient (D) that is an organic peroxide.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: June 11, 2019
    Assignee: KYOCERA CORPORATION
    Inventor: Chie Chikara
  • Patent number: 10306769
    Abstract: A wiring board includes an insulating layer made of an insulating resin containing inorganic insulating particles, a groove positioned in a surface of the insulating layer and including a wall surface being perpendicular to the surface of the insulating layer, and a wiring conductor filled in the groove, wherein a cross-section of the insulating resin and cross-sections of the inorganic insulating particles are exposed at the wall surface in flush with each other.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 28, 2019
    Assignee: KYOCERA CORPORATION
    Inventors: Masaaki Harazono, Takayuki Umemoto
  • Patent number: 10292279
    Abstract: A disconnect cavity is formed within a PCB, where the disconnect cavity is electrically disconnected from a PCB landing layer. The disconnect cavity is formed using a plating resist process which does not require low flow prepreg nor selective copper etching. Plating resist is printed on a core structure selectively positioned within a PCB stack-up. The volume occupied by the plating resist forms a subsequently formed disconnect cavity. After lamination of the PCB stack-up, depth control milling, drilling and electroless copper plating are performed, followed by a plating resist stripping process to substantially remove the plating resist and all electroless copper plated to the plating resist, thereby forming the disconnect cavity. In a subsequent copper plating process, without electric connectivity copper cannot be plated to the side walls and bottom surface of the disconnect cavity, resulting in the disconnect cavity wall being electrically disconnected from the PCB landing layer.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: May 14, 2019
    Assignee: Multek Technologies Limited
    Inventors: Jiawen Chen, Pui Yin Yu