Abstract: A redundant part of a plated through hole that is formed in a printed wiring board is removed by a back drilling method; a penetration hole is filled entirely with a curable resin composition for hole filling; the curable resin composition is initially heated at a temperature less than 100° C. so that a curing rate of the curable resin composition may be 60% to 85%; and the curable resin composition is subsequently heated at a temperature 130° C. to 200° C. so that the curable resin composition may be cured completely, where the curable resin composition contains 1 part by mass to 200 parts by mass of a curing agent with respect to 100 parts by mass of liquid epoxy resin, and contains no solvent.

Abstract: A substrate structure, a semiconductor package and a manufacturing method of semiconductor package are provided. The substrate structure comprises a conductive structure, an electrical component, a package body and a ring-shaped conductive structure. The conductive structure comprises a first conductive layer and a second conductive layer. The first conductive layer has a lower surface. The second conductive layer and the electrical component are formed on the lower surface of the first conductive layer. The package body encapsulates the conductive structure and the electrical component and has an upper surface. The ring-shaped conductive structure surrounds the conductive structure and the electrical component and is disposed at the edge of the upper surface of the package body to expose the conductive structure.

Abstract: A power module substrate includes an insulating layer, a circuit layer that is formed on a first surface of the insulating layer, and a metal layer that is formed on a second surface of the insulating layer, in which a first base layer is laminated on a surface of the metal layer on the opposite side of the surface to which the insulating layer is provided, and the first base layer has: a first glass layer that is formed at the interface with the metal layer; and a first Ag layer that is laminated on the first glass layer.

Abstract: A wiring board (3) according to an embodiment of the present invention includes an inorganic insulating layer (11A); a first resin layer (12A) on one main surface of the inorganic insulating layer (11A); a second resin layer (13A) on another main surface of the inorganic insulating layer (11A); and a conductive layer (8) partially on one main surface of the second resin layer (13A), the one main surface being on an opposite side to the inorganic insulating layer (11A). The inorganic insulating layer (11A) includes a plurality of first inorganic insulating particles (14) which are bound to each other at a part of each of the first inorganic insulating particles and gaps (G) surrounded by the plurality of first inorganic insulating particles (14). A part of the first resin layer (12A) and a part of the second resin layer (13A) are located inside the gaps (G).

Abstract: Resin infused composite parts are fabricated using a caul sheet having perforations therein for optimizing the flow of resin through the parts. The method allows for a simplified tooling and consumable arrangement for complex parts while achieving a smooth, aerodynamic caul-side or bag-side finish. The component may be placed in direct contact with a tool, and the caul sheet may be placed in direct contact with the component thereby eliminating the necessity for consumables between these items.

Abstract: An electronic device module includes a metallic casing having at least one boss formed therein, an electronic device unit placed inside the casing, connector terminals for external device connection electrically connected to the electronic device unit, and a metallic ground shell disposed so as to surround the connector terminals, having a front surface covered with a metal coated layer and including at least one boss insertion portion formed, a head of the at least one boss inserted into the at least one boss insertion portion and the coated layer positioned on a periphery of the corresponding at least one boss insertion portion being welded to each other to electrically connect and fix the ground shell to the casing.

Abstract: A ceramic electronic component includes a rectangular or substantially rectangular parallelepiped shaped laminate in which a ceramic layer and an internal electrode are alternately laminated and an external electrode provided on a portion of a surface of the laminate and electrically connected to the internal electrode. The external electrode includes an inner external electrode covering a portion of the surface of the laminate and including a mixture of a resin component and a metal component and an outer external electrode covering the inner external electrode and including a metal component.

Abstract: When laminating two resin films so that sides where the conductive patterns are not formed face each other, and when laminating other resin films so that sides where the conductive patterns are formed and the sides where the conductive patterns are not formed to face each other, a plurality of resin films each of which has the same resin thickness are used for the other resin films, and two resin films having a sum of resin thickness that is the same as the resin thickness of the other single resin film are used for the two resin films. Accordingly, dielectric thicknesses between the conductive patterns formed in the adjoining resin films can be made even so that an impedance can be calculated easily, and it becomes possible to ease the circuit design.

Abstract: Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.

Abstract: A resin composition is provided. The resin composition includes a thermosetting resin component and a filler, wherein the thermosetting resin component has a dissipation factor (Df) of no more than 0.006 at 1 GHz, the filler is a ceramic powder obtained through a sintering process at a temperature ranging from 1300° C. to less than 1400° C., and the amount of the filler is 10 parts by weight to 600 parts by weight per 100 parts by weight of the thermosetting resin component.

Abstract: The invention relates to a method for determining at least one property of a joint, such as a joint (112, 114, 116-119, 180) of a manipulator (110), wherein said joint is configured to be driven by at least one actuator, the actuator being configured to drive said joint (112, 114, 116-119, 180) via a drivetrain. The method comprises: clamping (200) said joint such that motion of the joint becomes constrained, and actuating (210) said drivetrain while monitoring at least one quantity associated with a torque of said actuator and at least one quantity associated with the actuator position in order to determine (220) at least one output value of said actuator, said output value corresponding to at least one joint position and determining (230) the at least one property of the joint based on said at least one output value. The invention further relates to a system for determining the at least one property of a joint.

Abstract: A method of curing a thermosetting resin composition according to the present invention includes mixing a thermosetting resin containing a benzoxazine compound and a curing accelerator containing a triazine thiol compound to prepare a thermosetting resin composition, and heating this thermosetting resin composition to be cured.

Abstract: A component built-in board mounting body has a component built-in board mounted on a mounting board, the component built-in board being configured having stacked therein a plurality of printed wiring bases that each have a wiring pattern and a via formed on/in a resin base thereof, and having an electronic component built in thereto, wherein the component built-in board has at least a portion of the plurality of printed wiring bases including thermal wiring in the wiring pattern and including a thermal via in the via, and is mounted on the mounting board via a bump formed on a surface layer of the component built-in board, and a surface on an opposite side to an electrode formation surface of the built in electronic component is connected to the bump via the thermal via and the thermal wiring, and is thermally connected to the mounting board via the bump.

Abstract: Provided is a semiconductor encapsulation resin composition exhibiting an insignificant heat decomposition when left under a high temperature of 200 to 250° C. for a long period of time; and a superior reliability and adhesion to a Cu LF and Ag plating under a high-temperature and high-humidity environment. The composition comprises: (A) a cyanate ester compound having not less than two cyanato groups in one molecule; (B) a phenolic compound; (C) at least one epoxy resin; (D) a copolymer obtained by a hydrosilylation reaction of an alkenyl group-containing epoxy compound and an organopolysiloxane; and (E) at least one compound selected from a tetraphenylborate salt of a tetra-substituted phosphonium compound and a tetraphenylborate salt. A molar ratio of phenolic hydroxyl groups in (B) to cyanato groups in (A) is 0.08 to 0.25, and a molar ratio of epoxy groups in (C) and (D) to cyanato groups in (A) is 0.04 to 0.25.

Abstract: A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic core material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material.

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Abstract: An electronic device (e.g., computing device, all-in-one computing system, stand-alone display, etc.) having a liquid crystal display (LCD) panel, and a light guide panel (LGP) having a first zone and a second zone physically segmented from each other. The electronic device includes a first light bar associated with the first zone; and a second light bar associated with the second zone. The LGP may include more than two zones.

Abstract: A ceramic electronic component includes a rectangular or substantially rectangular parallelepiped-shaped stack in which a ceramic layer and an internal electrode are alternately stacked and an external electrode provided on a portion of a surface of the stack and electrically connected to the internal electrode. The external electrode includes an inner external electrode covering a portion of the surface of the stack and including a mixture of a resin component and a metal component and an outer external electrode covering the inner external electrode and including a metal component. A volume occupied by the resin component in the inner external electrode is within a prescribed range.

Abstract: A manufacturing of a package carrier includes the following steps. Two base metal layers are bonded together. Two supporting layers are laminated onto the base metal layers respectively. Two release metal films are disposed on the supporting layers respectively. Each release metal film includes a first metal film and a second metal film separable from each other. Two first patterned metal layers are formed on the release metal films respectively. Each first patterned metal layer includes a pad pattern. Two dielectric layers are formed on the release metal films respectively and cover the corresponding first patterned metal layers. Each dielectric layer has a conductive via connecting to the corresponding pad pattern. Two second patterned metal layers are formed on the dielectric layers respectively. Each second patterned metal layer at least covers the conductive via. The base metal layers are separated from each other to form two independent package carriers.

Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.

Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer, a second insulation layer formed on the first insulation layer and the first conductive patterns and having an opening portion, a wiring structure accommodated in the opening portion of the second insulation layer and including an insulation layer and conductive patterns on the insulation layer, second conductive patterns formed on the second insulation layer; and a via conductor formed in the second insulation layer and connecting one of the first conductive patterns and one of the second conductive patterns.

Abstract: The electronic component of this invention includes a multilayer ceramic substrate 14 composed of a plurality of ceramic layers 12. A wiring electrode 16 and a planar electrode 18 are formed on a ceramic layer 12, which is an insulating layer. The planar electrode 18 is formed so as to be spaced apart from the wiring electrode 16 at the certain interval. An edge portion 22 is formed in a region of the planar electrode 18 adjacent to and spaced apart from the wiring electrode 16 at a certain interval. A central portion 20 is formed in a region of the planar electrode 18 other than the edge portion 22. At least the composition of the central portion 20 is different from the composition of the wiring electrode 16, and the composition of the edge portion 22 is the same as the composition of the wiring electrode 16.

Abstract: A light emitting diode load board includes a substrate, a first dielectric layer, a second dielectric layer and a first conductive pad and a second conductive pad. The second dielectric layer includes a first structure part, a second structure part and a third structure part. The first dielectric layer is disposed on the substrate. The first structure part is disposed on the first dielectric layer and has a first sidewall. The second structure part is disposed on the first structure part and has a second sidewall. The third structure part is disposed on the second structure part and has N sidewalls. The second sidewall is more prominent than the first sidewall. The first sidewall, the second sidewall and the N sidewalls define the first etched part, and the part of the first dielectric layer is exposed from the first etched part. The first conductive pad is disposed in the first etched part.

Abstract: A liquid composition containing a liquid crystalline polyester, a solvent, and a boron nitride having a volume average particle diameter of not less than 10 ?m and not more than 80 ?m, wherein the amount of the boron nitride is 30 to 90% by volume based on the total amount of the liquid crystalline polyester and the boron nitride.

Abstract: A wiring board includes a core structure including a core substrate, and a buildup structure formed on the core structure and including an interlayer insulating layer and a conductive layer. The interlayer insulating layer does not contain inorganic fiber and includes a resin and an inorganic filler, and the conductive layer is formed on the interlayer insulating layer such that the inorganic filler in the interlayer insulating layer is not in contact with the conductive layer.

Abstract: A wiring substrate includes an insulating layer and a pad exposed from the insulating layer. An outermost surface of the insulating layer is modified to have a hydrophobic property by being stamped with silicone.

Abstract: A semiconductor device includes a semiconductor element, a lead, and a wire including a first bonding portion bonded to the semiconductor element and a second bonding portion bonded to the lead. The semiconductor element includes a first bonding surface which faces to a first side in a first direction and to which the first bonding portion is bonded. The lead includes a second bonding surface and a third bonding surface both facing to the first side in the first direction and forming an angle larger than 180° on the first side in the first direction. The semiconductor device further includes a ball bump extending onto both the second bonding surface and the third bonding surface. The second bonding portion is bonded to the lead via the ball bump.

Abstract: A wiring board includes a first wiring layer, a first insulating layer, first via wirings, connection terminals and a protection layer. The first insulating layer is formed with through holes. The first via wirings are formed in the through holes. The connection terminals are electrically connected to the first wiring layer through the first via wirings. The connection terminals protrude upward from the first insulating layer. The protection layer is made of insulating resin which contains photosensitive resin as a main component. The protection layer is formed on an upper surface of the first insulating layer. The protection layer includes first and second protection layers. The first protection layer surrounds the connection terminals. The second protection layer is separated from the first protection layer. The second protection layer is thinner than the first protection layer.

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract: A wiring substrate includes a core layer having a hole penetrating therethrough in a thickness direction thereof, and having a projecting part projecting from an inner wall of the hole toward an inner space of the hole, a plurality of electronic components disposed in the hole and arranged side by side at a spaced interval in a plan view, the electronic components having side portions thereof, the side portions being engaged with the projecting part, and a resin layer filling the hole and supporting the electronic components.

Abstract: An interposer for establishing a vertical connection between semiconductor packages includes an electrically insulating substrate having a first main side and a second main side opposite the first main side, a plurality of first electrical conductors at the first main side of the substrate, a plurality of second electrical conductors at the second main side of the substrate, and a programmable connection matrix at one or both main sides of the substrate. The programmable connection matrix includes programmable junctions configured to open or close electrical connections between different ones of the first electrical conductors and different ones of the second electrical conductors upon programming of the junctions.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.

Abstract: An insulating adhesive by having a plateable layer which is comprised of a plateable layer-use resin composition which contains a polar group-containing alicyclic olefin polymer (A1) and a curing agent (A2) and an adhesive layer which is comprised of an adhesive layer-use resin composition which contains a polar group-containing alicyclic olefin polymer (B1), a curing agent (B2), and an inorganic filler (B3), wherein a ratio of content of the polar group-containing alicyclic olefin polymer (A1) to the solid content as a whole which is contained in the plateable layer is 50 to 90 wt %, and a ratio of content of the polar group-containing alicyclic olefin polymer (B1) to the solid content as a whole which is contained in the adhesive layer is 1 to 30 wt % and a ratio of content of the inorganic filler (B3) is 50 to 90 wt % is provided.

Abstract: An apparatus has a permittivity attenuation layer interposed between a substrate and a first conductive trace, wherein the permittivity attenuation layer comprises a resin matrix containing functionalized carbon nanomaterial, such as functionalized single-wall carbon nanotubes (f-SWNTs). In some embodiments, a design structure for designing, manufacturing, or testing the apparatus is tangibly embodied in a machine readable medium. In some embodiments, the apparatus comprises an enhanced laminate core for use in a printed wiring board (PWB) that contains a differential pair having an inner-leg conductive trace and an outer-leg conductive trace. A permittivity attenuation layer is interposed between the inner-leg conductive trace and a laminate core, wherein the loading level of f-SWNTs in the permittivity attenuation layer is selected to attenuate the permittivity of the inner-leg conductive trace to match the permittivity of the outer-leg conductive trace.

Abstract: A manufacturing method for a piezoelectric resonator device includes sequential steps of: (i) laminating a metal film constituted by at least two types of metals on at least one of a substrate of a joining region of a piezoelectric resonator plate, a substrate of a region of an upper lid member, and a substrate of a region of a lower lid member; (ii) promoting metal diffusion inside the metal film by heat processing; and (iii) roughening a surface of the substrate of the at least one of the piezoelectric resonator plate, the upper lid member, and the lower lid member by performing wet etching with an etchant caused to penetrate into the metal film and thereby forming a large number of micropores in the surface of the substrate of the at least one of the piezoelectric resonator plate, the upper lid member, and the lower lid member.

Abstract: A circuit board includes a multi-layer structure, a ceramic member, and a first conductive layer. The multi-layer structure has a thru-hole penetrating two opposite board surfaces thereof. The multi-layer structure includes a plurality of stacked plates and an adhesive connecting any two stacked plates. The ceramic member is arranged in the thru-hole of the multi-layer structure, and a surface of the ceramic member is approximately coplanar with a board surface of the multi-layer structure. The adhesive is adhered on the lateral surface of the ceramic member for connecting the ceramic member and the plates. The first conductive layer is formed on the board surface of the multi-layer structure and the surface of the ceramic member. Thus, the circuit board of the instant disclosure can be applied to a high-heat-generating product and is different from a conventional circuit board.

Abstract: There is provided a wiring substrate including: a core substrate including: a first core substrate including: a plate-shaped first glass substrate; and a first through electrode formed through the first glass substrate; a second core substrate including: a plate-shaped second glass substrate; and a second through electrode formed through the second glass substrate, wherein a diameter of the second through electrode is different from that of the first through electrode; and an insulating member encapsulating the first and second core substrates, and a wiring layer formed on at least one surface of the core substrate. The first and second core substrates are arranged to be separated from each other when viewed from a top.

Abstract: There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.

Abstract: In a particular embodiment, a method of manufacturing a printed circuit board (‘PCB’) with reduced dielectric loss includes fabricating conductive traces disposed upon layers of dielectric material; and fabricating the layers of dielectric material, including core layers and prepreg layers, with one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB. In the particular embodiment, the conductive traces are disposed upon layers of the dielectric material orthogonally with respect to one another and the pockets of air are aligned at an angle of 45 degrees with respect to the conductive traces.

Abstract: A photosensitive composition, suitable for a hardened film capable of sufficiently blocking light in the visible range and sufficiently transmitting light in the near infrared region, is provided. The photosensitive composition contains a colorant, a compound having an ethylenic unsaturated group, a photopolymerization initiator and a solvent. The colorant contains (A1) to (A3); (A1) a colorant of the following formula (1): (A2) a blue colorant, a green colorant, or both, and (A3) a yellow colorant, a red colorant, or both. R1 and R2 is a hydrogen atom, a hydroxyl group, a methoxy group or an acetyl group. R3 and R4 is a phenylene group or a direct bond. R5 and R6 is a direct bond or an alkanediyl group having 1 to 10 carbon atoms, with the proviso that R3 and R5 are not simultaneously direct bonds, and R4 and R6 are not simultaneously direct bonds.

Abstract: A multilayer wiring board with a built-in electronic component includes a substrate, a conductor layer formed on surface of the substrate, one or more electronic components positioned in a cavity formed through the substrate, an insulating layer formed on the substrate such that the insulating layer is formed on the component in the cavity, and a wiring layer formed on the insulating layer. The conductor layer has an opening formed such that the cavity is formed in the opening of the conductor layer and that the conductor layer has a first side in the opening and a second side in the opening on the opposite side across the cavity, and the cavity is formed in the opening of the conductor layer such that width between the cavity and the first side of the conductor layer is greater than width between the cavity and the second side of the conductor layer.

Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.

Abstract: Flexible electronic structure and methods for fabricating flexible electronic structures are provided. An example method includes applying a first layer to a substrate, creating a plurality of vias through the first layer to the substrate, and applying a second polymer layer to the first layer such that the second polymer forms anchors contacting at least a portion of the substrate. At least one electronic device layer is disposed on a portion of the second polymer layer. At least one trench is formed through the second polymer layer to expose at least a portion of the first layer. At least a portion of the first layer is removed by exposing the structure to a selective etchant to providing a flexible electronic structure that is in contact with the substrate. The electronic structure can be released from the substrate.

Abstract: An object of the present invention is to provide a curable resin composition capable of giving a cured product which is excellent in mechanical properties (such as elastic modulus) and toughness. The curable resin composition contains 60 to 99 parts by mass of an unsaturated ester resin, 0.5 to 20 parts by mass of an epoxy resin, and 0.1 to 20 parts by mass of crosslinked rubber particles having a number average particle diameter of 20 nm to 600 nm. The crosslinked rubber particles are obtained by polymerizing a vinyl monomer in the presence of one or more rubber polymers selected from the group consisting of a butadiene rubber, a butadiene-styrene rubber, a butadiene-butyl acrylate rubber, a butyl acrylate rubber and an organosiloxane rubber.

Abstract: Thin film electronic devices (or stacks integrated with a substrate) that include a permeation barrier formed of a thin layer of metal that provides a light transmitting and electrically conductive layer, wherein the electrical conductive layer is formed on a surface of the substrate or device layer such as a transparent conducting material layer with pin holes or defects caused by manufacturing and the thin layer of metal is deposited on the conductive layer and formed from a self-healing metal that forms self-terminating oxides. A permeation plug or block is formed in or adjacent to the thin film of metal at or proximate to the pin holes to block further permeation of contaminants through the pin holes.

Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.

Abstract: An electrical element can be attached and electrically connected to a substrate by a conductive adhesive material. The conductive adhesive material can electrically connect the electrical element to a terminal or other electrical conductor on the substrate. The conductive adhesive material can be cured by directing a flow of heated gas onto the material or by heating the material through a support structure on which the substrate is located. A non-conductive adhesive material can attach the electrical element to the substrate with a greater adhesive strength than the conductive adhesive. The non-conductive adhesive material can also be cured by directing a flow of heated gas onto the material or by heating the material through the support structure on which the substrate is located. The non-conductive adhesive material can cover the conductive adhesive material.

Abstract: A high dielectric nanosheet laminate is produced by laminating nanosheets, each of which has a thickness of 10 nm or less and is formed of an oxide that has a perovskite structure wherein at least four NbO6 octahedrons, TaO6 octahedrons or TiO6 octahedrons are included in a unit lattice. Consequently, the high dielectric nanosheet laminate is capable of achieving a high dielectric constant and a satisfactory insulation property, which are preferable for high dielectric nanosheet multilayer capacitors or the like, at the same time even if formed very thin.

Abstract: The circuit board includes a ceramic sintered body and a metal wiring layer provided on at least one primary surface thereof with a glass layer interposed therebetween, and when the cross section of the circuit board perpendicular to the primary surface of the ceramic sintered body is viewed, the ratio of the length of an interface between the glass layer and the metal wiring layer to a length of the glass layer in a direction along the primary surface is 1.25 to 1.80.

Abstract: An electrode, a biosignal detecting device and a method of measuring a biosignal are provided. The electrode includes an ion conductive member configured to be attached to a body surface, a nonconductive member including a through hole and disposed on the ion conductive member, a conductive member disposed on the nonconductive member, and a nonpolarizable conductive member configured to electrically couple the ion conductive member to the conductive member.