Abstract: Provided are a heating element, which includes: a transparent substance; a conductive heating line that is provided on at least one side of the transparent substance; bus bars that is electrically connected to the conductive heating line; and a power portion that is connected to the bus bars, wherein 30% or more of the entire area of the transparent substance has a conductive heating line pattern in which, when the straight line that intersects the conductive heating line is drawn, a ratio (distance distribution ratio) of standard deviation in respects to an average value of distances between adjacent intersection points of the straight line and the conductive heating line is 5% or more, and a method for manufacturing the same.

Abstract: A passive electrical article including a dielectric layer having a nonwoven material.

Abstract: Disclosed is a touch window which includes a substrate; a plurality of sensing electrodes on the substrate; and an opening part between the sensing electrodes.

Abstract: Provided is a highly versatile heat-curable resin composition for semiconductor encapsulation that exhibits a favorable water resistance and abradability when used to encapsulate a semiconductor device; and a superior fluidity and a small degree of warpage even when used to perform encapsulation on a large-sized wafer. The heat-curable resin composition for semiconductor encapsulation comprises: (A) a cyanate ester compound having not less than two cyanato groups in one molecule, and containing a particular cyanate ester compound that has a viscosity of not higher than 50 Pa·s; (B) a phenol curing agent containing a resorcinol-type phenolic resin; (C) a curing accelerator; (D) an inorganic filler surface-treated with a silane coupling agent; and (E) an ester compound.

Abstract: There is provided a semiconductor device and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a second wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.

Abstract: A printed wiring board includes a laminated base material including an insulating layer and a conductor layer formed on the insulating layer, and a solder resist layer laminated on the laminated material and including photosensitive resin. The resist layer has surface portion and portion in contact with the laminated material, the conductor layer has pattern including conductor pads in contact with the resist layer such that the pads are positioned in openings in the resist layer, and the resist layer satisfies a first condition that a chemical species derived from a photopolymerization initiator has concentration higher in the portion in contact with the laminated material than concentration in the surface portion and/or a second condition that the chemical species derived from the initiator in the portion in contact with the laminated material has photopolymerization initiating ability higher than a chemical species derived from a photopolymerization initiator in the surface portion.

Abstract: A printed wiring board includes: a core substrate having a core layer, conductor layers on the core layer, and through-hole conductors; a first build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer; and a second build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer. Each of the conductor layers, inner side conductor layers, and outermost conductor layers has a metal foil, a seed layer and an electrolytic plating film, and that each inner side conductor layer has the smallest thickness among the conductor layers, inner side conductor layers and outermost conductor layers.

Abstract: A circuit board is disclosed. In addition to insulating layers, the circuit board includes a structure for heat transfer that includes a first layer that is formed of graphite or graphene, a second layer that is formed of metallic material and disposed on one surface of the first layer, and a third layer that is formed of metallic material and disposed on the other surface of the first layer, and at least a portion of the structure for heat transfer is inserted into an insulation layer. Such a circuit board provides improved heat management. Also disclosed is a method of manufacturing the circuit board.

Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.

Abstract: The invention relates to a connection arrangement for an electrically conductive contact between at least one electrical conductor (17) provided on a screen (16), in particular for a motor vehicle, and an electrical coupling element (18), wherein at least one contact point (20) between the coupling element (18) and the electrical conductor (17) is provided on a coupling point (15) for the at least one electrical conductor (17) and wherein the electrical coupling element (18) and the electrical conductor (17) are connected to each other by means of an electrically conductive compound (19), and wherein the at least one contact point (20) of the coupling point (15) is at least partially surrounded by a casting compound (24), and a method for producing such a connection arrangement (10).

Abstract: A substrate for packaging a semiconductor device includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer. The first patterned conductive layer includes a first portion and a second portion. Each of the first portion and the second portion is embedded in the first dielectric layer and protrudes relative to the first surface of the first dielectric layer toward a direction away from the second surface of the first dielectric layer. A thickness of the first portion of the first patterned conductive layer is greater than a thickness of the second portion of the first patterned conductive layer.

Abstract: A resin composition of the present disclosure contains an ingredient (A) that is a polyphenylene ether whose hydroxyl group bonded to a terminal of a main chain is modified with an ethylenically unsaturated compound, an ingredient (B) that is an olefin resin containing a hydroxyl group or carboxyl group, an ingredient (C) that is at least one kind selected from among triallyl isocyanurate and triallyl cyanurate, and an ingredient (D) that is an organic peroxide.

Abstract: A wiring board includes an insulating layer made of an insulating resin containing inorganic insulating particles, a groove positioned in a surface of the insulating layer and including a wall surface being perpendicular to the surface of the insulating layer, and a wiring conductor filled in the groove, wherein a cross-section of the insulating resin and cross-sections of the inorganic insulating particles are exposed at the wall surface in flush with each other.

Abstract: A disconnect cavity is formed within a PCB, where the disconnect cavity is electrically disconnected from a PCB landing layer. The disconnect cavity is formed using a plating resist process which does not require low flow prepreg nor selective copper etching. Plating resist is printed on a core structure selectively positioned within a PCB stack-up. The volume occupied by the plating resist forms a subsequently formed disconnect cavity. After lamination of the PCB stack-up, depth control milling, drilling and electroless copper plating are performed, followed by a plating resist stripping process to substantially remove the plating resist and all electroless copper plated to the plating resist, thereby forming the disconnect cavity. In a subsequent copper plating process, without electric connectivity copper cannot be plated to the side walls and bottom surface of the disconnect cavity, resulting in the disconnect cavity wall being electrically disconnected from the PCB landing layer.

Abstract: A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers.

Abstract: A liquid solder resist composition contains a carboxyl group-containing resin (A), a thermosetting component (B), a photopolymerizable component (C), a photopolymerization initiator (D), and a coloring agent (E). The thermosetting component (B) contains a powdery epoxy compound (B11) represented by following formula (1), An amount of the epoxy compound (B11) with respect to a total amount of the carboxyl group-containing resin (A), the thermosetting component (B), and the photopolymerizable component (C) is within a range of 15 to 40 weight %.

Abstract: A power converter module includes a baseplate, a substrate on the baseplate, one or more silicon carbide switching components on the substrate, and a housing over the baseplate, the substrate, and the one or more silicon carbide switching components. The housing has a footprint less than 25 cm2. Including a baseplate in a power converter module with a footprint less than 25 cm2 runs counter to accepted design principles for silicon and silicon carbide-based power converter modules, but may improve performance of the power converter module and/or decrease the cost of the power converter module.

Abstract: This invention relates to a touch window. The touch window includes a substrate; a plurality of sensing electrodes on the substrate; and an opening part between the sensing electrodes. In addition, the touch window has an opening part formed between the electrode parts, so that the electrode parts may be prevented from being short-circuited with each other.

Abstract: A package-on-package semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between two both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, another semiconductor device is disposed over a top surface of the core base and is electrically coupled to the semiconductor device in the dielectric recess through a buildup circuitry under a bottom surface of the core base.

Abstract: A circuit subassembly, comprising a conductive layer, a dielectric layer is formed from a thermosetting composition, wherein the thermosetting composition comprises, based on the total weight of the thermosetting composition, a low polarity resin, a oxaphosphorinoxide-containing aromatic compound, and an protective adhesive layer disposed between the conductive layer and the dielectric layer, wherein the circuit subassembly has a UL-94 rating of at least V-0. Also disclosed is a composition for a bond ply and a circuit subassembly that further comprises such bond ply.

Abstract: A multilayer electronic component includes a body, first and second external electrodes, and first and second side parts. The body includes a multilayer structure in which first and second internal electrode patterns are alternately stacked and contains a dielectric material. The first and second side parts are disposed on outer surfaces of the body to face each other. The first and second external electrodes are disposed on outer surfaces of the body to face each other. The first internal electrode patterns are exposed to a third surface and a fifth surface of the body on which the first external electrode and the first side part are disposed, respectively. Additionally, the second internal electrode patterns are exposed to a fourth surface and a sixth surface of the body on which the second external electrode and the second side part are disposed, respectively.

Abstract: The objective of the present invention is to obtain a semiconductor resin composition having a sufficiently low coefficient of linear expansion of the cured product thereof and a uniform distribution of inorganic particles in the direction of film thickness of a produced semi-cured film thereof. The semiconductor resin composition, which contains (a) an epoxy compound, (b) inorganic particles, (c) a polyimide, and (d) a solvent, is characterized by further containing (e) rubber particles and by the fraction of the (b) inorganic particles in the weight of the total solid fraction resulting from subtracting the weight of the (d) solvent from the total weight of the semiconductor resin composition being 60-92 wt % inclusive.

Abstract: In the method for forming a protective coat on an electrode for a touch panel according to the invention, a photosensitive layer comprising a photosensitive resin composition containing a binder polymer having a carboxyl group and an acid value of 30 to 120 mgKOH/g, a photopolymerizable compound having at least three ethylenic unsaturated groups, and a photopolymerization initiator, is formed on a base material having an electrode for a touch panel, prescribed sections of the photosensitive layer are cured by irradiation with active light rays and then the sections other than the prescribed sections are removed, to form a protective coat comprising the cured sections of the photosensitive resin composition covering all or a portion of the electrode.

Abstract: A first signal line, a second signal line, a first line, and a second line are disposed in an identical direction on an identical layer. A distance between the first signal line and the second signal line is larger than a distance between the first signal line and the first line or larger than a distance between the second signal line and the second line.

Abstract: There is provided a resin composition that exhibits excellent heat resistance, heat conductivity, and water absorption. The resin composition comprises a cyanate ester resin (A) represented by formula (I), an epoxy resin (B), and an inorganic filler (C), the content of the inorganic filler (C) being 301 to 700 parts by weight based on 100 parts by weight in total of the cyanate ester resin (A) and the epoxy resin (B) wherein Rs each independently represent a hydrogen atom or a methyl group; and n is an integer of 1 to 50.

Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.

Abstract: A wiring substrate is manufactured by attaching an adhesive protective film to a metal-foiled laminate sheet, forming bottomed via holes by partially removing the film and an insulating film, filling conductive pastes into the holes, and peeling the film. A wiring substrate is manufactured by forming an adhesive protective layer so as to cover a patterned metal foil on a metal-foiled laminate sheet, forming bottomed step via holes by partially removing the layer and an insulating film, filling conductive pastes into the holes, and peeling off a protective film. The wiring substrate and the second wiring substrate are laminated in such a way that protruding parts of the pastes come into contact with respective protruding parts of the pastes.

Abstract: An electronic device includes a display panel configured to display an image, first electrodes provided on the display panel and arranged in parallel in a direction, second electrodes provided on the display panel and arranged in parallel in a direction crossing the first electrodes, an insulating layer provided between the first electrodes and the second electrodes, a controller configured to transmit driving signals to the first electrodes, and receive electrical signals from the second electrodes, touch detection areas and fingerprint-touch detection areas in which the first electrodes cross the second electrodes, and a protection film provided on the first electrodes and the second electrodes. The touch detection areas are arranged in a matrix of M rows and N columns, the fingerprint-touch detection areas are disposed at positions in the matrix, and each of the fingerprint-touch detection areas includes fingerprint detection pixels.

Abstract: A method of manufacturing an intermediate product for an interposer including a glass substrate having a plurality of through holes is provided. The method includes a step of forming a resin layer on a support substrate, and a step of forming a laminated body by adhering the glass substrate having the plurality of through holes on the resin layer. The glass substrate having the plurality of through holes has a thickness within a range of 0.05 mm to 0.3 mm.

Abstract: A flexible printed circuit board on which a first electronic component and a second electronic component are to be mounted adjacent to each other has a first land for soldering a terminal of the first electronic component on a side adjacent to the second electronic component, and a second land for soldering a terminal of the second electronic component on a side adjacent to the first electronic component. The first land and the second land are connected by a wire extending outside of an inter-land region that is an approximately belt-shaped region formed by connecting end portions in a width direction or end portions in a thickness direction of the first land and the second land in a straight line.

Abstract: A wiring substrate is provided with a surface wiring on at least one surface, a through hole which passes through the wiring substrate, and a through wiring which is formed in the through hole and is connected to a surface wiring, in which an inner surface of the through hole is a rough surface, and electric resistance of the through wiring is equal to or less than the electric resistance of the surface wiring.

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

Abstract: A ceramic electronic component includes a laminated body including ceramic layers and conductor layers stacked alternately; and first and second external electrodes provided on portions of the laminated body. Each of the first and second external electrodes includes a sintered metal layer provided on the laminated body, a conductive resin layer covering the sintered metal layer, and a plated layer covering the conductive resin layer. The maximum length of the sintered metal layer provided on the second principal surface is shorter than the maximum length of the sintered metal layer provided on each of the first and second side surfaces.

Abstract: A ceramic electronic component includes a laminated body including ceramic layers and conductor layers stacked alternately; and first and second external electrodes provided on portions of the laminated body. Each of the first and second external electrodes includes a sintered metal layer provided on the laminated body, a conductive resin layer covering the sintered metal layer, and a plated layer covering the conductive resin layer. The maximum length of the sintered metal layer provided on the second principal surface is shorter than the maximum length of the sintered metal layer provided on each of the first and second side surfaces.

Abstract: A wiring board includes: an inorganic insulating layer having a via hole formed so as to penetrate the inorganic insulating layer in a thickness direction thereof; a conductive layer disposed on the inorganic insulating layer; and a via conductor which adheres to an inner wall of the via hole and is connected with the conductive layer. The inorganic insulating layer includes a first section including a plurality of inorganic insulating particles partly connected to each other, and a resin portion located in gaps between the inorganic insulating particles, and a second section which is interposed between the first section and the via conductor, including a plurality of inorganic insulating particles partly connected to each other, and a conducting portion composed of part of the via conductor which is located in gaps between the inorganic insulating particles.

Abstract: A ceramic electronic component includes a laminated body including ceramic layers and conductor layers stacked alternately; and first and second external electrodes provided on portions of the laminated body. Each of the first and second external electrodes includes a sintered metal layer provided on the laminated body, a conductive resin layer covering the sintered metal layer, and a plated layer covering the conductive resin layer. The maximum length of the sintered metal layer provided on the second principal surface is shorter than the maximum length of the sintered metal layer provided on each of the first and second side surfaces.

Abstract: Circuit boards are designed and configured for mounting light emitting devices (LEDs), such as for LED light bulb and LED light tube applications, and are capable of passing a non-isolated, mains powered, electrical strength test.

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Abstract: A conductive film forming composition includes a fluorine atom-containing migration inhibitor and a metal particle, with the migration inhibitor including at least one selected from the group consisting of compounds represented by General Formulae (1) to (5), (22) and (23) as well as compounds having a group of General Formula (24) and a group of General Formula (25). The conductive film forming composition makes it possible to form a conductive film excellent in conductive characteristics and ion migration inhibiting function.

Abstract: A tool for supporting multilayer printed circuit boards during manufacture having a frame in which there is fixed a pretensed, non-electrically conductive fabric which has a thickness less than 0.1 mm and which can be accessed by its two faces. The tool allows the induction bonding of the layers at internal points of the bundle following a method in which the bundle is placed on the tool and at least one of the welding electrodes used in the welding operation is applied on the lower face of a fabric of the tool supporting the bundle. A machine especially suitable for putting the method into practice includes C-shaped magnetic cores, the arms of which are long enough to reach the internal points of the bundle.

Abstract: A ceramic electronic component includes a laminated body including ceramic layers and conductor layers stacked alternately; and first and second external electrodes provided on portions of the laminated body. Each of the first and second external electrodes includes a sintered metal layer provided on the laminated body, a conductive resin layer covering the sintered metal layer, and a plated layer covering the conductive resin layer. The maximum length of the sintered metal layer provided on the second principal surface is shorter than the maximum length of the sintered metal layer provided on each of the first and second side surfaces.

Abstract: A wiring substrate includes a core substrate and a cavity extending through the core substrate. The cavity has a planar shape that is rectangular, and includes corners and sides connecting the corners in a plan view. The wiring substrate also includes first through holes that extend through the core substrate and are spaced apart from the cavity. An electronic component is arranged in the cavity. The wiring substrate also includes a first insulating material with which the first through holes are filled and a second insulating material with which a gap between the electronic component and walls of the cavity is filled. The first through holes are arranged around the corners of the cavity in a plan view. Each of the first through holes is L-shaped in a plan view and formed continuously along two of the sides of the cavity that define the corresponding corner.

Abstract: A module includes a first partial housing and a second partial housing, wherein the first partial housing and the second partial housing together form a recess, a circuit board disposed in the recess; and an encapsulation mass, which closes the recess. A material from which the first partial housing is manufactured and a material from which the second partial housing is manufactured have a difference in thermal expansion coefficients that is at most 10% of the largest value of the two thermal expansion coefficients, the first partial housing includes a sealing structure and the second partial housing includes a counter-sealing structure, and at least one of the sealing structure and the counter-sealing structure is configured to extend into the other of the sealing structure and the counter-sealing structure.

Abstract: A substrate structure and a manufacturing method thereof are provided. The substrate structure comprises a dielectric material layer, a first conductive wiring layer, a second conductive wiring layer, a first conductive pillar layer, and a second conductive pillar layer. The first conductive wiring layer is disposed inside the dielectric material layer. The first conductive pillar layer having a first conductive pillar is disposed inside the dielectric material layer and between the first conductive wiring layer and the second conductive wiring layer. The second conductive pillar layer having a second conductive pillar is disposed on the second conductive wiring layer. The first conductive wiring layer and the second conductive wiring layer are electrically connected by the first conductive pillar layer. The second conductive pillar is a -shape conductive pillar, a -shape conductive pillar, or a -shape conductive pillar.

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Abstract: A method for manufacturing a back drilling hole in a printed circuit board (PCB) and PCB are provided. The method for manufacturing the back drilling hole comprises: forming a through hole in the PCB (1); forming a metal layer (12) with prescribed thickness on an inner wall of the through hole; filling resin in the through hole which has been formed with the metal layer (12); performing back drilling machining on the through hole which has been filled with the resin; removing metal scraps remained in the through hole. The manufacturing method protects the hole wall copper by filling the hole with the resin, so that acid corrosion process only removes the remained metal scraps after back drilling of the small hole, does not affect on the hole copper of the resin protecting portion.

Abstract: Embodiments herein may relate to a technique for generating a via in a substrate. Specifically, the technique may include coupling a polyethylene terephthalate (PET) layer, a protective metal layer, and a build-up layer to a metal layer. The process may further include etching a via in the PET layer, the protective metal layer, and at least a portion of the build-up layer. The process may further include performing a plasma desmear process on the substrate and then peeling the PET layer to remove the PET layer and the protective metal layer. Other embodiments may be described and/or claimed.

Abstract: A heat spreader for printed wiring boards and a method of manufacture are disclosed. The heat spreader is made from a plurality of graphene sheets that are thermo-mechanically bonded using an alloy bonding process that forms a metal alloy layer using a low temperature and pressure that does not damage the graphene sheets. The resulting heat spreader has a higher thermal conductivity than graphene sheets alone.

Abstract: The present invention relates to a resin composition that becomes a cured product that exhibits force response behavior such that an area surrounded by a tensile stress-strain curve f1(x), when an amount of strain is increased from 0% to 0.3% by pulling at 999 ?m/min while plotting the amount of strain on the x axis and tensile stress on the y axis, and also surrounded by the x axis, is greater than an area surrounded by a stress-strain curve f2(x), when the amount of strain is decreased from 0.3%, and also surrounded by the x axis, and the amount of change in the amount of strain when tensile stress is 0, before and after applying tensile stress, is 0.05% or less.