Preform In Hole Patents (Class 174/265)
  • Patent number: 11905388
    Abstract: The present invention provides a resin composition that contains copper particles and a particular resin and that is capable of producing a cured product having a low volume resistance value, and a cured product obtained by curing the resin composition. The resin composition contains (A) copper particles having an average particle diameter of 0.1 to 20 ?m, (B) a phosphoric acid-modified epoxy resin obtained by reacting a phosphoric acid (b1) with an epoxy compound (b2), and (C) a curing agent, wherein the content of the component (B) and the content of the component (C), based on 100 parts by mass of the total amount of the components (A) to (C), are 0.1 to 30 parts by mass and 0.1 to 5 parts by mass, respectively. Further, the cured product is obtained by curing the resin composition.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 20, 2024
    Assignee: ADEKA CORPORATION
    Inventors: Yusuke Nuida, Hitoshi Hosokawa, Hiroshi Morita
  • Patent number: 11901286
    Abstract: A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Chih-Min Hsiao, Ching-Hsu Chang, Jiann-Tyng Tzeng
  • Patent number: 11882665
    Abstract: This application relates to the field of electronic technologies, and provides a printed circuit board and a manufacturing method thereof, and an electronic device. The printed circuit board has target holes that penetrate through the printed circuit board, and an area that is not provided with the target holes has blocking structures (B) for blocking liquid flow, where the area is on at least one side that is of the printed circuit board and that is connected to the target holes.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: January 23, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhengbao Sun, Xu Zhang, Bin Wang, Hai Hao, Lijun Peng
  • Patent number: 11818841
    Abstract: The present disclosure relates to a printed circuit board. The printed circuit board includes a core layer; a through portion penetrating through the core layer; a first via disposed to be spaced apart from an inner wall of the through portion within the through portion; and a second via disposed in the first via and having a diameter different from that of the first via.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: November 14, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hae Kyo Seo, Jin Won Lee
  • Patent number: 11817847
    Abstract: An elastic wave device includes a piezoelectric substrate, an interdigital transducer electrode on the piezoelectric substrate, a support on the piezoelectric substrate, including a cavity, and surrounding the interdigital transducer electrode at the cavity, a cover covering the cavity and provided on the support, and a via hole electrode penetrating the cover and the support. The via hole electrode includes a projection portion projecting outward from a side surface portion when seen in a plan view. The projection portion is located within the cover.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 14, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Daisuke Fukuda
  • Patent number: 11788196
    Abstract: The present disclosure discloses an ABO3 type high-entropy perovskite Bax(FeCoNiZrY)0.2O3-? electrocatalytic material and a preparation method thereof, belonging to the technical field of electrocatalytic materials. The electrocatalytic material is prepared by taking hydrated cobalt nitrate, hydrated ferric nitrate, hydrated nickel nitrate, barium nitrate, hydrated yttrium nitrate, hydrated zirconium nitrate and polyacrylonitrile staple fibers as raw materials through processes of liquid phase chelation, gelation, calcination, etc. The prepared high-entropy perovskite Bax(FeCoNiZrY)0.2O3-? electrocatalytic material can release more electrochemical active sites due to its special nanostructure, thus showing better electrocatalytic activity.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: October 17, 2023
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Tianxi Liu, Kaibin Chu, Feili Lai
  • Patent number: 11778754
    Abstract: A component carrier includes an electrically insulating layer structure with a first main surface and a second main surface, a through hole extends through the electrically insulating layer structure between the first main surface and the second main surface. The through hole has a first tapering portion extending from the first main surface and a second tapering portion extending from the second main surface. The through hole is delimited by a first plating structure on at least part of the sidewalls of the electrically insulating layer structure and a second plating structure formed separately from and arranged on the first plating structure. The second plating structure includes an electrically conductive bridge structure connecting the opposing sidewalls.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: October 3, 2023
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Robin Zhang, Seok Kim Tay
  • Patent number: 11737205
    Abstract: An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
  • Patent number: 11735502
    Abstract: An integrated circuit chip has an active surface and a chip pad arrangement on the active surface. The chip pad arrangement includes four pairs of chip pads arranged in two rows along a side edge of the active surface. Two pairs of chip pads are a first transmission differential pair chip pad and a first reception differential pair chip pad respectively. Positions of the two pairs of chip pads are not adjacent to each other and are in different rows. The other two pairs of chip pads are a second transmission differential chip pad and a second reception differential chip pad respectively. Positions of the other two pairs of chip pads are not adjacent to each other and are in different rows. In addition, a package substrate corresponding to the integrated circuit chip and an electronic assembly including the package substrate and the integrated circuit chip are also provided.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 22, 2023
    Assignee: VIA LABS, INC.
    Inventor: Sheng-Yuan Lee
  • Patent number: 11586797
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
  • Patent number: 11472088
    Abstract: A method for manufacturing a cosmetic stick having at least two different colored portions includes inserting a pin into at least one mold cavity of a mold body, filling the mold cavity containing the pin with a first cosmetic material of a first color, and then recovering the excess first cosmetic material from a top surface of the mold body. The pin is removed from the mold cavity leaving a void in the mold cavity, and a guard plate is placed over the top surface of the mold body, the guard plate having a hole over the mold cavity. The void in the mold cavity is filled with a second cosmetic material, the second cosmetic material being a second color that is different than the first color. The excess second cosmetic material is then recovered from a top surface of the guard plate.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 18, 2022
    Assignee: PORT JERVIS LABORATORIES, INC.
    Inventors: Vincent Domenick, Cheryl Ewing, Matt Abbadessa
  • Patent number: 11457525
    Abstract: An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
  • Patent number: 11375614
    Abstract: The present disclosure provides a wiring structure, a display substrate and a display device, and belongs to the field of display technology. The wiring structure of the present disclosure comprises a body portion provided with hollow patterns; the body portion has a first side and a second side which are provided opposite to each other along an extending direction of the wiring structure, and both the first and second sides are wavy; the body portion comprises a plurality of conductive elements sequentially connected along the extending direction of the wiring structure; and in each conductive element, a length of a protruding portion on the first side in the extending direction of the wiring structure is different from that of a protruding portion on the second side in the extending direction of the wiring structure.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 28, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhifeng Zhan, Peng Huang, Yanxin Wang, Shuquan Yang, Wei Wang
  • Patent number: 11276618
    Abstract: An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Jonathan Rosch, Andrew J. Brown
  • Patent number: 11233342
    Abstract: An electrical assembly that includes a substrate having an aperture. A flat conductor is mounted to the substrate and extends over at least a portion of the aperture, with a ring terminal in contact with the flat conductor adjacent to the aperture. A lead wire connects to the ring terminal and is spaced from the substrate, and a fastener extends through the ring terminal and flat conductor, secured in the aperture, and securing the ring terminal against the flat conductor.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: January 25, 2022
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Gabrielle Elizabeth Moilanen Vuylsteke, David Jeffeory Berels
  • Patent number: 11196073
    Abstract: The present invention relates to a proton ceramic fuel cell which has a hydrogen-permeable film as an anode and in which an electrolyte material is BaZrxCe1-x-zYzO3 (x=0.1 to 0.8, z=0.1 to 0.25, x+z?1.0) (BZCY). An electron-conducting oxide thin film having a film thickness of 1-100 nm is present between a cathode and an electrolyte comprising the material. The present invention also relates to a method for producing a proton ceramic fuel cell having a hydrogen-permeable film as an anode. The method comprises forming a thin film having a thickness of 1-100 nm between a cathode and an electrolyte comprising BZCY, the thin film comprising an electron-conducting oxide. The present invention provides a novel means for improving the output of a PCFC in which BZCY is used in an electrolyte material, and provides a PCFC having an output that exceeds a benchmark of 0.5 W cm?2 at 500° C.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 7, 2021
    Assignee: National University Corporation Hokkaido University
    Inventors: Yoshitaka Aoki, Hiroki Habazaki, Tomoyuki Yamaguchi
  • Patent number: 11004781
    Abstract: An electronic component mounting substrate including: an insulating substrate for mounting an electronic component; a via conductor disposed in the insulating substrate in an thickness direction of the insulating substrate; and a via pad conductor disposed in the insulating substrate, connected to the via conductor, having a thickness gradually increasing from an outer edge portion toward an inside portion, and including a protruding portion protruding from the via conductor in a width direction of the via conductor.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 11, 2021
    Assignee: Kyocera Corporation
    Inventors: Shigeyoshi Fukuzono, Yuuki Baba
  • Patent number: 10957836
    Abstract: A printed board includes: a plate-shaped base member having an upper surface and a lower surface opposite the upper surface and having an insulation property; a first metal layer disposed on the upper surface; and a second metal layer disposed on the lower surface. The base member has a through-hole penetrating the base member in a thickness direction thereof. The second metal layer is spaced apart from the through-hole by a predetermined distance in a bottom view. The printed board may further include a third metal layer that continuously covers the first metal layer, the second metal layer, and an inner surface of the through-hole. A light emitting device includes the printed board and a light emitting element mounted on the printed board such as to be electrically connected with a wiring pattern composed of the first metal layer, the second metal layer, and the third metal layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 23, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Masaaki Katsumata, Masakazu Sakamoto
  • Patent number: 10790426
    Abstract: A method of manufacturing a light emitting element mounting base member includes: arranging a plurality of core members each including an electrical conductor core and a light-reflecting insulating member provided on a surface of the electrical conductor core; integrally holding the core members with a light blocking resin; and partially removing the insulating members such that at least one surface of the electrical conductor cores is exposed from the light blocking resin.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 29, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Yukitoshi Marutani
  • Patent number: 10624247
    Abstract: An electronic control unit includes; a circuit board including a plurality of layers, the layers including a plurality of ground layers having different thicknesses from one another; a drain line connected to the circuit board; a switching device configured to selectively connect the drain line to one of the plurality of ground layers based on a frequency of an electromagnetic wave inside a vehicle cabin; and a controller configured to control the connection of the switching device based on the frequency of the electromagnetic wave inside the vehicle cabin.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: April 14, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Yuki Wakayama
  • Patent number: 10571529
    Abstract: An electrical structural member comprises a first package and a second package. The first package has a first connection frame, a chip disposed in the first connection frame, and a first encapsulation material encapsulating the chip and at least portions of the first connection frame. The second package has a second connection frame and a second encapsulation material encapsulating at least portions of the second connection frame. The first encapsulation material is securely connected to the second encapsulation material.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: February 25, 2020
    Assignee: TE Connectivity Sensors Germany GmbH
    Inventor: Georg Stute
  • Patent number: 10020327
    Abstract: A method device is prepared with a patterned thin film that can include one or more metal oxides on a suitable substrate. Initially, a pattern of a deposition inhibitor is provided on a surface of the substrate, which deposition inhibitor comprises at least one cellulose ester. This pattern has both inhibitor areas where the deposition inhibitor is present and open areas where the deposition inhibitor is absent. An inorganic thin film is then deposited on the surface of the substrate by a chemical vapor deposition process only in the open areas of the pattern. Further operations can be carried out including deposit of a second inorganic thin film exactly over the initial inorganic thin film, the deposition inhibitor can be removed from the inhibitor areas of the pattern, or both operations can be carried out in sequence.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 10, 2018
    Assignee: EASTMAN KODAK COMPANY
    Inventor: Carolyn Rae Ellinger
  • Patent number: 9793199
    Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor trace with a first segment that does not include a via land. A first via is formed on the first segment.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: October 17, 2017
    Assignee: ATI Technologies ULC
    Inventors: Andrew K W Leung, Neil McLellan, Yip Seng Low
  • Patent number: 9661741
    Abstract: A printed wiring board includes conductive layers, resin insulation layers, a through-hole conductor penetrating through one or more insulation layers and having a first-surface-side and second-surface-side lands, a first-surface-side signal line formed on one of the insulation layers and connecting the first-surface-side land and a conductive layer on the insulation layer, and a second-surface-side signal line formed on one of the insulation layers and connecting the second-surface-side land and a conductive layer on the insulation layer.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: May 23, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Haruhiko Morita, Shinobu Kato
  • Patent number: 9437489
    Abstract: A method of manufacturing a wiring substrate including a step of forming a through hole that includes forming a first concave portion in a substrate that extends from a second surface to a first insulating layer without passing through the first insulating layer; forming a second insulating layer at least within the first concave portion; and forming a second concave portion through the second insulating layer and the first insulating layer to expose a surface of a pad electrode, wherein the second concave portion is formed within the first concave portion; and filling the first concave portion and the second concave portion with a conductive body or forming the conductive body to coat inner walls of the first concave portion and the second concave portion, and forming the through electrode such that it is connected to the pad electrode.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: September 6, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Tsuyoshi Yoda
  • Patent number: 9386686
    Abstract: An electronic package structure is provided which comprises a metal core PCB, an energy storage device and at least one electronic component. The at least one electronic component is disposed between the metal core PCB and the energy storage device. The metal core PCB defines at least a through hole. A thermal passage is disposed in the through hole. An insulating layer is disposed in the through hole and located between the metal layer of the metal core PCB and the thermal passage to prevent the electric coupling between the thermal passage and the metal layer. The energy storage device comprises at least a connecting pin in thermal contact with the thermal passage.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: July 5, 2016
    Assignee: CYNTEC CO., LTD.
    Inventors: Chi-Feng Huang, Bau-Ru Lu, Da-Jung Chen, Jeng-Jen Li
  • Patent number: 9363885
    Abstract: A method of fabricating a heat dissipating board according to the present invention, includes: a substrate intermediate forming step of forming a substrate intermediate with an insulating layer made of an insulating resin material and a conducting layer made of a conductive material formed on the insulating layer; a through hole forming step of forming a through hole having an approximately cylindrical shape, the through hole penetrating through the substrate intermediate; an inserting step of inserting a heat conducting member to be disposed in the through hole, the heat conducting member being made of a metal and having an approximately cylindrical shape; and a plastically deforming step of plastically deforming the heat conducting member to be secured in the through hole. Prior to the inserting step, an annealing step of annealing the heat conducting member is performed.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 7, 2016
    Assignee: Meiko Electronics Co., Ltd.
    Inventors: Noriaki Taneko, Tsuyoshi Takagi, Shukichi Takii
  • Patent number: 9282646
    Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.
    Type: Grant
    Filed: January 26, 2014
    Date of Patent: March 8, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Dyi-Chung Hu, Ming-Chih Chen, Tzyy-Jang Tseng
  • Patent number: 9196538
    Abstract: Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: November 24, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min gi Hong
  • Patent number: 9155203
    Abstract: According to one embodiment, an apparatus includes: a device configured to partially provide a second conductor layer on a surface of a first conductor layer; a device configured to partially provide a first insulating layer on the surface of the first conductor layer; a device configured to integrate the first conductor layer, the second conductor layer, the first insulating layer, and a third conductor layer, in a state in which the second conductor layer and the first insulating layer provided on the surface of the first conductor layer are covered with the third conductor layer from a side opposite the first conductor layer; a device configured to form a conductor pattern by partially removing at least one of the first conductor layer and the third conductor layer in a structure obtained by the integrating; and a device configured to cover both sides of the structure.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiko Happoya, Yasuki Torigoshi, Sadahiro Tamai
  • Publication number: 20150136468
    Abstract: Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Inventors: Henry Meyer Daghighian, Steven C. Bird, YongShan Zhang
  • Patent number: 9024208
    Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 5, 2015
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Sandor Farkas, Stuart Allen Berke
  • Patent number: 8997341
    Abstract: It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings.
    Type: Grant
    Filed: September 6, 2010
    Date of Patent: April 7, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yoshinori Ejiri, Kiyoshi Hasegawa, Takehisa Sakurai, Yoshiaki Tsubomatsu
  • Patent number: 8952271
    Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Limited
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Seiki Sakuyama, Toshiya Akamatsu
  • Patent number: 8952269
    Abstract: Provided are a wiring substrate; a multi-piece wiring substrate array; and a method for reliably producing the multi-piece wiring substrate array. The wiring substrate includes a substrate main body, which has first and second main surfaces, side surfaces, a groove surface, and a fracture surface; and a notch which has a concave shape in plan view, and which is provided on a side surface on a side toward the first main surface, wherein, in the side surface having the notch, the boundary between the groove surface and the fracture surface has first curved portions on opposite sides of the notch, the first curved portions being convex toward the first main surface in side view; and also has a second curved portion on a second-main-surface side of the notch, the second curved portion being convex toward the second main surface of the substrate main body in side view.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: February 10, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Masami Hasegawa, Satoshi Hirayama, Naoki Kito
  • Patent number: 8952268
    Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal carrier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Dyi-Chung Hu, Ming-Chih Chen, Tzyy-Jang Tseng
  • Patent number: 8946892
    Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghoon Kim, Jihyun Lee
  • Patent number: 8916781
    Abstract: An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: December 23, 2014
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Cyprian Emeka Uzoh
  • Patent number: 8901434
    Abstract: A board unit includes a board that has a through hole penetrating the board from a first side of the board to a second side of the board and having a conductive inner wall surface a first electronic component that has a first connection pin to be press-fitted in the through hole from the first side of the board, and a conductive member that is disposed in the through hole to connect the inner wall surface of the through hole to the first connection pin.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Limited
    Inventors: Akihiro Yasuo, Koji Kuroda
  • Patent number: 8890002
    Abstract: A resin multilayer substrate includes a component-containing layer and a thin resin layer stacked on a surface of the component-containing layer. The resin multilayer substrate further includes a surface electrode located on a surface opposite to the surface of the thin resin layer stacked on the component-containing layer, a first via conductor provided in the component-containing layer, which includes an end reaching one surface of the component-containing layer, and a second via conductor provided in the thin resin layer, which includes a first end electrically connected to the surface electrode and a second end electrically connected to the via conductor. A portion of the thin resin layer in contact with the second via conductor defines a projection projecting into the first via conductor.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: November 18, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masashi Arai, Mayuko Nishihara
  • Patent number: 8878072
    Abstract: A method for forming a frame attachment interconnect between a substrate and a frame is disclosed. The method can include applying a composite material (e.g., epoxy-glass prepreg) to a surface of a substrate. The composite material can have one or more holes disposed to substantially align with a corresponding pad on the surface of the substrate. A metal disc is placed in each hole of the composite material on top of the corresponding pad. A frame member can be placed on top of the composite material and the metal discs. The frame member can have one or more pads disposed to substantially align with the metal discs. The substrate, composite material, metal discs and frame combination can be cured in a controlled atmosphere that can include a vacuum and a predetermined temperature to create discrete electrical connections between adjacent pads but with each encapsulated and electrically isolated.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: November 4, 2014
    Assignee: Lockheed Martin Corporation
    Inventors: Stephen Gonya, Jim Patterson, Kenn Twigg
  • Patent number: 8829356
    Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 9, 2014
    Assignee: Unimicron Technology Corporation
    Inventors: Shih-Ping Hsu, Zhao-Chong Zeng
  • Patent number: 8802994
    Abstract: An insulating layer is formed on a support substrate having a conductive property. Write wiring traces, read wiring traces, and first and second electrode pad pairs are formed on the insulating layer. The first electrode pad pair is connected to the write wiring traces. The second electrode pad pair is connected to the read wiring traces. Parts of regions of the support substrate, which overlap the electrode pads, are removed. Thus, openings are formed in the regions of the support substrate, which overlap the electrode pads.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: August 12, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Jun Ishii, Daisuke Yamauchi
  • Patent number: 8779561
    Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi Ho Jeong, Si Young Yang, Jae Wook Kwon, Jeong Hoon Park, Hyun Ju Yi, Choon Keun Lee
  • Patent number: 8772646
    Abstract: A method for manufacturing a printed wiring board includes preparing a metal sheet having metal members and connectors joining the metal members, forming a structure having core substrates which are connected through the connectors and which have insulation structure portions covering the metal members, respectively, cutting the connectors in the structure such that an independent core substrate having a recessed portion is formed and a respective one of the connectors is removed from the independent core substrate, and covering the recess portion of the independent core substrate with a resin. The covering of the recess portion includes either forming an interlayer insulation layer on a surface of the independent core substrate or forming interlayer insulation layers on opposing surfaces of the independent core substrate.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: July 8, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Kazuyuki Ueda, Takema Adachi, Kazuhiro Yoshikawa
  • Patent number: 8766101
    Abstract: A wiring substrate includes an inorganic substrate including a substrate body formed of an inorganic material, a wiring pattern formed on the substrate body, and an external connection terminal being electrically connected to the wiring pattern, an organic substrate that is formed below the inorganic substrate, the organic substrate including an insulating layer and a wiring layer formed on the insulating layer, and a bonding layer interposed between the inorganic substrate and the organic substrate, the bonding layer including a stress buffer layer and a penetration wiring that penetrates the stress buffer layer. A thermal expansion coefficient of the stress buffer layer is greater than a thermal expansion coefficient of the inorganic substrate and less than a thermal expansion coefficient of the organic substrate. The wiring pattern and the wiring layer are electrically connected by way of the penetration wiring.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 1, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Ken Miyairi, Akihito Takano
  • Patent number: 8759691
    Abstract: A wiring board has a first resin insulation layer, a first conductive pattern formed on the first resin insulation layer, a second resin insulation layer formed on the first conductive pattern and having an opening portion exposing at least a portion of the first conductive pattern, a second conductive pattern formed on the second resin insulation layer, and a via conductor formed in the opening portion of the second resin insulation layer and electrically connecting the first conductive pattern and the second conductive pattern. The via conductor has a side surface extending between the first conductive pattern and the second conductive pattern and a bent portion where an inclination of the side surface of the via conductor changes in a depth direction of the via conductor.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: June 24, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Shinji Ouchi, Shigeru Yamada, Makoto Terui, Yoshinori Shizuno
  • Patent number: 8754336
    Abstract: A wiring board includes: wiring layers; insulating layers disposed between the wiring layers; and external connection pads respectively including surface plated layers, for connecting to an external circuit. In each of the external connection pads in one face of the wiring board, an outer peripheral edge of the external connection pad is retracted from an outer peripheral edge of the surface plated layer toward a center of the external connection pad.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: June 17, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kentaro Kaneko
  • Publication number: 20140158416
    Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include an electronic arrangement, a first die, and a second die coupled to the first die and the electronic arrangement. The electronic arrangement may include an opening. At least a portion of the die may occupy at least a portion of the opening in the electronic arrangement. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Inventors: Youngseok Oh, Joe Walczyk
  • Patent number: 8743555
    Abstract: Substrates having power planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a first power plane and a second power plane. The at least one noise suppression structure may include a first power plane extension that extends from the first power plane generally toward the second power plane, and a second power plane extension that extends from the second power plane generally toward the first power plane. Methods for suppressing noise in at least one of the first power plane and second power plane include providing such noise suppression structures between the power planes.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Houfei Chen, Shiyou Zhao