With Particular Conductive Connection (e.g., Crossover) Patents (Class 174/261)
  • Patent number: 11510318
    Abstract: A single-layer redistribution plate functioning as a space translator between a device under testing (“DUT”) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: November 22, 2022
    Inventors: Dominik Schmidt, Prasanna Rao Chitturi, Jed Hsu
  • Patent number: 11476202
    Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: October 18, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Han-Wen Chen, Steven Verhaverbeke, Guan Huei See, Giback Park, Giorgio Cellere, Diego Tonini, Vincent Dicaprio, Kyuil Cho
  • Patent number: 11476149
    Abstract: The present invention discloses a substrate configured to receive a plurality of micro elements on a carrier board. The substrate comprises a body, a first conductive bump, and a second conductive bump. The body has a first surface, a transfer area is defined within the first surface, and a central portion and a peripheral portion is defined within the transfer area. The first conductive bump, disposed on the central portion, has a first volume. The second conductive bump, disposed on the peripheral portion, has a second volume. Wherein the first volume is different from the second volume.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: October 18, 2022
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen
  • Patent number: 11477886
    Abstract: A circuit board structure includes a body, multiple first pads, a conductive assembly, multiple first engaging components, and multiple second engaging components. The body includes a first portion and a second portion integrally formed. A first surface of the first portion directly contacts a second surface of the second portion. A first region of the first surface protrudes from the second portion, and a second region of the second surface protrudes from the first portion. The first pads and the first engaging components are disposed on the first portion of the body and located in the first region of the first surface. The conductive assembly and the second engaging components are disposed on the second portion of the body and located in the second region of the second portion. The first pads are located between the first engaging components, and the conductive assembly is located between the second engaging components.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: October 18, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Yunn-Tzu Yu, Ching-Ho Hsieh, Wang-Hsiang Tsai
  • Patent number: 11465397
    Abstract: An economical, efficient, and effective formation of a high resolution pattern of conductive material on a variety of films by polymer casting. This allows, for example, quite small-scale patterns with sufficient resolution for such things as effective microelectronics without complex systems or steps and with substantial control over the characteristics of the film. A final end product that includes that high resolution functional pattern on any of a variety of substrates, including flexible, stretchable, porous, biodegradable, and/or biocompatible. This allows, for example, highly beneficial options in design of high resolution conductive patterns for a wide variety of applications.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: October 11, 2022
    Assignee: Iowa State University Research Foundation, Inc.
    Inventors: Metin Uz, Surya Mallapragada
  • Patent number: 11450805
    Abstract: An object is to provide a semiconductor material and coating having high solubility in solvents and having advantageous filling property, high heat resistance, and/or high etching resistance. Another object is to provide a method for manufacturing a semiconductor using the semiconductor material. Still another object is to provide a novel compound. Provided are: a semiconductor material consisting of a specific aromatic hydrocarbon ring derivative; methods for manufacturing a coating and a semiconductor using the semiconductor material; and a compound consisting of a specific aromatic hydrocarbon ring derivative.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 20, 2022
    Assignee: MERCK PATENT GMBH
    Inventors: Shigemasa Nakasugi, Hiroshi Yanagita, Kazunori Kurosawa, Takashi Sekito, Yusuke Hama, Yuriko Matsuura
  • Patent number: 11435860
    Abstract: A touch panel including: a first electrode pattern arranged in a first direction, including a plurality of first electrode cells that are physically separated from each other; a second electrode pattern arranged in a second direction crossing the first direction, including a plurality of second electrode cells that are physically separated from each other; first touch signal lines connected to the first electrode cells; and second touch signal lines connected to the second electrode cells. The electrode patterns and the touch signal lines are arranged on the same layer on a substrate such that a first virtual connection line for connecting centers of second electrode cells of a first group corresponding to an n-th first electrode cell crosses a second virtual connection line for connecting centers of second electrode cells of a second group corresponding to an (n+1)-th first electrode cell.
    Type: Grant
    Filed: March 7, 2021
    Date of Patent: September 6, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Hye Shin, Soon Sung Ahn
  • Patent number: 11432398
    Abstract: One example printed circuit board transmission line includes a substrate layer, a metal line, at least one first welding point, at least one first transmission medium, and a metal component that is configured to implement a grounding function. The metal line is plated on a surface of the substrate layer. The at least one first welding point is a welding point at which the metal line is connected to the at least one first transmission medium. The at least one first welding point is welded to the metal line and welded to the at least one first transmission medium. The metal component is welded to the at least one first transmission medium. At least one groove is provided on one side of the at least one first welding point.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: August 30, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yiyao Wu, Xinbo Ma, Zhiqiang Liao
  • Patent number: 11417821
    Abstract: Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: August 16, 2022
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Anna Y. Herr, Vladimir V. Talanov, Quentin P. Herr
  • Patent number: 11398705
    Abstract: A charging surface comprising multiple conductive regions can be used to charge an electronic device placed on it the surface so that electrodes on the device engage respective conductive regions of the surface. In order to distinguish such chargeable devices from short circuits and other spurious connections, the devices are required to demonstrate an anti-inversion characteristic, for example implemented with a MOSFET, across at least a pair of these electrodes. The surface can then be controlled so as to establish a text voltage across each pair of conductive regions in sequence, and look for pairs of conductive regions behaving as being coupled by such an anti inverter circuit. Relationships between every pair of conductive regions can be determined and recording, and the voltage level supplied to each conductive region set accordingly.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 26, 2022
    Assignee: FRANCE BREVETS
    Inventors: Daniel Lollo, Timothée Le Quesne, Matthieu Poidatz
  • Patent number: 11398433
    Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 26, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Han-Wen Chen, Steven Verhaverbeke, Guan Huei See, Giback Park, Giorgio Cellere, Diego Tonini, Vincent Dicaprio, Kyuil Cho
  • Patent number: 11375615
    Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film and a metal layer disposed on at least one of surfaces of the base film. In the substrate for a printed circuit board, an amount of nitrogen present per unit area, the amount being determined on the basis of a peak area of a N1s spectrum in XPS analysis of a surface of the base film exposed after removal of the metal layer by etching with an acidic solution, is 1 atomic % or more and 10 atomic % or less.
    Type: Grant
    Filed: August 6, 2016
    Date of Patent: June 28, 2022
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Printed Circuits, Inc., Sumitomo Electric Fine Polymer, Inc.
    Inventors: Yuichiro Yamanaka, Yoshio Oka, Satoshi Kiya, Yoshifumi Uchita, Makoto Nakabayashi
  • Patent number: 11373942
    Abstract: A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: June 28, 2022
    Inventors: Junyoung Ko, Senyun Kim, Younghoon Ro
  • Patent number: 11362464
    Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 14, 2022
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
  • Patent number: 11355484
    Abstract: A micro LED display panel includes a substrate, a plurality of first metal electrodes and a plurality of metal pads on a surface of the substrate, a connection layer on the substrate, a plurality of micro LEDs on a side of the connection layer away from the substrate. The connection layer includes conductive particles. Each of the micro LEDs is coupled to at least one of the first metal electrode. A side of each of the metal pads away from the substrate is coupled to some of the conductive particles in the connection layer to form a metal retaining wall. The metal retaining walls enhance structural strength of the micro LED display panel and avoid breakage of any of the micro LEDs.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: June 7, 2022
    Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventor: Po-Ching Lin
  • Patent number: 11342697
    Abstract: A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 24, 2022
    Assignee: International Business Machines Corporation
    Inventors: Paul W Coteus, Thomas Cipolla, Kyu-hyoun Kim, Edmund Blackshear
  • Patent number: 11330711
    Abstract: The present invention is directed to flexible conductive articles (600) that include a printed circuit (650) and a stretchable or non-stretchable substrate (610). In some embodiments, the substrate has a printed circuit on both sides. The printed circuit contains N therein a porous synthetic polymer membrane (660) and an electrically conductive trace (670) as well as a non-conducive region (640). The electrically conductive trace is imbibed or otherwise incorporated into the porous synthetic polymer membrane. In some embodiments, the synthetic polymer membrane is microporous. The printed circuit may be discontinuously bonded to the stretchable or non-stretchable substrate by adhesive dots (620). The printed circuits may be integrated into garments, such as smart apparel or other wearable technology.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 10, 2022
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Mark D. Edmundson, Paul D. Gassler, Justin J. Skaife, Scott J. Zero
  • Patent number: 11316305
    Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 26, 2022
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
  • Patent number: 11302624
    Abstract: In some implementations, a substrate for coupling to an integrated circuit includes multiple layers. Each of the multiple layers has, in a particular region of the substrate, a repeating pattern of regions corresponding to power and ground. The multiple layers include (i) a top layer having, in the particular region, power contacts and ground contacts for coupling to an integrated circuit and (ii) a bottom layer having, in the particular region, power contacts and ground contacts for coupling to another device. At least one layer of the multiple layers has a repeating pattern of signal traces that extend along and are located between the regions corresponding to ground in the at least one layer.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 12, 2022
    Assignee: Google LLC
    Inventors: Jin Young Kim, Zhonghua Wu
  • Patent number: 11289415
    Abstract: A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 ?m or less.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 29, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mizuho Ishikawa, Kazuhiro Ueda
  • Patent number: 11289405
    Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 29, 2022
    Assignee: ROHM Co., Ltd.
    Inventors: Satoshi Kageyama, Yoshihisa Takada
  • Patent number: 11289414
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim
  • Patent number: 11277923
    Abstract: A printed wiring board includes a conductor layer, an outermost resin insulating layer having a first surface and a second surface on the opposite side with respect to the first surface and laminated on the conductor layer such that the second surface faces the conductor layer, and metal posts formed in the outermost resin insulating layer such that the metal posts are penetrating through the outermost resin insulating layer and reaching the conductor layer. The metal posts include first metal posts and second metal posts such that each of the first metal posts has a first upper surface positioned above the first surface of the outermost resin insulating layer and having an entirely flat surface and that each of the second metal posts has a second upper surface positioned above the first surface of the outermost resin insulating layer and having a partly flat surface.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: March 15, 2022
    Assignee: IBIDEN CO., LTD.
    Inventors: Yukinobu Mikado, Tomoaki Shinozuka
  • Patent number: 11247439
    Abstract: A display unit according to an embodiment of the disclosure includes a substrate, a wiring line and a light-emission section that are provided on the substrate, an insulating layer covering the wiring line and the light-emission section, and provided on an entire surface of the substrate, and a sealing layer provided on an entire surface of the insulating layer, and including a resin material having an oxygen transmission rate higher than a water-vapor transmission rate.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 15, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Toshiya Takagishi
  • Patent number: 11244912
    Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: Sai Vadlamani, Aleksandar Aleksov, Rahul Jain, Kyu Oh Lee, Kristof Kuwawi Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati, Telesphor Kamgaing
  • Patent number: 11234328
    Abstract: A circuit board disclosed in the present invention includes a substrate and a circuit layer. The circuit layer is formed on a surface of the substrate and includes at least one test circuit line. The test circuit line includes a main segment and a branch segment connected with each other. The branch segment is provided to be contacted with a test equipment for electrical test so as to protect the main segment from breaking during electrical test.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: January 25, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chia-En Fan, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11232825
    Abstract: A capacitor is provided. The capacitor includes a substrate that has opposing first and second main surfaces. The capacitor also includes at least two conductive plates that are formed in the substrate and extend from the first main surface to the second main surface of the substrate. The capacitor further includes at least one insulating structure that is formed between two adjacent conductive plates of the at least two conductive plates and extends from the first main surface to the second main surface.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: January 25, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Liang Chen, Cheng Gan, Xin Wu, Wei Liu
  • Patent number: 11217513
    Abstract: An integrated circuit (IC) package includes an encapsulation package that contains an integrated circuit die attached to a lead frame. A set of contacts is formed on the package that each have an exposed contact sidewall surface and an exposed contact lower surface. A protective layer of solder wettable material covers each contact sidewall surface.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: January 4, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daiki Komatsu, Makoto Shibuya
  • Patent number: 11217508
    Abstract: The present invention discloses a lead structure of the circuit, which comprises a first lead and a second lead. The first lead includes a first bump connecting part and a first lead segment. The first lead segment is connected to the first bump connecting part. The width of the first lead segment is smaller than the width of the first bump connecting part. The second lead is adjacent to the first lead and there is a lead gap therebetween. The second lead also includes a second bump connecting part and a first lead segment. The first lead segment of the second lead is connected to the second bump connecting part. The second bump connecting part and the first bump connecting part are arranged staggeredly. The second bump connecting part is adjacent to the first lead segment of the first lead.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: January 4, 2022
    Assignee: Sitronix Technology Corp.
    Inventors: Kuo-Wei Tseng, Po-Chi Chen, Jui-Hsuan Cheng
  • Patent number: 11211722
    Abstract: One embodiment includes a computer interconnect system. The system includes a first cable comprising a first superconducting signal line formed from a superconductor material to propagate at least one signal and a second cable comprising a second superconducting signal line formed from the superconductor material to propagate the respective at least one signal. The system also includes an interconnect structure configured to contact each of the first and second cable and comprising a third superconducting signal line formed from the superconductor material and configured to propagate the respective at least one signal between the respective first and second superconducting signal line. The system further includes at least one interconnect contact disposed on the first, second, and third at least one superconducting signal line at a contact portion between each of the at least one first and third superconducting signal lines and the at least second and third superconducting signal lines.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: David B. Tuckerman
  • Patent number: 11203165
    Abstract: A wire embedding system and methods are presented. A wire is embedded in a substrate at predetermined locations in a series of sequential embedding instances using heat and pressure. The heat and pressure are removed from the wire in between the series of sequential embedding instances.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 21, 2021
    Assignee: Board of Regents, The University of Texas System
    Inventors: Chi Yen Kim, Ryan Wicker, David Espalin, Charlie Sullivan
  • Patent number: 11205861
    Abstract: A staking terminal includes a conductor portion having a conductor platform, a first plurality of tines extending from the conductor platform, and a conductor crimp extending from the conductor platform. The conductor platform and the tines are not coplanar in a folded configuration. The staking terminal further includes a ground portion having a ground platform, a second plurality of tines extending from the ground platform, and a first braid crimp extending from the ground platform. The ground platform and the tines are not coplanar in the folded configuration.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: December 21, 2021
    Assignee: Illinois Tool Works Inc.
    Inventors: Edward Bulgajewski, John Healey
  • Patent number: 11201426
    Abstract: Methods of coating contacts to have a specific color. The color can be selected to match a color of a portion of a device enclosure for an electronic device housing the contacts. Examples can instead provide methods of coating contacts to have a color to contrast with a color of a portion of the device enclosure. These methods can provide electrical contacts having a low contact resistance and good corrosion and scratch resistance.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 14, 2021
    Assignee: Apple Inc.
    Inventors: Raymund W. M. Kwok, Hani Esmaeili, Robert Scritzky, Michael W. Barnstead, Xiaoqiang Huang, Ida Y. Lo, Sean R. Novak, Christoph Werner
  • Patent number: 11195657
    Abstract: A multilayer electronic component includes a body including a capacitance forming portion including dielectric layers and first and second internal electrodes with respective dielectric layers interposed therebetween and an upper cover portion and a lower cover portion, respectively disposed above and below the capacitance forming portion, and first and second external electrodes disposed on the body and respectively connected to the first and second internal electrodes. At least one of the upper cover portion or the lower cover portion includes a dummy electrode layer including a dummy pattern having a mesh shape. The dummy pattern includes a first dummy pattern, connected to the first external electrode, and a second dummy pattern spaced apart from the first dummy pattern and connected to the second external electrode.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO LTD
    Inventors: Je Jung Kim, Seung Ryeol Lee, Ji Won Lee
  • Patent number: 11195679
    Abstract: A temperature-dependent switch includes a housing with a top face and an outer face that runs transversely to the top face. The switch includes a first outer contact area that is arranged on the top face. The switch includes a second outer contact area that is arranged at the housing. The switch includes a temperature-dependent switching mechanism that is arranged in the housing and configured to establish or open an electrically conductive connection between the first and the second outer contact area depending on a temperature of the switching mechanism. The housing is disposed in a metal mounting cap that includes a wall. An upper rim of the wall protrudes beyond the top face of the housing. An inner side of the wall bears at least partially against the outer face of the housing.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 7, 2021
    Inventor: Marcel P. Hofsaess
  • Patent number: 11181793
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Patent number: 11172837
    Abstract: In one aspect, forming a stacked strain gauge sensor with increased electrical resistance includes: forming multiple sensor layers, wherein the sensor layers include strain gauge sensor wires on substrates; forming holes in the substrates; stacking the sensor layers, one on top of another, to form a stack with the holes aligned in one or more locations forming through holes in the stack; and forming interconnects in the holes in one or more other locations interconnecting the strain gauges sensor wires between adjacent sensor layers to form a stacked strain gauge sensor. A stacked strain gauge sensor and method of use thereof are also provided.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Katsuyuki Sakuma, Jeffrey D. Gelorme, Marlon Agno
  • Patent number: 11162979
    Abstract: A plate spring-type connection pin is proposed. The connection pin includes: a support pin that has a bending lip portion at an upper portion thereof and a base portion at a lower portion thereof, and is vertically elongated; a plate spring that has an upper probe portion vertically extending adjacent to the lip portion, a lower probe portion disposed at the same height as the base portion, a laterally lying V-shaped portion disposed between the upper probe portion and the lower probe portion, an upper bending portion connecting an upper end of the V-shaped portion and a lower end of the upper probe portion, and a lower bending portion connecting a lower end of the V-shaped portion and an upper end of the lower probe portion; and a bridge that is disposed between the base portion of the support pin and the lower probe portion of the plate spring.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 2, 2021
    Inventor: Sangyang Pak
  • Patent number: 11158597
    Abstract: The electronic device includes first and second semiconductor components. And, the electronic device includes a sealing body for sealing the first semiconductor component (i.e., the logic chip). A plurality of through conductors electrically connected to the first semiconductor component and/or the second semiconductor component is formed in the sealing body. In plan view, the sealing body has a first region in which the first semiconductor component is located, a second region located on a periphery of a first surface of the sealing body, a third region located between the second region and the first region, and a fourth region located between the second region and the third region. The plurality of through conductors is arranged most in the second region. The number of the plurality of through conductors located in the third region is larger than the number of the plurality of through conductors located in the fourth region.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 26, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Wataru Shiroi, Shuuichi Kariyazaki
  • Patent number: 11160162
    Abstract: Disclosed herein are multi-layer metal circuits, such as printed circuit boards (PCBs), with single-sided, partially-shielded, or fully-shielded via-less common-mode filters. The multi-layer metal circuits comprise at least one shield layer, at least one signal trace, and at least one reference layer (e.g., ground). The reference layer comprises a pattern of the via-less common-mode filter. The pattern may comprise, for example, a single piece-wise linear segment, or two or more disjoint and non-intersecting segments (which may be strictly linear or piece-wise linear). The reference layer is electrically isolated from the shield layer, and thus the via-less common-mode filters do not require vias. In addition to being used in PCBs, the disclosed multi-layer metal circuits may also be used in other applications, such as integrated circuits (e.g., implemented in semiconductor chips).
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xinzhi Xing, Antonio Ciccomancini Scogna, Jack Nguyen
  • Patent number: 11160165
    Abstract: A component carrier and a method of manufacturing a component carrier are provided. The component carrier includes a stack having a front side and a back side, the stack including a plurality of stacked electrically insulating layer structures, a through hole being narrower in its inner portion compared to its exterior portions and extending through the plurality of electrically insulating layer structures so that sidewalls of each of the electrically insulating layer structures delimit respective parts of the through hole, and an electrically conductive filling medium filling at least a part of the through hole.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: October 26, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Mikael Tuominen, Seok Kim Tay, Sally Sun, Robin Zhang
  • Patent number: 11127643
    Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 21, 2021
    Assignee: XILINX, INC.
    Inventors: Vadim Heyfitch, Jaspreet Singh Gandhi
  • Patent number: 11122678
    Abstract: A structure having imbedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surface of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 14, 2021
    Assignee: Tesla, Inc.
    Inventors: Vijaykumar Krithivasan, Jin Zhao, Mengzhi Pang, Steven Wayne Butler, Ganesh Venkataramanan, Yang Sun
  • Patent number: 11114405
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure; a first conductive layer on the first transition layer; and a second conductive layer over the first conductive layer. The first conductive layer is substantially made of twinned copper. A first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hua Chang, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 11114776
    Abstract: Various implementations include a method of connecting wire to conductive fabric. The method includes (1) providing a conductive fabric having a main portion and a protrusion extending along a protrusion central axis from the main portion, the protrusion having a distal edge spaced apart from the main portion along the central axis and side edges that extend between the main portion and the distal edge; (2) placing a wire along at least a portion of the protrusion, the wire having a first end and a second end opposite the first end; (3) folding the distal edge of the protrusion over the wire one or more times to form a folded portion of the protrusion; and (4) after folding the distal edge, securing the folded portion of the protrusion with a securing device.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 7, 2021
    Assignee: JOYSON SAFETY SYSTEMS ACQUISITION LLC
    Inventor: Dwayne Van'tZelfde
  • Patent number: 11101570
    Abstract: An integrated antenna array device includes a circuitry component layer having bounds defining a circuitry zone. The circuitry component layer includes beam steering circuitry. The integrated antenna array device also includes an antenna component layer affixed to the circuitry component layer in the circuitry zone. The antenna component layer includes a radiating region and an interconnecting region. The radiating region is outside the circuitry zone and includes one or more antenna arrays having radiating antenna elements. The interconnecting region is substantially defined within the circuitry zone and interconnects the beam steering circuitry with the one or more radiating elements.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 24, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sean Russell Mercer, Nahal Niakan
  • Patent number: 11101189
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 24, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming Yen Lee, Chia-Hao Sung, Ching-Han Huang, Yu-Hsuan Tsai
  • Patent number: 11096286
    Abstract: There is provided a printed circuit board including: a first insulating layer; a first circuit pattern formed on a first surface of the first insulating layer; an adhesive layer provided on a second surface of the first insulating layer; and an electronic component disposed on the adhesive layer and enclosed by the first insulating layer and a second insulating layer formed on the first insulating layer.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 17, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung Hyun Park, Yong Ho Baek, Jae Hoon Choi
  • Patent number: 11088062
    Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
  • Patent number: 11076516
    Abstract: Aspects relate to methods of building Z-graded radiation shielding and covers. In one aspect, the method includes: providing a substrate surface having about medium Z-grade; plasma spraying a first metal having higher Z-grade than the substrate surface; and infusing a polymer layer to form a laminate. In another aspect, the method includes electro/electroless plating a first metal having higher Z-grade than the substrate surface. In other aspects, the invention provides methods of improving an existing electronics enclosure to build a Z-graded radiation shield by applying a temperature controller to at least part of the enclosure and affixing at least one layer of a first metal having higher Z-grade than the enclosure.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 27, 2021
    Assignee: UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF NASA
    Inventors: Donald L. Thomsen, III, Roberto J. Cano, Brian J. Jensen, Stephen J. Hales, Joel A. Alexa