With Particular Conductive Connection (e.g., Crossover) Patents (Class 174/261)
  • Patent number: 11181793
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Patent number: 11172837
    Abstract: In one aspect, forming a stacked strain gauge sensor with increased electrical resistance includes: forming multiple sensor layers, wherein the sensor layers include strain gauge sensor wires on substrates; forming holes in the substrates; stacking the sensor layers, one on top of another, to form a stack with the holes aligned in one or more locations forming through holes in the stack; and forming interconnects in the holes in one or more other locations interconnecting the strain gauges sensor wires between adjacent sensor layers to form a stacked strain gauge sensor. A stacked strain gauge sensor and method of use thereof are also provided.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Katsuyuki Sakuma, Jeffrey D. Gelorme, Marlon Agno
  • Patent number: 11162979
    Abstract: A plate spring-type connection pin is proposed. The connection pin includes: a support pin that has a bending lip portion at an upper portion thereof and a base portion at a lower portion thereof, and is vertically elongated; a plate spring that has an upper probe portion vertically extending adjacent to the lip portion, a lower probe portion disposed at the same height as the base portion, a laterally lying V-shaped portion disposed between the upper probe portion and the lower probe portion, an upper bending portion connecting an upper end of the V-shaped portion and a lower end of the upper probe portion, and a lower bending portion connecting a lower end of the V-shaped portion and an upper end of the lower probe portion; and a bridge that is disposed between the base portion of the support pin and the lower probe portion of the plate spring.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 2, 2021
    Inventor: Sangyang Pak
  • Patent number: 11160165
    Abstract: A component carrier and a method of manufacturing a component carrier are provided. The component carrier includes a stack having a front side and a back side, the stack including a plurality of stacked electrically insulating layer structures, a through hole being narrower in its inner portion compared to its exterior portions and extending through the plurality of electrically insulating layer structures so that sidewalls of each of the electrically insulating layer structures delimit respective parts of the through hole, and an electrically conductive filling medium filling at least a part of the through hole.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: October 26, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Mikael Tuominen, Seok Kim Tay, Sally Sun, Robin Zhang
  • Patent number: 11160162
    Abstract: Disclosed herein are multi-layer metal circuits, such as printed circuit boards (PCBs), with single-sided, partially-shielded, or fully-shielded via-less common-mode filters. The multi-layer metal circuits comprise at least one shield layer, at least one signal trace, and at least one reference layer (e.g., ground). The reference layer comprises a pattern of the via-less common-mode filter. The pattern may comprise, for example, a single piece-wise linear segment, or two or more disjoint and non-intersecting segments (which may be strictly linear or piece-wise linear). The reference layer is electrically isolated from the shield layer, and thus the via-less common-mode filters do not require vias. In addition to being used in PCBs, the disclosed multi-layer metal circuits may also be used in other applications, such as integrated circuits (e.g., implemented in semiconductor chips).
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xinzhi Xing, Antonio Ciccomancini Scogna, Jack Nguyen
  • Patent number: 11158597
    Abstract: The electronic device includes first and second semiconductor components. And, the electronic device includes a sealing body for sealing the first semiconductor component (i.e., the logic chip). A plurality of through conductors electrically connected to the first semiconductor component and/or the second semiconductor component is formed in the sealing body. In plan view, the sealing body has a first region in which the first semiconductor component is located, a second region located on a periphery of a first surface of the sealing body, a third region located between the second region and the first region, and a fourth region located between the second region and the third region. The plurality of through conductors is arranged most in the second region. The number of the plurality of through conductors located in the third region is larger than the number of the plurality of through conductors located in the fourth region.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 26, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Wataru Shiroi, Shuuichi Kariyazaki
  • Patent number: 11127643
    Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 21, 2021
    Assignee: XILINX, INC.
    Inventors: Vadim Heyfitch, Jaspreet Singh Gandhi
  • Patent number: 11122678
    Abstract: A structure having imbedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surface of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 14, 2021
    Assignee: Tesla, Inc.
    Inventors: Vijaykumar Krithivasan, Jin Zhao, Mengzhi Pang, Steven Wayne Butler, Ganesh Venkataramanan, Yang Sun
  • Patent number: 11114405
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure; a first conductive layer on the first transition layer; and a second conductive layer over the first conductive layer. The first conductive layer is substantially made of twinned copper. A first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hua Chang, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 11114776
    Abstract: Various implementations include a method of connecting wire to conductive fabric. The method includes (1) providing a conductive fabric having a main portion and a protrusion extending along a protrusion central axis from the main portion, the protrusion having a distal edge spaced apart from the main portion along the central axis and side edges that extend between the main portion and the distal edge; (2) placing a wire along at least a portion of the protrusion, the wire having a first end and a second end opposite the first end; (3) folding the distal edge of the protrusion over the wire one or more times to form a folded portion of the protrusion; and (4) after folding the distal edge, securing the folded portion of the protrusion with a securing device.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 7, 2021
    Assignee: JOYSON SAFETY SYSTEMS ACQUISITION LLC
    Inventor: Dwayne Van'tZelfde
  • Patent number: 11101570
    Abstract: An integrated antenna array device includes a circuitry component layer having bounds defining a circuitry zone. The circuitry component layer includes beam steering circuitry. The integrated antenna array device also includes an antenna component layer affixed to the circuitry component layer in the circuitry zone. The antenna component layer includes a radiating region and an interconnecting region. The radiating region is outside the circuitry zone and includes one or more antenna arrays having radiating antenna elements. The interconnecting region is substantially defined within the circuitry zone and interconnects the beam steering circuitry with the one or more radiating elements.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 24, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sean Russell Mercer, Nahal Niakan
  • Patent number: 11101189
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 24, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming Yen Lee, Chia-Hao Sung, Ching-Han Huang, Yu-Hsuan Tsai
  • Patent number: 11096286
    Abstract: There is provided a printed circuit board including: a first insulating layer; a first circuit pattern formed on a first surface of the first insulating layer; an adhesive layer provided on a second surface of the first insulating layer; and an electronic component disposed on the adhesive layer and enclosed by the first insulating layer and a second insulating layer formed on the first insulating layer.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 17, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung Hyun Park, Yong Ho Baek, Jae Hoon Choi
  • Patent number: 11088062
    Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
  • Patent number: 11075171
    Abstract: A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jung Soo Kim
  • Patent number: 11076516
    Abstract: Aspects relate to methods of building Z-graded radiation shielding and covers. In one aspect, the method includes: providing a substrate surface having about medium Z-grade; plasma spraying a first metal having higher Z-grade than the substrate surface; and infusing a polymer layer to form a laminate. In another aspect, the method includes electro/electroless plating a first metal having higher Z-grade than the substrate surface. In other aspects, the invention provides methods of improving an existing electronics enclosure to build a Z-graded radiation shield by applying a temperature controller to at least part of the enclosure and affixing at least one layer of a first metal having higher Z-grade than the enclosure.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 27, 2021
    Assignee: UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF NASA
    Inventors: Donald L. Thomsen, III, Roberto J. Cano, Brian J. Jensen, Stephen J. Hales, Joel A. Alexa
  • Patent number: 11071201
    Abstract: An electrical component is configured to allow electrical cables to be mounted directly to a package substrate, such that electrical traces of the package substrate directly place the electrical cables in electrical communication with an integrated circuit that is mounted to the package substrate without passing through any separable interfaces of an electrical connector.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: July 20, 2021
    Assignee: SAMTEC, INC.
    Inventor: James Dunlop
  • Patent number: 11067622
    Abstract: A method for testing a printed circuit board includes providing a printed circuit board having a first main section, a second main section, a bent connecting section and at least one monitoring conductor track. The connecting section is disposed between the first main section and the second main section. The monitoring conductor track runs from the first main section, in a curved manner through the connecting section, to the second main section. At least one electrical measurement value which is representative of the integrity of the at least one monitoring conductor track is detected. A printed circuit board, a control unit and methods for producing the printed circuit board and for operating the control unit are also provided.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: July 20, 2021
    Assignee: Vitesco Technologies GmbH
    Inventors: Detlev Bagung, Hubert Horn
  • Patent number: 11056841
    Abstract: An electrical connector including a housing and electrical conductor plating. The housing includes a first member and a second member. The first member is made of plastic and forms at least one first contact receiving channel therein. The second member is attached around the first member, and the first and second members form at least one second contact receiving channel therebetween. The electrical conductor plating is on the first member. The electrical conductor plating includes at least one first section along the at least one first contact receiving channel and at least one second section along an exterior side of the first member at the at least one second contact receiving channel. The first and second sections of the electrical conductor plating are electrically separate from one another.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 6, 2021
    Assignee: FCI USA LLC
    Inventor: Charles Copper
  • Patent number: 11056475
    Abstract: A semiconductor module includes: a first circuit substrate having a conductive layer disposed on an insulating plate; a plurality of semiconductor elements on the conductive layer, a second circuit substrate disposed above the semiconductor elements, the second circuit substrate having a main current wiring layer and a control wiring layer positioned in a layer above the main current wiring layer; a first lead terminal vertically extending upwards from and in contact with the main current wiring layer; a second lead terminal vertically extending upwards from and in contact with the conductive layer of the first circuit substrate; a third lead terminal vertically extending upwards from and in contact with the control wiring layer; and a sealing material covering at least some of the elements mentioned above.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 6, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Katsumi Taniguchi
  • Patent number: 11044808
    Abstract: A printed circuit board includes a core layer, a plurality of conductive pattern layers disposed on one side and the other side of the core layer, a plurality of insulating layers disposed on the one side and the other side of the core layer, and a plurality of via layers disposed on the one side and the other side of the core layer. The printed circuit board has a wiring region and a dummy region surrounding at least a portion outside of the wiring region on a plane. A metal ratio in the dummy region on one side and a metal ratio in the dummy region on the other side are different from each other.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Min Hee Yoon, Jong Eun Park, Sun Young Choi
  • Patent number: 11021991
    Abstract: A measurement system for determining an angular position of a component of a gas turbine engine includes one or more proximity sensors positioned at a fixed structure of the gas turbine engine and one or more sensor targets positioned at a rotatable component of the gas turbine engine. Each sensor target of the one or more sensor targets includes a target surface having a variable distance between the target surface and the proximity sensor with rotation of the rotatable component about a component axis of rotation. A measurement of distance between the proximity sensor and the target surface as measured by the proximity sensor is indicative of an angular position of the rotatable component relative to the component axis of rotation.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: June 1, 2021
    Assignee: RAYTHEON TECHNOLOGIES CORPORATION
    Inventors: Daniel J. Boudreau, Eli Cole Warren, Bryan J. Hackett
  • Patent number: 11018216
    Abstract: In accordance with an embodiment, an electrical element includes a first portion of a first dielectric material between a first portion of a first electrical conductor and a first portion of a second electrical conductor and a second portion of the first dielectric material between a second portion of the first electrical conductor and a first portion of a third electrical conductor. In accordance with another embodiment, an electrical component has a plurality of dopant regions formed in a semiconductor material, where the dopant regions include a plurality of dopant regions formed in a dopant region of the same conductivity type. A plurality of dopant regions of an opposite conductivity type are formed in corresponding dopant regions of the first conductivity type. A metallization system is formed over the semiconductor material, where a portion of the metallization system contacts the semiconductor material.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 25, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Richard Scott Burton, Karel Ptacek
  • Patent number: 11011457
    Abstract: A wiring substrate includes a first insulation layer containing insulating resin, a first through hole passing through the first insulation layer is the thickness direction, a pad formed within the first through hole, a second insulation layer containing insulating resin and laminated on a first surface of the first insulation layer, and a first wiring layer provided on the second insulation layer and connecting to the pad. A connecting surface of the pad that connects the first wiring layer includes a curved surface that curves in a protruding shape toward the first surface of the first insulation layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: May 18, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Koichi Nishimura, Noriyoshi Shimizu, Jun Furuichi
  • Patent number: 11004807
    Abstract: A method of manufacturing a laminated substrate including an insulation substrate comprised of ceramic, and a front electrode formed on a front surface of the insulation substrate, a semiconductor element being mountable on a front surface of the front electrode, including forming the front electrode on the front surface of the insulation substrate, and before or after the forming the front electrode, applying laser processing to the front surface of the insulation substrate at an outer peripheral area of the front electrode to modify a conductive property of the front surface of the insulation substrate to have electrical conductivity.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: May 11, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keisuke Yamashiro
  • Patent number: 11006526
    Abstract: According to one embodiment, a semiconductor storage device includes a board, a semiconductor memory component, and a capacitor. The hoard includes a first pad and a second pad. The first capacitor includes a first electrode and a second electrode. The first pad includes a first region and a second region. A direction from the first pad to the second pad is a first direction and a direction different from the first direction is a second direction. A difference between a dimension of the second region in the second direction and a dimension of the first electrode in the second direction is smaller than a difference between a dimension of the first region in the second direction and a dimension of the first electrode in the second direction.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Kengo Kumagai, Daigo Tanuma, Masahiro Mizuno
  • Patent number: 11002726
    Abstract: A test element analysis system for an analytical examination of a sample, in particular of a body fluid, is disclosed. The test element analysis system comprises an evaluation device with a test element holder for positioning a test element containing the sample and a measuring device for measuring a change in a measuring zone of the test element, the change being characteristic for an analyte. The test element holder contains contact elements with contact surfaces which allow an electrical contact between contact surfaces of the test element and the contact surfaces of the test element holder. The contact surfaces of the contact elements of the test element holder are provided with an electrically conductive surface containing metallic ruthenium.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 11, 2021
    Assignee: Roche Diagnostics Operations, Inc.
    Inventors: Kai Hebestreit, Sylvia Saecker, Klaus Thome, Werner Heidt
  • Patent number: 10999927
    Abstract: A ceramic substrate according to the present disclosure includes a plurality of electrodes on an electronic component mounting surface, and one or more interelectrode wires that connect the electrodes to each other on the electronic component mounting surface. A resist that extends across the interelectrode wire is disposed on the electronic component mounting surface.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: May 4, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yosuke Mino
  • Patent number: 10991648
    Abstract: An RDL structure including a first pad, a second pad, a third pad, a fourth pad, a first switch device, a second switch device, a third switch device, and a fourth switch device is provided. The first pad, the second pad, the third pad, and the fourth pad are separated from each other. The first switch device includes a first conductive layer and a second conductive layer separated from each other. The second switch device includes a third conductive layer and a fourth conductive layer separated from each other. The third switch device includes a fifth conductive layer and a sixth conductive layer separated from each other. The fourth switch device includes a seventh conductive layer and an eighth conductive layer separated from each other.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 27, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 10991845
    Abstract: A method for producing an optoelectronic semiconductor component and an optoelectronic semiconductor component are disclosed. In an embodiment the method include A) providing at least two source substrates, wherein each of the source substrates is equipped with a specific type of radiation-emitting semiconductor chip; B) providing a target substrate having a mounting plane, the mounting plane being configured for mounting the semiconductor chip; and C) transferring at least part of the semiconductor chips with a wafer-to-wafer process from the source substrates onto the target substrate so that the semiconductor chips, within one type, maintain their relative position with respect to one another, so that each type of semiconductor chips arranged on the target substrate has a different height above the mounting plane, wherein the semiconductor chips are at least one of at least partially stacked one above the other or at least partially applied to at least one casting layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 27, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Andreas Plößl, Siegfried Herrmann, Martin Rudolf Behringer, Frank Singer, Thomas Schwarz
  • Patent number: 10993315
    Abstract: A compensated via structure is utilized in a multi-layer printed circuit board (PCB) stackup to improve the radio frequency (RF) transmission performance of the PCB. The compensated via structure includes a compensating structure and a central via surrounded by multiple grounding posts, wherein both ends of the central via are connected to the input and the output transmission lines through pads. The compensating structure is within a ground plane located in between of the two layers within which the input and output transmission lines are. The increased coupling between the central via and the grounding posts and between the compensating structure and the ground plane results in reductions in both return and insertion losses and contributes to the improved RF transmission performance.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 27, 2021
    Assignee: AvL Technologies, Inc.
    Inventors: Ian J. Timmins, Keith Edenfield, Bruce Barratt, Alan Ellis
  • Patent number: 10993312
    Abstract: A printed circuit board (PCB) for an information handling system includes first and second signal vias, and a quantity of ground vias. The first signal via is separated from the second signal via by a first distance. The ground vias are grouped into pairs and each ground via of each pair is separated from one of the first or second signal vias by a second distance. The location of the ground vias in terms of an angle between the ground vias is given as an expression relating the first distance, the second distance, and the quantity of ground vias.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 27, 2021
    Assignee: Dell Products L.P.
    Inventors: Sanjay Kumar, Bhyrav M. Mutnury
  • Patent number: 10976879
    Abstract: A method of manufacturing a touch panel includes forming a first touch electrode layer including first touch electrodes, first touch traces and first pins, and the first pins are located in the first pin bonding area of the touch panel. The method further includes depositing an interlayer insulating layer by using a first mask including a first shielding structure, and the first shield structure is configured to shield a first pin bonding area. The method further includes forming a second touch electrode layer including second touch electrodes, second touch traces and second pins, and the second pins are located in a second pin bonding area of the touch panel.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: April 13, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Weinan Dai, Hwang Kim, Yangsheng Liu, Mengxia Kong
  • Patent number: 10959328
    Abstract: A wiring substrate includes: a wiring structure that includes a wiring layer and an insulating layer laminated; a plurality of first posts that are formed along a periphery of a predetermined area on a surface of the wiring structure, and that protrude out from the surface of the wiring structure; and a second post that is connected to the wiring layer at a position surrounded by the first posts, and that protrudes out from the surface of the wiring structure. The first posts are formed such that a post arranged at a central portion of a side constituting the periphery of the predetermined area is lower in height from the surface of the wiring structure than posts arranged at both ends of the side.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: March 23, 2021
    Inventors: Naoki Kobayashi, Kei Murayama, Mitsuhiro Aizawa, Shota Miki
  • Patent number: 10957974
    Abstract: The present disclosure discloses an antenna base for fixing an antenna body on a casing. The antenna base includes a base plate and a slot structure. The base plate is fixed on the casing. The slot structure includes a first side wall, a second side wall, and at least one welding structure. The first side wall and the second side wall are connected to the base plate and opposite to each other. An accommodating slot is formed between the first side wall and the second side wall for accommodating the antenna body. The at least one welding structure is disposed on the first side wall and for welding with the antenna body. In such a way, the antenna base is suitable for various antenna bodies with different structures according to practical demands without redesigning different molds for different antenna bases, which effectively reduces manufacturing cost.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: March 23, 2021
    Assignee: Wistron Corporation
    Inventors: Chung-Ta Yu, I-Hsiang Wang
  • Patent number: 10943795
    Abstract: A method of joining a semiconductor die to a passive heat exchanger can include applying a bond enhancing agent to a semiconductor device; creating an assembly that includes a thermal interface disposed on the semiconductor device such that a first major surface of the thermal interface material is in touching relation with the bond enhancing agent on the semiconductor device, and a heat exchanger disposed in touching relation with a second major surface of the thermal interface material; and reflowing the assembly such that the thermal interface bonds the heat exchanger to the semiconductor device. Embodiments can use the ability of indium to bond to a non-metallic surface to form the thermal interface, which may be enhanced by a secondary coating on either or both joining surfaces.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 9, 2021
    Assignee: INDIUM CORPORATION
    Inventors: Ross B. Berntson, James E. Hisert, Robert N. Jarrett, Jordan P. Ross
  • Patent number: 10939557
    Abstract: An organic light emitting display apparatus is provided that includes a display panel, a first source printed circuit board connected to the display panel in a first direction, and including a first memory disposed in an area of first source printed circuit board, a second source printed circuit board connected to the display panel in the first direction, and a control printed circuit board disposed between the first source printed circuit board and the second source printed circuit board, and connected to each of the first source printed circuit board and the second source printed circuit board. Here, a direction in which the control printed circuit board and the first source printed circuit board are connected and a direction in which the control printed circuit board and the second source printed circuit board are connected are a second direction different from the first direction.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: March 2, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: JinSol Choi, ByungChan Song, ChangIn Kim, YongKyu Park
  • Patent number: 10932359
    Abstract: A circuit board and an electrical connector with the same are disclosed in the present invention. The circuit board includes a first line layer, a first insulating layer, a second line layer, an insulating substrate, a third line layer, a second insulating layer and a fourth line layer, which are stacked from top to bottom. A first metal line and a second metal line are formed on the first line layer and the second line layer, respectively, and together constitute a first differential line pair. A third metal line and a fourth metal line are formed on the third line layer and the fourth line layer, respectively, and together constitute a second differential line pair. Two metal lines constituting each differential line pair are arranged up and down and have different widths, thereby reducing signal crosstalk between adjacent differential line pairs.
    Type: Grant
    Filed: October 13, 2019
    Date of Patent: February 23, 2021
    Assignee: OUPIIN ELECTRONIC (KUNSHAN) CO., LTD.
    Inventor: Hsin Chih Chen
  • Patent number: 10919199
    Abstract: A composite component and methods for producing a composite component are described herein. In some aspects, a method for producing a composite component may include molding a body from a plastic material, such that the molded body has at least one recess arranged adjacent to at least one respective projection. This method may also include pressing the at least one respective projection such that the plastic material of the molded body is thereby displaced into an opening-side region of the at least one recess adjacent thereto. The method may further include introducing flowable filler material into the at least one recess and solidifying the filler material. The filler material may be an electrically conductive filler material.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: February 16, 2021
    Assignee: OSRAM Beteiligungsverwaltung GmbH
    Inventor: Karl Roeder
  • Patent number: 10921657
    Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals in the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: February 16, 2021
    Assignee: Japan Display Inc.
    Inventors: Hideaki Abe, Yasuhito Aruga, Hiroyuki Onodera, Hiroki Kato, Yasushi Nakano, Hitoshi Kawaguchi, Keisuke Asada
  • Patent number: 10921661
    Abstract: Embodiments of the present disclosure provide a color filter substrate and a method of manufacturing the same, and a display panel. The color filter substrate includes a base substrate and a light shielding pattern on the base substrate. The light shielding pattern is provided with a groove, which divides the light shielding pattern into an outer light shielding sub-pattern corresponding to a peripheral region of the color filter substrate and an inner light shielding sub-pattern arranged at a position corresponding to a display area of the color filter substrate; an electrically conductive pattern is provided in at least part of a region in the groove and electrically connected with the inner light shielding sub-pattern and/or the outer light shielding sub-pattern.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 16, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Peirong Huo, Yezhou Fang, Shicheng Sun, Jingyi Xu
  • Patent number: 10923305
    Abstract: A no-voltage output and voltage output switching circuit includes an actuator connection terminal block including a plurality of ports each including a first pin, a second pin, and a third pin to which an actuator is connected, a power connection terminal block including a voltage terminal and a common terminal to which a power supply is connected, first relays, and second relays. The common terminal is connected to the second pin of each of the plurality of ports. The first relay enables connection between the first pin of a corresponding port among the plurality of ports and the third pin of the corresponding port. The second relay corresponding to the port corresponding to the first relay enables connection between the first pin of the port and the voltage terminal.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: February 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Wataru Hamamoto
  • Patent number: 10923456
    Abstract: A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 16, 2021
    Assignee: Cerebras Systems Inc.
    Inventor: Jean-Philippe Fricker
  • Patent number: 10901027
    Abstract: Embodiments relate to testing LEDs by applying a voltage difference between anode electrodes and cathode electrodes of the LEDs using transistors and probe pads and determining whether the LEDs satisfy a threshold level of operability. A final substrate has transistors that apply the voltage difference to the LEDs via conductive traces and probe pads during testing mode. A gate voltage is applied to gate terminals of the transistors, a first voltage is applied to anode electrodes of the LEDs, and a second voltage is applied to cathode electrodes of the LEDs. After applying the voltages, turning on of the LEDs is observed. Embodiments also relate to testing current leakage in the final substrate with the transistors and the LEDs.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: January 26, 2021
    Assignee: Facebook Technologies, LLC
    Inventor: Ilias Pappas
  • Patent number: 10903592
    Abstract: A memory card includes a substrate, first row terminals and second row terminals. The substrate has a first pair of side edges extending in a first direction and a second pair of side edges extending in a second direction perpendicular to the first direction. The first row terminals are arranged adjacent to an insertion side edge of the substrate, the first row terminals including a first power terminal, the insertion side edge being one of the first pair of side edges. The second row terminals are arranged further from the insertion side edge than the first row terminals, the second row terminals including a second power terminal. At least one recessed terminal among the first and second row terminals includes a recess area in an exposed surface of the at least one terminal.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: January 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-wan Koh, Seok-heon Lee, Seok-jae Han
  • Patent number: 10905003
    Abstract: The present invention relates generally to electric circuit testing, building, or implementing using a breadboard-style printed circuit board (PCB). Aspects of the present invention include eliminating the need to use hookup wires when building and testing electric circuits on PCBs. In one or more embodiments, a PCB system having rows and columns of signal tie points connected in a breadboard layout and using an embedded wire and a solder bridge to form partial connections between signal tie points may be built. In one or more embodiments, an embedded wire and solder bridge is capable of connecting a column of signal tie points, and/or an embedded wire and solder bridge is capable of connecting a power rail to a signal tie point. Thus, a circuit may be implemented and tested by applying a small amount of solder to the solder bridge without the need for hookup wire.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 26, 2021
    Inventor: Samuel P Kho
  • Patent number: 10896633
    Abstract: To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: January 19, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi Umezaki
  • Patent number: 10896838
    Abstract: An electrostatic chuck includes a base, a dielectric plate on the base, a chuck electrode in the dielectric plate, and a lower heater section including lower heaters in the dielectric plate between the chuck electrode and the base, and a lower ground electrode between the lower heaters and the base. The chuck further includes an upper heater section including upper heaters between the lower heaters and the chuck electrode, and a upper ground electrode between the upper heaters and the lower heaters, and a plurality of via contact electrodes connecting the upper ground electrode into the lower ground electrode.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minsung Kim, Myoung Soo Park, Dougyong Sung, Yun-Kwang Jeon
  • Patent number: 10897816
    Abstract: A rigid-flex circuit board includes a core substrate, a first adhesive layer, and a first outer conductive circuit layer. The core substrate includes a first and a second base layer, a first and a second conductive circuit layer respectively on the first and second base layer, and an insulating layer between the first and second base layer. The first and second conductive circuit layer are embedded in the insulating layer. The first adhesive layer is on the first base layer and defines a first opening which exposes the first opening. The first outer conductive circuit layer is on the first adhesive layer and defines an opening aligned with the first opening. A portion of the core substrate located within the first opening is defined as a flexible board section, and the portions of the core substrate located outside of the first opening are defined as a hard board section.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: January 19, 2021
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Tzu-Chien Yeh, Lin-Jie Gao
  • Patent number: 10888941
    Abstract: When a distance between an end portion of a brazing material and a downward extended line of a side surface of an insulating substrate is taken as “a”, and a distance between an end portion of a solder resist on the side of a solder and the downward extended line of the side surface of the insulating substrate is taken as “b”, the positional relationship a<b is satisfied. The position of the end portion of the solder is regulated by the solder resist, and the position of the end portion of the brazing material on the side of the side surface of the insulating substrate is closer to the side of the side surface of the insulating substrate than to the position of the end portion of the solder on the side of the side surface of the insulating substrate.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: January 12, 2021
    Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
    Inventors: Daichi Kawamura, Toru Masuda, Junpei Kusukawa, Naoki Sakurai