With Particular Conductive Connection (e.g., Crossover) Patents (Class 174/261)
  • Patent number: 10438883
    Abstract: A wiring board includes an insulator layer having a top surface, and a plurality of pads arranged in a pad arrangement region on the top surface of the insulator layer. The pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density. At least one dummy pad is arranged juxtaposed to at least one of the second plurality of pads in the second region of the pad arrangement region.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 8, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kei Imafuji
  • Patent number: 10438814
    Abstract: An object is to provide a novel method in place of the above-described conventional technology, as a technique for obtaining a thin film with a wiring pattern applied. A method for manufacturing a wiring pattern according to the present invention is characterized in that the method includes: a laminate forming step of forming a laminate by bringing a first member that has a resist layer and a metal layer formed on the resist layer into contact with a second member that includes a substrate; a resist layer patterning step of subjecting the resist layer to patterning; and an etching step of selectively removing the metal layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 8, 2019
    Assignee: NIKON CORPORATION
    Inventors: Makoto Nakazumi, Yasutaka Nishi, Kei Nara
  • Patent number: 10427585
    Abstract: An electrical power supply device for at least one light source of the light emitting diode type and at least one electronic component, including a circuit for driving the electrical power supply of the light source or each light source, the drive circuit including at least one electrical conductor track and a housing for accommodating an insert, and an insert in an electrically conducting material, the insert being inserted in the accommodation housing and including a first end portion electrically connected to the conductor track, and a second end portion suited to being electrically connected to at least one electronic component so as to supply electrical power to the electronic component.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 1, 2019
    Assignee: VALEO ILUMINACION
    Inventors: Jose-David Roldan, Miguel-Angel Pena, Antonio Domingo Illan
  • Patent number: 10431542
    Abstract: An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier liner that is located in an opening present in an interconnect dielectric material layer. An interconnect metal or metal alloy structure is present on physically exposed sidewalls of the seed enhancement spacer and on the physically exposed horizontal surface of the diffusion barrier liner.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Joseph F. Maniscalco, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10408420
    Abstract: A light emitting device includes a light emitting element with first and second electrodes formed on the same surface side; a base with first and second conductive members, each including a wide part facing the an electrode and a narrow part extending away from the wide part; first and second bonding members each electrically connecting a corresponding electrode with a conductive member, and continuously covering the wide and narrow parts of a corresponding conductive member; and one or more light reflecting members at least partially covering the conductive members.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 10, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Kazuhiro Kamada
  • Patent number: 10412841
    Abstract: A FPCB includes a base layer defining at least one first through hole. A conductive paste block is formed in each first through hole. Each conductive paste block includes a first and a second end portion. The base layer has opposite surfaces, and a first conductive wiring layer is formed on each surface of the base layer. The first end portion at least protrudes from the base layer and is exposed from the first conductive wiring layer. An insulating layer and a second conductive wiring layer are formed on each first conductive wiring layer. At least one second through hole is defined in each insulating layer. The second through hole positioned near the first end portion extends to the first end portion and forms a recess. A conductive via is formed in each second through hole and the corresponding recess, and is electrically connected to the conductive paste block.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 10, 2019
    Assignees: Avary Holding (Shenzhen) CO., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventor: Tzu-Chien Yeh
  • Patent number: 10395832
    Abstract: A method of manufacturing an electronic component includes forming a component body into which elements are built; and a metal plate electrode that is joined to the component body by conductive paste so as to be electrically coupled to the elements, the metal plate electrode exceeding in size a surface of the component body onto which the conductive paste is deposited.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 27, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tomokazu Nakashima, Masayuki Itoh, Yoshinori Mesaki
  • Patent number: 10396339
    Abstract: A bi-metal tab includes an internal tab segment that can be coupled to a battery cell terminal within an interior of the cell and an external tab segment that can be coupled to an element external to the cell. One tab segment includes a pin tab segment that comprises a pin, and another tab segment includes a socket tab segment comprised of a separate metal material, that comprises a socket. The socket can be at least partially enclosed, on at least two opposing sides, by the structure of the socket tab segment, and the socket and pin of the separate segments can be configured to couple, to form the tab, where at least two surfaces of the pin are in flush contact with the socket tab segment structure. A protection layer that restricts electronic transport across the tab based on exposure to particular physical conditions can be included between the tab segments.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 27, 2019
    Assignee: Apple Inc.
    Inventors: Qingcheng Zeng, Donald G. Dafoe, Andrew Chu, Ashley S. Harvey, Junwei Jiang
  • Patent number: 10383221
    Abstract: An aspect of the present invention makes it possible to reduce stress at a boundary between a coverlay and a terminal section of a flexible circuit board and reduce the possibility of disconnection in the terminal section in the flexible circuit board. An aspect of the present invention provides a flexible circuit board including: a reinforcing plate bonded to a whole of a terminal section and a portion of a coverlay; and a flexible plate including a holding portion and a bonding portion, the flexible plate bonding to the coverlay via only the bonding portion, the flexible plate being spaced apart from the reinforcing plate.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Ryohsuke Sugiyama, Takayuki Yanagi
  • Patent number: 10374313
    Abstract: A multilayer electronic component includes a body and a coil. The body includes a plurality of sheets each containing magnetic powder particles. The coil includes an uppermost coil pattern disposed on a top surface of an uppermost sheet among the plurality of sheets, a lowermost coil pattern disposed on a bottom surface of a lowermost sheet among the plurality of sheets, and side coil patterns disposed on edges of central sheets disposed between the uppermost sheet and the lowermost sheet in a central portion of the body. The magnetic powder particles have shape anisotropy, and a major axes of the magnetic powder particles are aligned with each other within the body. A multilayer chip antenna can include the multilayer electronic component.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soon Kwang Kwon, Chang Ryul Jung, Jung Wook Seo, In Gyu Kim
  • Patent number: 10371719
    Abstract: A printed circuit board (PCB) test fixture includes a substrate, a first insulation layer formed on the substrate, a conductor layer formed on the first insulation layer and electrically connected to the upper electrodes through at least one first connection member, a second insulation layer formed on the first insulation layer, and multiple conductive cones arranged on the second insulation layer in a matrix form. A part of the conductive cones is electrically connected to the conductor layer through at least one second connection member. The circuit layout of the conductor layer, the at least one first connection member and the at least one second connection member is employed to supply testing power to a part of the conductive cones and an adjustable arrangement of the conductive cones to enhance density of test probes upon electrical testing.
    Type: Grant
    Filed: April 17, 2016
    Date of Patent: August 6, 2019
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 10367117
    Abstract: The present invention provides an apparatus and a method for transferring micro light-emitting diodes. Said apparatus for transferring the micro light-emitting diodes comprises a main body, and a spraying module, a cooling module and a heating module disposed on said main body. The spraying module sprays metallic adhesive liquid onto the micro light-emitting diodes that wait to transfer, the cooling module cools the metallic adhesive liquid on the wait-to-transfer micro light-emitting diodes, thereby curing the metallic adhesive liquid to adhesively bond the main body with the wait-to-transfer micro light-emitting diodes together implementing the transfer of the micro light-emitting diodes, After transferred to reach the position, the cured metallic adhesive liquid is heated by the heating module, thereby melting the metallic adhesive liquid to separate the main body from the wait-to-transfer micro light-emitting diodes.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 30, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Macai Lu, Jiangbo Yao
  • Patent number: 10356904
    Abstract: The invention relates to an electronic device having an electrically isolating support structure, an electrically conducting conductor path on a surface of the support structure, and an electrically conducting contact structure which extends from the surface into the support structure and is electrically connected to the conductor path at a connection point, thereby forming a common conductor track. The conductor path and the contact structure transition into each other in an enlargement-free manner at the connection point.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: July 16, 2019
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellshaft
    Inventors: Johannes Stahr, Wolfgang Schrittwieser, Mike Morianz, Christian Vockenberger, Markus Leitgeb
  • Patent number: 10340056
    Abstract: A flat cable includes at least one cable portion and at least one rib portion. The at least one cable portion has a plurality of conductor wires arranged in parallel at predetermined intervals on a plane, and a coating portion that collectively covers the plurality of conductor wires arranged in parallel. The coating portion is made of an insulating resin. The at least one rib portion is provided in parallel with the cable portion on the plane. bus bar is to be fixed to the at least one rib portion and the at least one rib portion is made of only the same resin as the coating portion. A body including the at least one cable portion and the at least one rib portion is substantially bilaterally symmetrical in a cross-sectional structure of the body.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 2, 2019
    Assignee: YAZAKI CORPORATION
    Inventor: Takeshi Oshima
  • Patent number: 10339968
    Abstract: Provided is a base unit for use in a disk drive apparatus including a motor arranged to be capable of rotating about a central axis extending in a vertical direction. The base unit includes a base member arranged to extend radially to support the motor, and including a predetermined adhesion region and an outside region outside of the adhesion region; and a connector electrically connected to a wire arranged on the base member. The connector is adhered to the base member through an adhesive at the adhesion region of the base member. A wettability of the adhesive on the adhesion region is higher than a wettability of the adhesive on the outside region of the base member.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 2, 2019
    Assignee: NIDEC CORPORATION
    Inventors: Shingo Suginobu, Takumi Shimomura, Masahiro Imahori
  • Patent number: 10340576
    Abstract: A zero insertion loss directional coupler includes an input port, an antenna port, an isolation port, and a detect port. The coupler has a first signal trace, a second signal trace, and an inductive winding. The first signal trace is on one of two layers and is connected to the input port and the antenna port, while the inductive winding is on another one of the two layers. A first terminal of the inductive winding is connected to the isolation port. A first terminal of the second signal trace is connected to the detect port and a second terminal of the second signal trace is connected to a second terminal of the inductive winding.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 2, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Lisette L. Zhang, Oleksandr Gorbachov
  • Patent number: 10325853
    Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin, Ming-Da Cheng
  • Patent number: 10304787
    Abstract: Void formation in a semiconductor device is to be prevented. The semiconductor device includes a semiconductor element, signal lines, and a protective layer. In the semiconductor device, the semiconductor element is mounted on a substrate. The signal lines in the semiconductor device are connected to the semiconductor element on the substrate. Further, the protective layer in the semiconductor device is provided in an inter-line region interposed between both edges of two adjacent signal lines among the signal lines on the substrate.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: May 28, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Jun Suzuki
  • Patent number: 10297935
    Abstract: The invention discloses a circuit board output structure, which includes a power output section disposed on a circuit board and at least one metal connection stand electrically connected to the power output section. Each metal connection stand includes a first connection piece showing an included angle with respect to the circuit board. A plurality of connection holes for electrically connecting output wires are formed on the first connection piece. When it is required to change an output specification, the replacement can be more simple and convenient since the metal connection stand may be directly replaced without replacing the whole circuit board. Because the first connection piece has the included angle specified with respect to the circuit board, R angle and stress of the inserted output wires may be reduced to prevent the output wires from damage, detaching from the circuit board or having poor electrical contact after the assembly.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: May 21, 2019
    Assignee: 3Y POWER TECHNOLOGY (TAIWAN), INC.
    Inventors: Shao-Feng Lu, Chuan-Kai Wang
  • Patent number: 10293627
    Abstract: A printed matter is provided. The printed matter includes a porous printing medium and a printed layer. The printed layer contains silver and has a printed surface having an image clarity (2 mm), defined in Japanese Industrial Standards H8686-2, of 5.0 or more and a b* value in the range of from ?7.0 to +4.0.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: May 21, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Tatsuya Tomura, Yoshimasa Miyazawa, Takuya Fujita
  • Patent number: 10292263
    Abstract: The invention provides transient printed circuit board devices, including active and passive devices that electrically and/or physically transform upon application of at least one internal and/or external stimulus.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: May 14, 2019
    Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: John A. Rogers, Xian Huang
  • Patent number: 10290959
    Abstract: Provided is a cable mounting substrate for mounting plural cables each of which includes a center conductor, an insulation covering the center conductor and an outer conductor covering the insulation. The cable mounting substrate includes a plate-shaped base, a ground pattern that is arranged on the base and electrically connected to the outer conductor, and a solder member that is provided on the ground pattern and is melted to electrically connect and fix the outer conductor to the ground pattern. The solder member includes a recessed portion having a shape along an outer shape of the outer conductor.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Hitachi Metals, Ltd.
    Inventors: Takashi Kumakura, Hideharu Nagai
  • Patent number: 10283270
    Abstract: An electronic component includes: a component body into which elements are built; and a metal plate electrode that is joined to the component body by conductive paste so as to be electrically coupled to the elements, wherein the metal plate electrode exceeds in size a surface of the component body onto which the conductive paste is deposited.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: May 7, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tomokazu Nakashima, Masayuki Itoh, Yoshinori Mesaki
  • Patent number: 10262906
    Abstract: The method of manufacturing a functional inlay, comprises at least the steps of: (1) providing a substrate with a wire antenna embedded therein and with an aperture wherein two wire antenna portions are positioned over said aperture; (2) acquiring the positions and the dimensions of said wire antenna portions and of said aperture; (3) determining if the acquired positions and dimensions meet predetermined tolerances; (4) if the acquired dimensions and positions meet said tolerances, then placing a chip in fie aperture so that said wire portions are positioned over connections pads of said chip and then bonding said wire portions to said connection pads.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: April 16, 2019
    Assignee: ASSA ABLOY AB
    Inventors: Laurent Pellanda, Julien Richard
  • Patent number: 10257921
    Abstract: Embedded air gap transmission lines and methods of fabrication are provided. An apparatus having an air gap transmission line can include a first conductive plane, a core dielectric layer having a bottom surface in contact with the first conductive plane, a conductor having a bottom surface in contact with a top surface of the core dielectric layer, and a second conductive plane positioned over, and spaced apart from, a top surface of the conductor such that a gap separates the conductor from the second conductive plane. The top surface of the conductor is separated from the bottom surface of the second conductive plane by a first distance measured along an axis normal to the first conductive plane, and the bottom surface of the conductor is separated from the first conductive plane by a second distance greater than the first distance measured along the axis.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 9, 2019
    Assignee: Google LLC
    Inventors: Richard Roy, Pierre-luc Cantin, Teckgyu Kang, Woon Seong Kwon
  • Patent number: 10256175
    Abstract: A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on a first surface side of the laminate and second conductor pads on a second surface side of the laminate, and a solder resist layer interposed between the support plate and the laminate and having openings formed such that the openings are exposing the first conductor pads respectively. The laminate includes a resin insulating layer and has a first surface on the first surface side and a second surface on the second surface side on the opposite side with respect to the first surface of the laminate, the second conductor pads are embedded in the second surface of the laminate such that the second conductor pads have surfaces recessed from the second surface of the laminate respectively.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: April 9, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Hiroyuki Ban, Haiying Mei
  • Patent number: 10251277
    Abstract: A bridge section 12 is disposed in an area where mounting sections 11 are opposed to each other such that it is displaced toward a predetermined side. Accordingly, even if the line width of the bridge section 12 is formed larger than that in the related art, the self-alignment phenomenon can occur appropriately in a reflow process. It is thus possible to provide a resin-sealed module having high resin-charging properties and including a circuit substrate on which the bridge section 12 is not broken even if the size of a common land electrode 10 is reduced in accordance with a smaller size of a circuit component 5 and on which a sufficient gap between plural circuit components 5 mounted on the circuit substrate is reliably secured.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Tetsuya Oda, Tatsunori Kan, Kenichi Atsuchi
  • Patent number: 10244629
    Abstract: An apparatus that includes: a printed circuit board (PCB) that includes: a multilayer lamination of one or more ground layers, one or more power layers, and multiple signal layers; multiple vias that pass through one or more layers of the multilayer lamination, wherein a first via of the multiple vias includes: a first portion that has a first diameter, and a second portion that has a second diameter that is smaller than the first diameter, wherein a second via of the multiple vias includes: a third portion that has a third diameter, and a fourth portion that has a fourth diameter that is smaller from the third diameter; and wherein the first portion of the first via is adjacent to the fourth portion of the second via and the second portion of the first via is adjacent to the third portion of the second via is disclosed.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 26, 2019
    Assignee: Innovium, Inc.
    Inventors: Vittal Balasubramanian, Yongming Xiong
  • Patent number: 10242605
    Abstract: A display device and chip bonding method thereof are provided. The display device includes a flexible display panel and a chip bonded to the non-display area of the flexible display panel with the extension directions of individual bumps satisfying, depending on the area in which the bumps are located, the following requirements: in each row of bumps, at least the individual bumps in lateral zones have their extension lines on the same side converging at a same point on the reference line, and the two bumps belong to a same bump group have their extension lines respectively forming an angle with respect to the reference line, the angles being equal to each other.
    Type: Grant
    Filed: November 5, 2016
    Date of Patent: March 26, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Liqiang Chen, Hong Li
  • Patent number: 10234644
    Abstract: The optical-electrical printed circuit board disclosed herein includes a waveguide link assembly and a printed circuit board assembly. The printed circuit board assembly has first and second PCB layers between which optical waveguides of the waveguide link assembly are disposed. The end faces the optical waveguides are accessible through an access aperture in the printed circuit board assembly. An optical interconnector can be used to optically connect the optical waveguides to waveguides of an optical-electrical integrated circuit operably disposed on the printed circuit board assembly to form a photonic device. A waveguide bending structure can be used to bend the optical waveguides to facilitate optical coupling to the optical interconnector or directly to the waveguides of the optical-electrical integrated circuit. Methods of forming an optical-electrical printed circuit board, a photonic assembly and a photonic device are also disclosed.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Corning Optical Communications LLC
    Inventors: Douglas Llewellyn Butler, James Scott Sutherland
  • Patent number: 10229042
    Abstract: A technique relates comparing content. A first set of content in a first document and a second set of content in a second document are normalized. The first set of content in the first document and the second set of content in the second document are tokenized. The first set of content having been tokenized and the second set of content having been tokenized are compared in order to find differences in the second set of content with respect to the first set of content. The differences are compiled in a changes map. The differences in the changes map are analyzed to determine types of the differences in the first set of content and the second set of content, and predefined differences are to be excluded. A report of the differences is generated, and the report delineates the types of the differences while excluding the predefined differences.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Scott B. Greer, Rosalind Toy A. Radcliffe, Justin Z. Spadea, Timothy W. Wilson
  • Patent number: 10224682
    Abstract: A coaxial cable includes a coaxial wire in which an inner insulator, an outer conductor and a sheath are sequentially and coaxially provided around a center conductor, and a substrate having a surface on which a first contact pad and a second contact pad are arranged. The sheath is removed at one end portion of the coaxial wire by a predetermined length, so that the inner insulator and the outer conductor are exposed, and a tip end of the inner insulator is removed by a predetermined length, so that the center conductor is exposed. The exposed portion of the center conductor is soldered to the first contact pad with the exposed portion of the inner insulator being bent relative to the sheath, and the exposed portion of the outer conductor is soldered to the second contact pad with being bent in a direction different from the bending direction of the inner insulator. A part of the coaxial wire covered by the sheath is standing at an angle of 30° or greater relative to the surface of the substrate.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 5, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshimasa Watanabe, Kazuhiro Sato, Hitomi Yoshida
  • Patent number: 10219372
    Abstract: A flexible printed board electrically connected to an electronic component (for example, a liquid crystal panel) by thermal compression bonding, including a flexible substrate, a terminal portion formed on one surface of the flexible substrate and having a plurality of connection terminals to be connected to the electronic component, a wire portion having a plurality of wires formed on the other surface of the flexible substrate, and a plurality of through wires formed inside through holes penetrating the flexible substrate in a compression bonding connection area to the electronic component of the terminal portion to connect the connection terminals of the terminal portion and the respective wires of the wire portion.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: February 26, 2019
    Assignee: FUJIKURA LTD.
    Inventors: Yuki Ishida, Yusuke Nakatani
  • Patent number: 10191180
    Abstract: A detector assembly includes an insulating substrate, a printed circuit board, a resistive, plate, a drilled board, a drift volume, and a cathode. A surface of the printed circuit board exposed to the resistive plate includes printed circuit lines for measuring first and second coordinates of a charge event. A mechanical assembly applies a force between the insulating substrate and the resistive a plate to form an electrical contact between the printed circuit lines on the printed circuit board and the resistive plate without the use of an electrical adhesive.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 29, 2019
    Assignee: Lingacom Ltd.
    Inventors: David Yaish, Yosef Kolkovich, Amnon Harel
  • Patent number: 10185042
    Abstract: Provided are an array substrate of an X-ray detector, a digital X-ray detector including the same, a method for manufacturing an array substrate of an X-ray detector, and a method for manufacturing an X-ray detector. More specifically, provided are an array substrate of an X-ray detector which is capable of tracking a defective line with high accuracy since the array substrate includes a first line extended in a first direction, a second line extended in the first direction and apart from the first line, and a plurality of line identifiers provided between the first line and the second line, a digital X-ray detector including the same, a method for manufacturing an array substrate of an X-ray detector, and a method for manufacturing an X-ray detector.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 22, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: JaeHo Yoon, MoonSoo Kang, JaeKwang Lee, ShiHyung Park
  • Patent number: 10182134
    Abstract: An electronic device and its operating method are provided.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jin-Ho Lim, Yong-Hwa Kim, Sangyong Eom, Song Hee Jung, Gyun Heo, Dong-Il Son, Byounguk Yoon
  • Patent number: 10170882
    Abstract: A contact ribbon configured to connect a cable to a substrate includes a plurality of signal contacts, a ground plane, and at least one ground contact extending from the ground plane. The plurality of signal contacts are connected by a support member, and the support member is removable after the plurality of signal contacts are connected to the cable.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: January 1, 2019
    Assignee: SAMTEC, INC.
    Inventors: Keith R. Guetig, Brian R. Vicich, Andrew R. Collingwood, Travis S. Ellis
  • Patent number: 10170861
    Abstract: The present disclosure relates to a telecommunications connector having cross-talk compensations, and a method of managing alien crosstalk in such a connector. In one example, the telecommunications connector includes electrical conductors arranged in differential pairs and a circuit board with conductive layers that provide a cross-talk compensation arrangement for applying capacitance between the electrical conductors. The circuit board includes conductive paths that provide capacitive coupling and a conductive plate that intensifies capacitive coupling of the electrical conductors. In another example, the telecommunications connector is used with a twisted pair system.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: January 1, 2019
    Assignees: CommScope Technologies LLC, CommScope Connectivity UK Limited
    Inventors: Steven Richard Bopp, Bernard Harold Hammond, Jr.
  • Patent number: 10163871
    Abstract: An integrated device that includes a printed circuit board (PCB) and a package on package (PoP) device coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package that includes a first electronic package component (e.g., first die) and a second package coupled to the first package. The integrated device includes a first encapsulation layer formed between the first package and the second package. The integrated device includes a second encapsulation layer that at least partially encapsulates the package on package (PoP) device. The integrated device is configured to provide cellular functionality, wireless fidelity functionality and Bluetooth functionality. In some implementations, the first encapsulation layer is separate from the second encapsulation layer. In some implementations, the second encapsulation layer includes the first encapsulation layer.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Rajneesh Kumar, Chin-Kwan Kim, Milind Shah
  • Patent number: 10163791
    Abstract: It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Shuuichi Kariyazaki
  • Patent number: 10157822
    Abstract: Electrical interconnects having a non-linear conductive pathway, and related apparatuses and methods, are disclosed herein. In some embodiments, an electrical interconnect may include a non-linear conductive pathway electrically coupling top and bottom conductive portions. In some embodiments, an electrical interconnect may include a non-linear conductive pathway that propagates an electrical signal generating electromagnetic fields with an electrical field orthogonal to the direction of electromagnetic-wave propagation. In some embodiments, an electrical interconnect may include a non-linear conductive pathway portion and a linear conductive pathway portion. Also disclosed are connectors including an electrical interconnect having a non-linear conductive pathway.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Zhen Zhou, Tae Young Yang, Guosong Lin, Ling Zheng, Daqiao Du
  • Patent number: 10159143
    Abstract: A signal attenuation reduction structure for a flexible circuit board includes at least one conductive paste coating zone formed on surfaces of signal lines and an insulation layer formed on a dielectric layer of the flexible circuit board such that the conductive paste coating zone corresponds to at least one signal line or covers a plurality of signal lines. A resin-based conductive adhesive layer is formed on surfaces of the insulation layer and the conductive paste coating zone of the flexible circuit board. The resin-based conductive adhesive layer is pressed to bond between the conductive paste coating zone and a top insulation layer such that the conductive paste coating zone and the resin-based conductive adhesive layer achieve electrical connection therebetween.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 18, 2018
    Assignee: Advanced Flexible Circuits Co., Ltd.
    Inventors: Kuo-Fu Su, Chih-Heng Chuo, Gwun-Jin Lin
  • Patent number: 10153221
    Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 11, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Chan Yoo, Akshay Singh, Yi Xu, Liana Foster, Steven Eskildsen
  • Patent number: 10146071
    Abstract: Provided is an optical transmitter module. The optical transmitter module includes a substrate, a ground layer disposed on the substrate, an electro-absorption modulated laser (EML) chip disposed on the ground layer to generate an modulated optical signal, a ground structure disposed on the EML chip and electrically connected to the ground layer, a matching resistor disposed on the ground structure, and a first bonding wire disposed between the EML chip and the matching resistor to electrically connect the EML chip to the matching resistor.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 4, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-Tak Han, Sang Ho Park, Yongsoon Baek, Jang Uk Shin, Dong Hyo Lee, Dong-Hun Lee
  • Patent number: 10141222
    Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: November 27, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu
  • Patent number: 10127345
    Abstract: A method for determining a loading current of a circuit board is provided. In the method, outline positions of metal regions and hollowed regions in each of the metal regions are recorded. Metal widths corresponding to scan lines in circuit board are calculated in a sequence, so that a minimum metal width on each of the scan lines is acquired. According to the minimum metal width, a maximum loading current of each of the metal regions is calculated. In addition, a method and a system for filtering manufacturers are provided. A processing apparatus of the system analyzes the maximum loading current and manufacturing process parameters of the circuit board, calculates a weight score of a manufacturing process capability parameter table of each manufacturer according to the maximum loading current and manufacturing process parameters, and filtering the manufacturers to produce the best fit manufacturer list.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: November 13, 2018
    Assignee: Wistron Corporation
    Inventors: Ruey-Rong Chang, Wen-Jui Kuo, Feng-Ling Lin, Tzu-Heng Yeh
  • Patent number: 10126110
    Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: November 13, 2018
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Sandor Farkas, Stuart Allen Berke
  • Patent number: 10111343
    Abstract: Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: October 23, 2018
    Assignee: FINISAR CORPORATION
    Inventors: Henry Meyer Daghighian, Steven C. Bird, YongShan Zhang
  • Patent number: 10097030
    Abstract: A method for packaging a semiconductor device used in an electronic apparatus having wireless charging function is provided. The method includes coupling a semiconductor device and a coil over a redistribution layer. The method further includes forming a molding material over the semiconductor device and the coil. The method also includes forming a conductive metal slot over the molding material. An opening is formed on the conductive metal slot for allowing magnetic flux to pass through.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Hua Yu, Hao-Yi Tsai, Tzu-Sung Huang, Ming-Hung Tseng, Hung-Yi Kuo
  • Patent number: 10091873
    Abstract: An apparatus comprising a printed circuit board (PCB) that includes: a multilayer lamination of layers; vias on a surface of the PCB; and bonding pads that couple a ball grid array of an integrated circuit (IC) package to layers through the vias, wherein the bonding pads includes: first bonding pads in a first area of the PCB, each first bonding pad being coupled to a via of the vias in the first area, second bonding pads arranged in a second area of the PCB, each second bonding pad being coupled to a via of the vias in the second area, and third bonding pads arranged in a third area of the PCB, each third bonding pad being coupled to two or more vias of the vias in the third area, wherein the third area is located between the first area and the second area is disclosed.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 2, 2018
    Assignee: Innovium, Inc.
    Inventor: Yongming Xiong