With Particular Conductive Connection (e.g., Crossover) Patents (Class 174/261)
  • Patent number: 10799147
    Abstract: A wiring assembly includes a differential input port, a differential output port, and first and second pairs of electrical leads. The differential input port is configured to receive a differential signal from a sensor at a first end of the wiring assembly. The differential output port is configured to output the differential signal at a second end of the wiring assembly. The first and second pairs of electrical leads convey the differential signal from the first end to the second end, and are connected to one another at the first end and at the second end in a configuration that cancels pickup of an ambient magnetic field by the wiring assembly.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Biosense Webster (Israel) Ltd.
    Inventors: Sharona Ben Shoshan, Eden Kidishman, Vadim Gliner
  • Patent number: 10798818
    Abstract: A power supply includes a main circuit board and a multilayer power transmission board for transmitting power from one area of the main circuit board to another area of the main circuit board. The main circuit board includes a power input connector having power connections. The multilayer power transmission board includes conductive layers electrically coupled to the power connections of the power input connector, and a dielectric medium positioned between each of the conductive layers. The conductive layers of the multilayer board may include at least two conductive neutral layers and at least two conductive line layers positioned in an alternating configuration. Other example power supplies, multilayer boards and methods of manufacturing power supplies are also disclosed.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: October 6, 2020
    Assignee: Astec International Limited
    Inventors: Prabou Ranganathan, Norman Oliva
  • Patent number: 10796835
    Abstract: Embodiments of electronic devices, such as integrated circuit (IC) packages are disclosed. In one embodiment, an electronic device includes a first substrate and a second substrate. The first substrate has a first substrate body and a first inductor portion integrated into the first substrate body. Additionally, the second substrate comprises a second substrate body and a second inductor portion integrated into the second substrate body. The second substrate is mounted on the first substrate such that such that the second inductor portion is positioned over the first inductor portion and such that the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor. By using two substrates, the 3D inductor can be increased in height while still allowing the substrates to be miniaturized and standardized for an IC package.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 6, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Michael F. Zybura, George Maxim, Dirk Robert Walter Leipold, John August Orlowski, Baker Scott
  • Patent number: 10791627
    Abstract: A pad 11 is disposed at an end point of a first wiring 17 provided on a board 15, is connectable to one of N (N: an integer of two or more) wirings provided on the board 15 via a resistor or a conductor, and has (N+1) sides that are disposed by deforming respective sides of an equilateral polygon having (N+1) sides into convex sides each having a radius of curvature that is larger than a radius of curvature of a circumscribed circle of the equilateral polygon.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 29, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Daiki Sato
  • Patent number: 10790236
    Abstract: A wiring substrate includes a first substrate including a wiring layer and a solder resist layer that partially covers the wiring layer. The solder resist layer includes a circular opening partially exposing the wiring layer and a support partially covering the wiring layer within the opening. The wiring layer includes a first connection pad exposed in the opening and formed by a portion of the wiring layer located at an outer side of the support. The wiring substrate further includes a cylindrical connection pin and a bonding member that bonds a first end surface of the connection pin and the first connection pad located in the opening.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 29, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Sachiko Oda, Daisuke Takizawa, Yu Karasawa, Hiroaki Taniguchi
  • Patent number: 10751922
    Abstract: The present disclosure provides a metal-resin composite and a preparation method. The metal-resin composite includes a metal substrate; a porous resin layer formed on the metal substrate; a plastic layer formed on the porous resin layer; and a pore passage. The pore passage passes through the porous resin layer and extends inside the metal substrate, and the plastic layer fills in the pore passage to bond with the metal substrate.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 25, 2020
    Assignee: BYD COMPANY LIMITED
    Inventors: Jingna Cui, Xiulin Lai, Wenhai Luo
  • Patent number: 10748882
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • Patent number: 10748889
    Abstract: According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Matthew Berzins, Andrew Paul Hoover, Christopher Alan Peura
  • Patent number: 10736207
    Abstract: A wiring assembly includes a differential input port, a differential output port, and first and second pairs of electrical conductors. The differential input port is configured to receive a differential signal from a sensor at a first end of the wiring assembly. The differential output port is configured to output the differential signal at a second end of the wiring assembly. The first and second pairs of electrical conductors are laid out in a three-dimensional (3D) crossover configuration relative to one another and configured to conduct the differential signal from the first end to the second end, and to cancel pickup of a magnetic field by the wiring assembly. The electrical conductors of each pair are connected to one another at the first end and at the second end.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Biosense Webster (Israel) Ltd.
    Inventors: Yevgeny Bonyak, Michael Levin, Eyal Rotman, Alek Vilensky
  • Patent number: 10729008
    Abstract: A flexible printed circuit board according to an embodiment of the present invention includes an insulative base film; and a conductive pattern provided on at least one surface of the base film and including a wiring line including a bent portion having an angle of greater than or equal to 60° or a branched portion having an angle of greater than or equal to 60° in plan view. The wiring line is provided with a relaxation structure that relaxes stress concentration at the bent portion or the branched portion. The relaxation structure is structured such that the wiring line constitutes a wide wiring line or a dense wiring line group in a region in which a distance from the bent portion or the branched portion is less than or equal to 5 times a minimum width of the wiring line. The wide wiring line has a wiring line width that is greater than or equal to twice the minimum width of the wiring line.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 28, 2020
    Assignee: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Hiroshi Ueda, Kousuke Miura, Kou Noguchi
  • Patent number: 10729050
    Abstract: Systems and methods for fine pitch component placement on printed circuit boards are described. In one embodiment, a printed circuit board includes multiple vias and multiple of electrically conductive pads. The multiple vias include at least a first via and a second via. The multiple electrically conductive pads include a first pad and a second pad. The first pad and/or the second pad may include an electrically conductive material such as copper, silver, gold, or another conductive material. In some cases, the first pad and the second pad each have a reduced width portion positioned between and spaced apart from the first via and the second via.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 28, 2020
    Assignee: Seagate Technology LLC
    Inventors: Vimal Cyril, Subramanian Ramanathan
  • Patent number: 10721823
    Abstract: Method of manufacturing laminate body by: curing thermosetting resin composition on a support; laminating the curable resin onto a substrate; heating the laminate; forming a via hole in the cured resin layer; peeling the supporting body from the cured composite; performing a second heating of the cured composite; removing resin residue in the via hole of the cured composite; and forming a conductor layer on an inner wall surface of the via hole by electroless plating or a combination of electroless plating and electrolytic plating.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Makoto Fujimura, Youhei Tateishi
  • Patent number: 10716207
    Abstract: An apparatus comprising a printed circuit board (PCB) that includes: a multilayer lamination of layers; vias on a surface of the PCB; and bonding pads that couple a ball grid array of an integrated circuit (IC) package to layers through the vias, wherein the bonding pads includes: first bonding pads in a first area of the PCB, each first bonding pad being coupled to a via of the vias in the first area, second bonding pads arranged in a second area of the PCB, each second bonding pad being coupled to a via of the vias in the second area, and third bonding pads arranged in a third area of the PCB, each third bonding pad being coupled to two or more vias of the vias in the third area, wherein the third area is located between the first area and the second area is disclosed.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 14, 2020
    Assignee: Innovium, Inc.
    Inventor: Yongming Xiong
  • Patent number: 10709014
    Abstract: A multilayer substrate includes a differential line including first and second line conductors provided on or in a laminated body including base material layers. The differential line includes line portions and a connecting portion that connects the line portions. The connecting portion includes first parallel conductors extending in parallel or substantially in parallel with each other, first interlayer connecting conductors that connect the first parallel conductors in parallel, and connect the first line conductor to the first parallel conductors, second parallel conductors extending in parallel or substantially in parallel with each other, and second interlayer connecting conductors that connect the second parallel conductors in parallel, and connect the second line conductor to the second parallel conductors. The first parallel conductors cross the second parallel conductors as viewed in a laminating direction of the base material layers.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: July 7, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kuniaki Yosui
  • Patent number: 10709030
    Abstract: An electronic unit comprising a box defining a reception compartment for receiving an electronic module along two mutually opposite directions of an insertion axis, the compartment including electrical power supply means for powering the electronic module and connection means for connecting the electronic unit to the electronic module, these means extending onto a connection face forming part of the reception compartment and extending parallel to the insertion axis. An electronic module for mounting in a compartment of an electronic unit of the invention.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 7, 2020
    Assignee: SAFRAN ELECTRONICS & DEFENSE
    Inventors: François Guillot, Jean-Marc Blineau, Philippe Avignon, Serge Roques, Franck Albero
  • Patent number: 10709019
    Abstract: Methods, systems, and apparatus, including printed circuit boards (PCBs) with trace routing topologies are disclosed. In one aspect, a PCB includes an external layer that includes multiple integrated circuit (IC) installation regions that are each configured to receive an IC, a first trace routing layer having a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region, a second trace routing layer having a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, a first via region having one or more first vias that extend from the first trace routing layer to the second trace routing layer, and a second via region having one or more second vias that extend from the first trace routing layer to the second trace routing layer.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 7, 2020
    Assignee: Google LLC
    Inventors: Andrew Gerard Noonan, Sara Zebian
  • Patent number: 10698017
    Abstract: A test apparatus includes a host compliance printed circuit board having a first circuit plane and a second circuit plane separated by at least one dielectric layer. A first row of surface mount pads are disposed on the first circuit plane. The first row of surface mount pads includes a first pad and a second pad. A second and third row of surface mount pads are disposed on the first circuit plane. A first and second differential pair of circuit lines is disposed on the first circuit plane. The first differential circuit line has one end coupled to the first pad. The second differential circuit line has one end coupled to the second pad. The first and second differential pair of circuit lines extend from the first and second pads and between the second and third rows of surface mount pads.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 30, 2020
    Assignee: Dell Products, L.P.
    Inventor: Umesh Chandra
  • Patent number: 10699917
    Abstract: An object is to provide the structure of an ECU enabling resin to be filled without deformation of an electronic circuit board. A resin-sealed vehicle-mounted control device includes: a circuit board; a base member housing the circuit board; and resin filled between the circuit board and the base member. The base member has: a base portion fixing the circuit board; and a side wall opposed to the side surface side of the circuit board. The resin is provided at least between the circuit board and the base portion. The side wall has an opening at any position on the side of the base portion from a position opposed to the side surface side of the electronic circuit board.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: June 30, 2020
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Maki Ito, Toshiaki Ishii, Yoshio Kawai, Nobutake Tsuyuno, Yujiro Kaneko, Takayuki Fukuzawa, Masahiko Asano
  • Patent number: 10696048
    Abstract: A method of manufacturing an inkjet head substrate is provided. The inkjet head substrate includes an ink supply port having a through portion and a non-through portion, and the non-through portion is disposed at a position closer than the through portion to the energy generating element. The method includes disposing a mask having an opening that has a relatively large opening-width portion and a relatively small opening-width portion. The method also includes forming the through portion in the substrate at a position corresponding to the relatively large opening-width portion and the non-through portion in the substrate at a position corresponding to the relatively small opening-width portion by performing reactive ion etching on the substrate through the opening of the mask in one operation.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 30, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takayuki Kamimura, Masataka Kato, Hiroshi Higuchi, Atsunori Terasaki, Shuichi Tamatsukuri
  • Patent number: 10692829
    Abstract: A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Patent number: 10687415
    Abstract: A flexible printed circuit board is disclosed, which includes a pad portion, wherein the pad portion includes a pair of first signal pads formed in a first conductor layer and respectively connected with a pair of signal wires, a pair of second signal pads formed in a second conductor layer and electrically separated from a grounding layer; a pair of first grounding pads formed in the first conductor layer and electrically separated from the pair of signal wires, wherein: the pair of first signal pads is sandwiched between the pair of first grounding pads, and a pair of second grounding pads formed in the second conductor layer and connected with the grounding layer, wherein the pair of second signal pads are sandwiched between the pair of second grounding pads. A width of the first and the second signal pads is larger than that of the signal wires.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: June 16, 2020
    Assignee: DALIAN CANGLONG OPTOELECTRONICS TECHNOLOGIES CO., LTD
    Inventors: Hao Wang, Shun Zhang, Lin Cui, Wenchen Zhang, Chuanwu Liao
  • Patent number: 10676836
    Abstract: Some embodiments are directed to techniques for building single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while others use an intervening adhesion layer material. Some embodiments use different seed layer and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while others apply the materials in blanket fashion. Some embodiments remove extraneous material via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 9, 2020
    Assignee: Microfabrica Inc.
    Inventors: Adam L. Cohen, Michael S. Lockard, Kieun Kim, Qui T. Le, Gang Zhang, Uri Frodis, Dale S. McPherson, Dennis R. Smalley
  • Patent number: 10665151
    Abstract: A driver circuit carrier, a display panel, and a manufacturing method are provided. The driver circuit carrier includes a substrate, and a number of first pins arranged on at least one surface of the substrate. The first pins are arranged along a first reference line. An imaginary extending line of at least one of the first pins intersects with a second reference line perpendicular to the first reference line.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 26, 2020
    Assignees: KUNSHAN NEW FLAT PANEL DISPLAY TECHNOLOGY CENTER CO., LTD., KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventors: Xiuyu Zhang, Xiaofei Xue, Tao Xu, Xiangqian Wang, Zhan Sun
  • Patent number: 10658279
    Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 19, 2020
    Assignee: INTEL CORPORATION
    Inventors: Sanka Ganesan, Zhiguo Qian, Robert L. Sankman, Krishna Srinivasan, Zhaohui Zhu
  • Patent number: 10638945
    Abstract: An apparatus includes a substrate mechanically and electrically connected on one side of the substrate to multiple metallic probes in one or more arrays and includes the multiple metallic probes in the one or more arrays. In a method, multiple pits may be formed in an array on a first substrate. The pits have a pyramidal shape. A release layer is formed on the first substrate and covers surfaces of the pits. Probe tips are formed in the pits on the first substrate. The probe tips are formed from rigid conductive material. Multiple pillars are formed from rigid conductive material. The pillars are electrically and mechanically connected to a second substrate and to the probe tips. Release is caused of the probe tips from the first substrate, wherein the pillars and probe tips are connected to the second substrate and together form an array of rigid and conductive probes.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Yang Liu, Steven L. Wright
  • Patent number: 10645800
    Abstract: A high-frequency circuit board includes a first circuit structure, a second circuit structure, and a dielectric layer formed on the second circuit structure. The first circuit structure includes a first substrate layer and at least one first circuit layer. The at least one first circuit layer is formed on at least one surface of the first substrate layer. At least one receiving cavity is defined in the first substrate layer. A second circuit structure is embedded in the receiving cavity. The second circuit structure includes a second substrate layer, at least one second circuit layer embedded in the second substrate layer, and a plurality of support columns formed on the second substrate layer. A portion of the dielectric layer is filled into gaps between an inner wall of the receiving cavity and the second circuit structure. The support columns are embedded in the dielectric layer.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 5, 2020
    Assignees: Avary Holding (Shenzhen) Co., Limited., Hong Heng Sheng Electronical Technology (HuaiAn)Co., Ltd.
    Inventors: Yong-Quan Yang, Yong-Chao Wei
  • Patent number: 10636731
    Abstract: Disclosed are various embodiments that involve mechanically flexible interconnects, methods of making mechanically flexible interconnects, methods of using mechanically flexible interconnects, and the like.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: April 28, 2020
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Paul Kim Jo
  • Patent number: 10622386
    Abstract: The embodiments of the present invention provide a substrate, a chip on film and an electronic equipment. The substrate includes a plurality of first bonding pads arranged side by side along a first direction. Each first bonding pad has a first side edge and a second side edge arranged oppositely, which are arranged along the first direction. A third side edge and a fourth side edge of the first bonding pad are arranged oppositely and arranged along a second direction perpendicular to the first direction. The first side edge and second side edge of each first bonding pad are not parallel to each other.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: April 14, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hong Li, Liqiang Chen, Weifeng Zhou
  • Patent number: 10617018
    Abstract: A circuit board includes a board, circuitry provided on the board that supplies electric power to a motor, a positive-electrode-side power source terminal portion connected to a positive electrode terminal of the circuitry, and a negative-electrode-side power source terminal portion connected to a negative electrode terminal of the circuitry. The circuitry includes a first capacitor connected to the positive-electrode-side power source terminal portion, and a second capacitor connected to the negative-electrode-side power source terminal portion. The first and second capacitors are connected in series between the positive-electrode-side and the negative-electrode-side power source terminal portions. The board includes a through hole, at least a portion of which is between at least two of the first capacitor, the second capacitor, the positive-electrode-side power source terminal portion, and the negative-electrode-side power source terminal portion.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 7, 2020
    Assignee: NIDEC ELESYS CORPORATION
    Inventors: Kazuki Harada, Naoki Yamamoto
  • Patent number: 10606383
    Abstract: A touch sensor includes a sensing pattern which includes a first mesh pattern formed in a first direction and a second mesh pattern formed in a second direction, the second mesh pattern including isolated unit patterns, a bridge electrode connecting the neighboring isolated unit patterns of the second mesh patterns, an insulation layer disposed between the sensing pattern and the bridge electrodes, and an auxiliary mesh pattern disposed on or below at least one of the first mesh pattern and the second mesh pattern, the auxiliary mesh pattern being connected to at least one of the first mesh pattern and the second mesh pattern.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: March 31, 2020
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Byung Jin Choi, Dong Pil Park, Jae Hyun Lee
  • Patent number: 10604191
    Abstract: A vehicle frame construction or frame assembly and method for assembling a multi-material vehicle frame includes a first frame member formed of a first metal material and a second frame member formed of a second metal material that is dissimilar to the first metal material. The second frame member is joined to the first frame member via vaporizing foil actuator welding (VFAW).
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: March 31, 2020
    Assignee: Honda Motor Co., Ltd.
    Inventors: Timothy A. Abke, Duane Trent Detwiler
  • Patent number: 10608359
    Abstract: A connection structure between a flat cable and an electronic circuit board includes an electronic circuit board; a cable connection hole formed to penetrate the electronic circuit board; a plurality of internal contacts provided on an inner surface of the cable connection hole; and a flat cable provided with a plurality of contacts which correspond to the plurality of internal contacts of the cable connection hole and are exposed to one side surface of the flat cable. When one end of the flat cable is inserted into the cable connection hole of the electronic circuit board, the plurality of contacts of the flat cable are in contact with the plurality of internal contacts of the cable connection hole, respectively.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sung-soo Kim
  • Patent number: 10586782
    Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Clement J. Fortin, Christopher D. Muzzy, Brian W. Quinlan, Thomas A. Wassick, Thomas Weiss
  • Patent number: 10580720
    Abstract: A silicon interposer that includes an array, or pattern, of conductive paths positioned within a silicon substrate with a plurality of pins on the exterior of the substrate. Each of the pins is connected to a portion of the array of conductive paths. The array of conductive paths is configurable to provide a first electrical flow path through the substrate via a portion of the array of conductive paths or a second electrical flow path through the substrate. The electrical flow path through the substrate may be customizable for testing various die or chip layout designs. The electrical flow path through the substrate may be customizable by laser ablation of portions of the conductive paths, breaking of fuses along the conductive paths, and/or the actuation of logic gates connected to the conductive paths.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 3, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Bret K. Street, Owen R. Fay, Eiichi Nakano
  • Patent number: 10575413
    Abstract: Apparatuses and methods for forming serial advanced technology attachment (SATA) board edge connectors with electroplated hard gold contacts. One example method can include forming a tie bar on an inner layer of a printed circuit board (PCB), forming a trace on an outer layer of the PCB, forming a via, wherein the via electrically couples the tie bar to the trace, forming a contact coupled to the trace on the outer layer, and sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kurt B. Smith
  • Patent number: 10573655
    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: February 25, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. deVilliers
  • Patent number: 10564498
    Abstract: Display systems and related methods involving bus lines with low capacitance cross-over structures are provided. A representative display system includes: a first structure comprising: a plurality of scan lines extending in a first direction; and a plurality of data lines extending in a second direction and crossing over the scan lines at respective cross-over locations, each of the plurality of data lines having a pair of side walls spaced apart from each other at each of the cross-over locations, with each of the side walls exhibiting a height higher than portions of the data lines not located at the cross-over locations.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: February 18, 2020
    Assignee: A.U. VISTA INC.
    Inventor: Lee Seok Lyul
  • Patent number: 10564499
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: February 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Patent number: 10534890
    Abstract: An apparatus for detecting printed circuit board (“PCB”) design violations includes an analysis module that analyzes a position of a trace on a PCB design to determine conductivity of a design material over which the trace is being added and/or an electrical property of the trace at the position. The apparatus further includes an identification module that identifies, in real time, a void violation on the PCB design in response to the design material including a non-conductive material and/or a reference voltage violation on the PCB design in response to the position including a voltage and a notification module that notifies a user of the void violation and/or the reference voltage violation. At least a portion of said modules include hardware circuits, a programmable hardware device, and/or executable code stored on one or more non-transitory computer-readable storage media.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alberto Garza, Emile L. Kowalski, Julio A. Maldonado, Jose L. Rodriquez
  • Patent number: 10530083
    Abstract: In some embodiments, an apparatus comprises a biosensing garment and an electronics assembly. The biosensing garment includes a sensor, a conductive pathway, and a connection region including one or more connectors that are disposed on a PCB. The connection region is electrically coupled to the conductive pathway and the sensor. The connection region is further configured to be electronically coupled to the electronics assembly via at least one conductive contact. In some embodiments, the electronics assembly includes at least one conductive contact that is configured to be electronically coupled to at least one portion of the PCB.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 7, 2020
    Assignee: HONEYWELL SAFETY PRODUCTS USA, INC.
    Inventor: Thierry Dumont
  • Patent number: 10527509
    Abstract: A sensor such as a load cell includes a metal body containing the sensor electronics and flexure elements. Power is brought into the electronics and signals are taken out via header pins arranged in any of various groupings so as to extend through holes in the body. The pins are fixed by means of fused glass or ceramic material and the body is sealed to tolerate harsh environmental conditions.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 7, 2020
    Assignee: FUTEK Advanced Sensor Technology
    Inventors: Javad Mokhbery, Richard Walker, Maciej Lisiak
  • Patent number: 10528184
    Abstract: The invention includes a substrate, a touch sensor layer, an insulative film and a signal transmission layer. The touch sensor layer has sensing columns. Each sensing column has a first sensing electrode and second sensing electrodes. The first sensing electrode is connected to a first contact through a first transparent path. Each second sensing electrode is connected to a second contact through a second transparent path. The second contacts are arranged in the same order of the second sensing electrodes connected thereto. The insulative film covers the second contacts. The signal transmission layer has first signal wires, second signal wires and signal output terminals. Two end of each first signal wire are separately connected to the first contact and one of the signal output terminals. Each second signal wire connects the second contacts in a line and is connected to one of the signal output terminals.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 7, 2020
    Assignee: YOUNG FAST OPTOELECTRONICS CO., LTD.
    Inventors: Chih-Chiang Pai, Meng-Guei Lin, Chin-Fong Lin, Li-Yeh Yang, Chiu-Wen Chen
  • Patent number: 10518518
    Abstract: Smartcards with metal layers manufactured according to various techniques disclosed herein. One or more metal layers of a smartcard stackup may be provided with slits overlapping at least a portion of a module antenna in an associated transponder chip module disposed in the smartcard so that the metal layer functions as a coupling frame. One or more metal layers may be pre-laminated with plastic layers to form a metal core or clad subassembly for a smartcard, and outer printed and/or overlay plastic layers may be laminated to the front and/or back of the metal core. Front and back overlays may be provided. Various constructions of and manufacturing techniques (including temperature, time, and pressure regimes for laminating) for smartcards are disclosed herein.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: December 31, 2019
    Assignee: Féinics AmaTech Teoranta
    Inventors: David Finn, Mustafa Lotya, Darren Molloy
  • Patent number: 10510722
    Abstract: A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Weiming Chris Chen, Tu-Hao Yu, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Patent number: 10483222
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 19, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Eun Sook Sohn, In Bae Park, Won Chul Do, Glenn A. Rinne
  • Patent number: 10483156
    Abstract: A method includes electrically joining two or more semiconductor chips to a silicon bridge chip, and electrically joining the two or more semiconductor chips to a substrate structure, the silicon bridge chip extends into a recess in the substrate structure such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10477672
    Abstract: An electronic device includes a printed circuit board. The printed circuit board includes a plurality of different signaling planes and a plurality of different reference planes. A single ended via interconnects the plurality of different signaling planes. A return via interconnects the plurality of different reference planes. The electronic device includes a shared void that includes the single ended via and the return via.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: November 12, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Karl J. Bois
  • Patent number: 10470311
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 5, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Matthew Twarog, Hui He, Thomas W. Jetton
  • Patent number: 10470294
    Abstract: Methods and systems for reducing the number of, and values of, passive components, such as capacitors, in System-in-Package devices below vendor recommendations for an active component are provided.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: November 5, 2019
    Assignee: OCTAVO SYSTEMS LLC
    Inventors: Erik James Welsh, Peter Linder
  • Patent number: 10468362
    Abstract: A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: November 5, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto