Abstract: A method of producing a conductive-sheet-equipped article includes: forming electrodes on an adherend to obtain an electrode-equipped adherend; and stretching and sticking a sheet-shaped conductive member to the electrode-equipped adherend.

Abstract: A method for determining mutual coupling between adjacent communication transmission lines is disclosed. The method includes providing a first periodic signal to a first communication transmit end of a first communication transmission line; providing a second periodic signal to a second communication transmit end of a second communication transmission line, wherein the first communication transmission line is adjacent to the second communication transmission line; measuring a time of zero-crossing at a second communication receive end of the second communication transmission line compared with a zero-crossing of an ideal reference signal; and determining a mutual coupling level based on the time of zero-crossing on the second communication transmission line compared with a zero-crossing of an ideal reference signal that was measured.

Abstract: This disclosure provides a conductive circuit carrier module including a carrier and a conductive circuit film layer. The conductive circuit film layer is disposed on the carrier. The conductive circuit film layer has at least one conductive circuit structure including a vertical wire part and at least four horizontal wire parts. The vertical wire part extends along a thickness direction of the conductive circuit film layer. The at least four horizontal wire parts are connected to one another via the vertical wire part and extend along a direction substantially perpendicular to the vertical wire part. The at least four horizontal wire parts are symmetrically arranged or asymmetrically arranged with respect to the vertical wire part.

Abstract: A semiconductor chip (3) is bonded to an upper surface of an electrode substrate (1) via a first solder (2). A lead frame (5) is bonded to an upper surface of the semiconductor chip (3) via a second solder (4). An intermediate plate (6) is provided in the first solder (2) between the electrode substrate (1) and the semiconductor chip (3). A yield strength of the intermediate plate (6) is higher than yield strengths of the electrode substrate (1) and the first solder (2) within the whole operating temperature range of the semiconductor device.

Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.

Abstract: A printed circuit board includes: a first insulating layer; a via pad including a first layer embedded in the first insulating layer and a second layer disposed on the first layer; and a first via layer disposed on the via pad, wherein the second layer has a width decreasing in a direction away from the first layer in a stacking direction of the first and second layers.

Abstract: A connector attached multi-conductor cable includes a multi-conductor cable and a connector that includes a circuit board including first to third surfaces. The circuit board includes first pads provided on the first surface and connected to central conductors of wires; second pads provided on the first surface, arranged in a first direction parallel to the third surface, and connected to the first pads; a first ground layer provided between the first and second surfaces, and extending in a second direction parallel to the first surface and perpendicular to the first direction; and a conductive member provided apart from the first pads in the second direction with respect to the second pads, and connected to the first ground layer. The conductive member is positioned on the first surface side with respect to the first ground layer in a third direction perpendicular to the first surface.

Abstract: There is provided a semiconductor device that includes a wiring layer, a plurality of bonding layers arranged on the wiring layer and having conductivity, and a semiconductor element having a rear surface facing the wiring layer and a plurality of pads provided on the rear surface, and bonded to the wiring layer via the plurality of bonding layers, wherein the plurality of bonding layers are arranged in a grid shape when viewed along a thickness direction, wherein each of the plurality of pads is electrically connected to a circuit formed inside the semiconductor element and any of the plurality of bonding layers, and wherein at least one of the plurality of pads is located to be spaced apart from the plurality of bonding layers when viewed along the thickness direction.

Abstract: A printed circuit board includes a first substrate portion including a first insulating layer and a first wiring layer; and a second substrate portion disposed on the first substrate portion and including a second insulating layer, a pad disposed on the second insulating layer, and a first via penetrating through the second insulating layer and connecting the first wiring layer and the pad to each other. The first via has a boundary with each of the first wiring layer and the pad, and includes a first metal layer and a second metal layer disposed on different levels.

Abstract: A device for imaging within a body of a patient is provided. In one embodiment, the device includes a flexible elongate member that can be inserted into the body of the patient. The device also has an imaging assembly that is disposed at and extending a length of a distal portion of the flexible elongate member. The imaging assembly may include an array (302) of imaging elements that may have an outward surface and an inward surface. The imaging assembly may further include an integrated circuit (304) adjacent to the inward surface of the array of imaging elements. The device may further include a conductive plate (375) adjacent to and extending at least a portion of a length of the imaging assembly. The conductive plate may receive heat generated by at least one of the array of imaging elements or the integrated circuit.

Abstract: A method for forming a package structure is provided. The method includes forming a first molding compound layer surrounding a first interposer. The method also includes forming a first redistribution structure over a first side of the first interposer and the first molding compound layer. The method also includes bonding a first semiconductor die and a second semiconductor die to the first redistribution structure through a plurality of first connectors. The method also includes bonding a surface-mount device (SMD) to the first redistribution structure through a second connector. The method also includes forming a second redistribution structure over a second side of the first interposer opposite the first side of the first interposer. A top surface of the surface-mount device (SMD) is lower than top surfaces of the first semiconductor die and the second semiconductor die.

Abstract: A method for forming a printed circuit board includes: forming on a substrate a first conductive layer for a first edge connector pin and a first conductive layer for a second edge connector pin, wherein the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin are electrically coupled to one another via a first conductive layer for an electrical bridging element; electroplating a second conductive layer onto both the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin via a plating current conductor; and removing at least a portion of the electrical bridging element to electrically separate the first edge connector pin from the second edge connector pin.

Abstract: A system of generating targeted user lists using customizable avatar characteristics includes a messaging server system. The messaging server system includes an application server that generates a database of mutable avatar characteristics, a database of style categories, and a targeted user list. The application server then causes a media content item to be displayed on display screens of electronic devices associated with the set of user identifiers included in the targeted user list. Other embodiments are disclosed.

Abstract: An optical module, including: a first laser and a first laser chip for driving the first laser; a second laser and a second laser chip for driving the second laser; and a multi-layer circuit board, including a surface layer, a reference layer, and an intermediate layer provided between the surface layer and the reference layer, where a first row of edge connector pins and a second row of edge connector pins are disposed in at least one surface layer; the first row of edge connector pins are disposed to be closer than the second row of edge connector pins to a side edge, of the multi-layer circuit board, that is provided with an edge connector; and a region, of the intermediate layer, that corresponds to a data signal line pin in the second row of edge connector pins is a hollow region.

Abstract: A single-layer redistribution plate functioning as a space translator between a device under testing (“DUT”) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.

Abstract: The present invention discloses a substrate configured to receive a plurality of micro elements on a carrier board. The substrate comprises a body, a first conductive bump, and a second conductive bump. The body has a first surface, a transfer area is defined within the first surface, and a central portion and a peripheral portion is defined within the transfer area. The first conductive bump, disposed on the central portion, has a first volume. The second conductive bump, disposed on the peripheral portion, has a second volume. Wherein the first volume is different from the second volume.

Abstract: A circuit board structure includes a body, multiple first pads, a conductive assembly, multiple first engaging components, and multiple second engaging components. The body includes a first portion and a second portion integrally formed. A first surface of the first portion directly contacts a second surface of the second portion. A first region of the first surface protrudes from the second portion, and a second region of the second surface protrudes from the first portion. The first pads and the first engaging components are disposed on the first portion of the body and located in the first region of the first surface. The conductive assembly and the second engaging components are disposed on the second portion of the body and located in the second region of the second portion. The first pads are located between the first engaging components, and the conductive assembly is located between the second engaging components.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: An economical, efficient, and effective formation of a high resolution pattern of conductive material on a variety of films by polymer casting. This allows, for example, quite small-scale patterns with sufficient resolution for such things as effective microelectronics without complex systems or steps and with substantial control over the characteristics of the film. A final end product that includes that high resolution functional pattern on any of a variety of substrates, including flexible, stretchable, porous, biodegradable, and/or biocompatible. This allows, for example, highly beneficial options in design of high resolution conductive patterns for a wide variety of applications.

Abstract: An object is to provide a semiconductor material and coating having high solubility in solvents and having advantageous filling property, high heat resistance, and/or high etching resistance. Another object is to provide a method for manufacturing a semiconductor using the semiconductor material. Still another object is to provide a novel compound. Provided are: a semiconductor material consisting of a specific aromatic hydrocarbon ring derivative; methods for manufacturing a coating and a semiconductor using the semiconductor material; and a compound consisting of a specific aromatic hydrocarbon ring derivative.

Abstract: A touch panel including: a first electrode pattern arranged in a first direction, including a plurality of first electrode cells that are physically separated from each other; a second electrode pattern arranged in a second direction crossing the first direction, including a plurality of second electrode cells that are physically separated from each other; first touch signal lines connected to the first electrode cells; and second touch signal lines connected to the second electrode cells. The electrode patterns and the touch signal lines are arranged on the same layer on a substrate such that a first virtual connection line for connecting centers of second electrode cells of a first group corresponding to an n-th first electrode cell crosses a second virtual connection line for connecting centers of second electrode cells of a second group corresponding to an (n+1)-th first electrode cell.

Abstract: One example printed circuit board transmission line includes a substrate layer, a metal line, at least one first welding point, at least one first transmission medium, and a metal component that is configured to implement a grounding function. The metal line is plated on a surface of the substrate layer. The at least one first welding point is a welding point at which the metal line is connected to the at least one first transmission medium. The at least one first welding point is welded to the metal line and welded to the at least one first transmission medium. The metal component is welded to the at least one first transmission medium. At least one groove is provided on one side of the at least one first welding point.

Abstract: Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.

Abstract: A charging surface comprising multiple conductive regions can be used to charge an electronic device placed on it the surface so that electrodes on the device engage respective conductive regions of the surface. In order to distinguish such chargeable devices from short circuits and other spurious connections, the devices are required to demonstrate an anti-inversion characteristic, for example implemented with a MOSFET, across at least a pair of these electrodes. The surface can then be controlled so as to establish a text voltage across each pair of conductive regions in sequence, and look for pairs of conductive regions behaving as being coupled by such an anti inverter circuit. Relationships between every pair of conductive regions can be determined and recording, and the voltage level supplied to each conductive region set accordingly.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film and a metal layer disposed on at least one of surfaces of the base film. In the substrate for a printed circuit board, an amount of nitrogen present per unit area, the amount being determined on the basis of a peak area of a N1s spectrum in XPS analysis of a surface of the base film exposed after removal of the metal layer by etching with an acidic solution, is 1 atomic % or more and 10 atomic % or less.

Abstract: A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.

Abstract: A micro LED display panel includes a substrate, a plurality of first metal electrodes and a plurality of metal pads on a surface of the substrate, a connection layer on the substrate, a plurality of micro LEDs on a side of the connection layer away from the substrate. The connection layer includes conductive particles. Each of the micro LEDs is coupled to at least one of the first metal electrode. A side of each of the metal pads away from the substrate is coupled to some of the conductive particles in the connection layer to form a metal retaining wall. The metal retaining walls enhance structural strength of the micro LED display panel and avoid breakage of any of the micro LEDs.

Abstract: A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface.

Abstract: The present invention is directed to flexible conductive articles (600) that include a printed circuit (650) and a stretchable or non-stretchable substrate (610). In some embodiments, the substrate has a printed circuit on both sides. The printed circuit contains N therein a porous synthetic polymer membrane (660) and an electrically conductive trace (670) as well as a non-conducive region (640). The electrically conductive trace is imbibed or otherwise incorporated into the porous synthetic polymer membrane. In some embodiments, the synthetic polymer membrane is microporous. The printed circuit may be discontinuously bonded to the stretchable or non-stretchable substrate by adhesive dots (620). The printed circuits may be integrated into garments, such as smart apparel or other wearable technology.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.

Abstract: In some implementations, a substrate for coupling to an integrated circuit includes multiple layers. Each of the multiple layers has, in a particular region of the substrate, a repeating pattern of regions corresponding to power and ground. The multiple layers include (i) a top layer having, in the particular region, power contacts and ground contacts for coupling to an integrated circuit and (ii) a bottom layer having, in the particular region, power contacts and ground contacts for coupling to another device. At least one layer of the multiple layers has a repeating pattern of signal traces that extend along and are located between the regions corresponding to ground in the at least one layer.

Abstract: A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 ?m or less.

Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package.

Abstract: A printed wiring board includes a conductor layer, an outermost resin insulating layer having a first surface and a second surface on the opposite side with respect to the first surface and laminated on the conductor layer such that the second surface faces the conductor layer, and metal posts formed in the outermost resin insulating layer such that the metal posts are penetrating through the outermost resin insulating layer and reaching the conductor layer. The metal posts include first metal posts and second metal posts such that each of the first metal posts has a first upper surface positioned above the first surface of the outermost resin insulating layer and having an entirely flat surface and that each of the second metal posts has a second upper surface positioned above the first surface of the outermost resin insulating layer and having a partly flat surface.

Abstract: A display unit according to an embodiment of the disclosure includes a substrate, a wiring line and a light-emission section that are provided on the substrate, an insulating layer covering the wiring line and the light-emission section, and provided on an entire surface of the substrate, and a sealing layer provided on an entire surface of the insulating layer, and including a resin material having an oxygen transmission rate higher than a water-vapor transmission rate.

Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

Abstract: A circuit board disclosed in the present invention includes a substrate and a circuit layer. The circuit layer is formed on a surface of the substrate and includes at least one test circuit line. The test circuit line includes a main segment and a branch segment connected with each other. The branch segment is provided to be contacted with a test equipment for electrical test so as to protect the main segment from breaking during electrical test.

Abstract: A capacitor is provided. The capacitor includes a substrate that has opposing first and second main surfaces. The capacitor also includes at least two conductive plates that are formed in the substrate and extend from the first main surface to the second main surface of the substrate. The capacitor further includes at least one insulating structure that is formed between two adjacent conductive plates of the at least two conductive plates and extends from the first main surface to the second main surface.

Abstract: An integrated circuit (IC) package includes an encapsulation package that contains an integrated circuit die attached to a lead frame. A set of contacts is formed on the package that each have an exposed contact sidewall surface and an exposed contact lower surface. A protective layer of solder wettable material covers each contact sidewall surface.

Abstract: The present invention discloses a lead structure of the circuit, which comprises a first lead and a second lead. The first lead includes a first bump connecting part and a first lead segment. The first lead segment is connected to the first bump connecting part. The width of the first lead segment is smaller than the width of the first bump connecting part. The second lead is adjacent to the first lead and there is a lead gap therebetween. The second lead also includes a second bump connecting part and a first lead segment. The first lead segment of the second lead is connected to the second bump connecting part. The second bump connecting part and the first bump connecting part are arranged staggeredly. The second bump connecting part is adjacent to the first lead segment of the first lead.

Abstract: One embodiment includes a computer interconnect system. The system includes a first cable comprising a first superconducting signal line formed from a superconductor material to propagate at least one signal and a second cable comprising a second superconducting signal line formed from the superconductor material to propagate the respective at least one signal. The system also includes an interconnect structure configured to contact each of the first and second cable and comprising a third superconducting signal line formed from the superconductor material and configured to propagate the respective at least one signal between the respective first and second superconducting signal line. The system further includes at least one interconnect contact disposed on the first, second, and third at least one superconducting signal line at a contact portion between each of the at least one first and third superconducting signal lines and the at least second and third superconducting signal lines.

Abstract: A staking terminal includes a conductor portion having a conductor platform, a first plurality of tines extending from the conductor platform, and a conductor crimp extending from the conductor platform. The conductor platform and the tines are not coplanar in a folded configuration. The staking terminal further includes a ground portion having a ground platform, a second plurality of tines extending from the ground platform, and a first braid crimp extending from the ground platform. The ground platform and the tines are not coplanar in the folded configuration.

Abstract: A wire embedding system and methods are presented. A wire is embedded in a substrate at predetermined locations in a series of sequential embedding instances using heat and pressure. The heat and pressure are removed from the wire in between the series of sequential embedding instances.

Abstract: Methods of coating contacts to have a specific color. The color can be selected to match a color of a portion of a device enclosure for an electronic device housing the contacts. Examples can instead provide methods of coating contacts to have a color to contrast with a color of a portion of the device enclosure. These methods can provide electrical contacts having a low contact resistance and good corrosion and scratch resistance.

Abstract: A multilayer electronic component includes a body including a capacitance forming portion including dielectric layers and first and second internal electrodes with respective dielectric layers interposed therebetween and an upper cover portion and a lower cover portion, respectively disposed above and below the capacitance forming portion, and first and second external electrodes disposed on the body and respectively connected to the first and second internal electrodes. At least one of the upper cover portion or the lower cover portion includes a dummy electrode layer including a dummy pattern having a mesh shape. The dummy pattern includes a first dummy pattern, connected to the first external electrode, and a second dummy pattern spaced apart from the first dummy pattern and connected to the second external electrode.

Abstract: A temperature-dependent switch includes a housing with a top face and an outer face that runs transversely to the top face. The switch includes a first outer contact area that is arranged on the top face. The switch includes a second outer contact area that is arranged at the housing. The switch includes a temperature-dependent switching mechanism that is arranged in the housing and configured to establish or open an electrically conductive connection between the first and the second outer contact area depending on a temperature of the switching mechanism. The housing is disposed in a metal mounting cap that includes a wall. An upper rim of the wall protrudes beyond the top face of the housing. An inner side of the wall bears at least partially against the outer face of the housing.

Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.