Voidless (e.g., Solid) Patents (Class 174/264)
  • Patent number: 10995232
    Abstract: This invention is a flexible conductive ink composition comprising (A) a resin binder, (B) silver-plated core conductive particles, and (C) conductive particles having a surface area at least 1.0 m2/g.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: May 4, 2021
    Assignees: HENKEL AG & CO. KGAA, HENKEL IP & HOLDING GMBH
    Inventors: Jie Cao, Jose Garcia-Miralles, Allison Yue Xiao, Rudie Oldenzijl, Gunther Dreezen, Qili Wu, Jianping Chen
  • Patent number: 10966311
    Abstract: Systems and methods are provided for reducing crosstalk between differential signals in a printed circuit board (PCB) using fine pitch vias. A pair of contact pads are on the top surface of the PCB and configured to couple a PCB component to the PCB, the contacts a first distance from each other. A first via of a plurality of vias is electrically coupled to a first contact of the pair of contacts and a second via is electrically coupled to a second contact, the first via and second via a second distance from each other, the second distance being less than current standards for minimum via pitch. Each via comprises a via pad on the top surface and a plated through-hole extending from the top surface to a termination point. A separator gap is between the first via and the second via.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: March 30, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Hyunjun Kim, Andrew J. Becker, Paul Taylor Wildes
  • Patent number: 10966321
    Abstract: System-in-package structures and methods of assembly are described. In an embodiment, a system-in-package includes opposing circuit boards, each including mounted components overlapping the mounted components of the opposing circuit board. A gap between the opposing circuit boards may be filled with a molding material, that additionally encapsulates the overlapping mounted components. In some embodiments, the opposing circuit boards are stacked on one another using one or more interposers that may provide mechanical or electrical connection.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: March 30, 2021
    Assignee: Apple Inc.
    Inventors: Yanfeng Chen, Shankar Pennathur, Mandar Painaik, Lan Hoang, Meng Chi Lee
  • Patent number: 10950552
    Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Kooi Chi Ooi, Paik Wen Ong
  • Patent number: 10923440
    Abstract: An integrated circuit and a method of securing the integrated circuit during its fabrication. The method includes delimitation of the integrated circuit into a first zone called a standard zone and a second zone called a security zone, and random degradation of an interconnection structure of the security zone thus forming a physical unclonable function modelled by random electrical continuity that can be queried by a challenge-response authentication protocol.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: February 16, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Michael May, Florian Pebay-Peyroula
  • Patent number: 10833020
    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Kemal Aygun, Ajay Jain, Zhiguo Qian
  • Patent number: 10827615
    Abstract: A printed circuit board includes a substrate having a first surface and a second surface, opposite to the first surface, and having a through-portion penetrating between the first surface and the second surface; and a through-via disposed in at least a portion of the through-portion, wherein the through-via includes a first metal layer having a first groove portion facing an interior of the through-portion from the first surface of the substrate and a second groove portion facing the interior of the through-portion from the second surface of the substrate, and the first metal layer has a first region, and a second region, having different average grain sizes.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Chan Choi, Young Kwon Jeong, Min Soo Kim, Seong Jae Mun
  • Patent number: 10813209
    Abstract: A multilayer substrate includes a base including insulating layers stacked on one another, a first principal surface, and a second principal surface, a heat transfer member extending through a first insulating layer nearest to the first principal surface, a second coefficient of thermal conductivity of a material of the heat transfer member is higher than a first coefficient of thermal conductivity of a material of the insulating layers, a first metal film adhered to the first principal surface, the first metal film overlapping the heat transfer member when viewed from the layer stacking direction, and a first joining member disposed between the heat transfer member and the first metal film and being made of a material with a coefficient of thermal conductivity which is higher than the first coefficient of thermal conductivity of the material of the insulating layers.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 20, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shuichi Kezuka, Kuniaki Yosui
  • Patent number: 10811588
    Abstract: Devices and methods that can facilitate vertical dispersive readout of qubits of a lattice surface code architecture are provided. According to an embodiment, a device can comprise a first substrate that can have a first side and a second side that can be opposite the first side. The first substrate can comprise a read pad that can be located on the first side and a readout resonator that can be located on the second side. The device can further comprise a second substrate that can be connected to the first substrate. The second substrate can comprise a qubit. In some embodiments, the device can further comprise a recess that can be located on the first side of the first substrate. The recess can comprise the read pad.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Salvatore Bernardo Olivadese, Patryk Gumann, Jay M. Gambetta
  • Patent number: 10811182
    Abstract: An inductor includes a body in which is disposed a coil connecting a plurality of coil patterns by a via. The via includes a first conductive layer and a second conductive layer disposed on the first conductive layer, and the via has an upper portion having a transverse cross-sectional area that is greater than a transverse cross-sectional area of a lower portion thereof. An interlayer contact area of coils may be increased, thereby improving electrical characteristics and connection reliability.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soo Yeol Kim, Jong Seok Bae, Se Woong Paeng
  • Patent number: 10804126
    Abstract: A method for manufacturing a circuit board includes forming recess structures on a transferring layer; forming a dielectric layer on the transferring layer to form a stacking structure, in which the dielectric layer is at least embedded with the recess structures; bonding the stacking structure a base board by pressing, such that the dielectric layer is in contact with the base board; patterning the dielectric layer, including performing an exposure process on the stacking structure through the transferring layer; and after the exposure process is finished, removing the transferring layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 13, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventor: Po-Hsuan Liao
  • Patent number: 10784224
    Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Yeruva, Kyle K. Kirby, Owen R. Fay, Sameer S. Vadhavkar
  • Patent number: 10779408
    Abstract: The printed wiring board of the present disclosure includes: a plurality of insulating layers laminated in a thickness direction; a plurality of wiring conductors respectively correspondingly positioned between the plurality of insulating layers; a through hole penetrating the plurality of insulating layers and the plurality of wiring conductors in the thickness direction; and a through-hole conductor positioned on a wall surface of the through hole; each of the plurality of wiring conductors has a first surface facing the through hole, each of the plurality of insulating layers has a second surface facing the through hole, and the first surface is farther away from a central axis penetrating the through hole in the thickness direction than the second surface.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 15, 2020
    Assignee: KYOCERA Corporation
    Inventors: Takashi Ishioka, Hidetoshi Yugawa
  • Patent number: 10739389
    Abstract: A method for measuring a contact resistance at an interface of an electrically conductive coating and a cross-ply surface of a composite layer having electrically conductive fibers. The method includes: placing a dielectric coating of a sensing pad in contact with the composite layer or with the electrically conductive coating on the cross-ply surface of the composite layer; electrically connecting first and second input terminals of a comparator to the sensing pad and to one side of a capacitor respectively; electrically connecting another side of the capacitor to a fixed resistance; electrically connecting the fixed resistance to an electrically conductive body inserted in a hole in the composite layer; supplying an alternating current to the electrically conductive body and to the fixed resistance; and outputting a characteristic voltage signal if an amplitude of the input signal at the first input terminal is at least equal to an amplitude of the input signal at the second input terminal.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 11, 2020
    Assignee: The Boeing Company
    Inventor: Shahriar Khosravani
  • Patent number: 10703924
    Abstract: A conductive ink for a rollerball pen comprises an aqueous solvent and conductive particles comprising one or more metals dispersed therein at a concentration of at least about 30 wt. %. The conductive particles include conductive flakes and conductive nanoparticles. A dispersant coats the conductive particles at a loading level of at least about 0.1 mg/m2 to about 0.8 mg/m2. A conductive trace deposited on a substrate from a rollerball pen comprises a percolative network of conductive particles comprising one or more metals. The conductive particles include conductive flakes and conductive nanoparticles. The conductive trace has a conductivity of at least about 1% of a bulk metal conductivity and a reflectance of greater than 40%.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: July 7, 2020
    Assignee: ELECTRONINKS WRITEABLES, INC.
    Inventors: Steven Brett Walker, Analisa Russo
  • Patent number: 10701793
    Abstract: A component carrier includes a layer stack formed of an electrically insulating structure and an electrically conductive structure. Furthermore, a bore extends into the layer stack and has a first bore section with a first diameter (D1) and a connected second bore section with a second diameter (D2) differing from the first diameter (D1). A thermally conductive material fills substantially the entire bore. The bore is in particular formed by laser drilling.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 30, 2020
    Assignee: AT&S (China) Co., Ltd.
    Inventors: Nikolaus Bauer-Öppinger, ZhaoJian Chen, Yucun Dou, Wilhelm Tamm
  • Patent number: 10622340
    Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chanhee Jeong, Hyunki Kim, Junwoo Park, Byoung Wook Jang, Sunchul Kim, Su-Min Park, Pyoungwan Kim, Inku Kang, Heeyeol Kim
  • Patent number: 10624212
    Abstract: An electronic device is provided and including a first substrate including a first glass substrate and a first conductive layer; a second substrate including: a second glass substrate which is disposed to be apart from the first conductive layer and includes a first surface opposed to the first conductive layer and a second surface opposite to the first surface, a second conductive layer disposed on the second surface, and a first hole penetrating the second glass substrate; and a connecting material electrically connecting the first conductive layer and the second conductive layer via the first hole, wherein the first hole is shaped as a funnel, and the connecting material includes a hollow part in which an insulative filling material is filled.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: April 14, 2020
    Assignee: Japan Display Inc.
    Inventors: Shuichi Osawa, Yoshikatsu Imazeki, Yoichi Kamijo, Yoshihiro Watanabe
  • Patent number: 10586712
    Abstract: According to a mode of the present invention, a method of manufacturing an electronic component includes: preparing a component main-body 110 including a first surface having an electrode-formed region having a plurality of bump electrodes 103, a second surface opposite to the first surface, and side peripheral surfaces connecting the first surface and the second surface; forming a mask section M1 on at least a peripheral portion of the first surface, the mask section surrounding the electrode-formed region, a height of the mask section being equal to or more than a height of the plurality of bump electrodes; bonding the mask section of the first surface to an adhesive layer 30 on a holder for holding a component; forming a protective film 105 on the component main-body, the protective film covering the second surface and the side peripheral surfaces; and removing the mask section M1 from the first surface.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: March 10, 2020
    Assignee: ULVAC, INC.
    Inventors: Takashi Kageyama, Tetsuya Shimada, Koji Takahashi, Yuu Nakamuta, Manabu Harada
  • Patent number: 10559542
    Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Shawn P. Fetterolf, Chi-Chun Liu
  • Patent number: 10410977
    Abstract: A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: September 10, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar
  • Patent number: 10319682
    Abstract: An electronic component device includes a mount substrate including an outer electrode on one principal surface and a mount electrode on another principal surface, at least one substrate component including a terminal electrode on one principal surface, and that is mounted on the mount substrate by joining the terminal electrode to the mount electrode, and a sealing resin layer that is provided on the mount substrate on which the at least one substrate component is mounted. The sealing resin layer includes a region with a large thickness, and a top surface including an inclination.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: June 11, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kazushi Watanabe
  • Patent number: 10297546
    Abstract: Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Erdem Kaltalioglu, Ronald G. Filippi, Jr., Ping-Chuan Wang, Cathryn Christiansen
  • Patent number: 10278280
    Abstract: A component carrier includes a layer stack formed of an electrically insulating structure and an electrically conductive structure. Furthermore, a bore extends into the layer stack and has a first bore section with a first diameter (D1) and a connected second bore section with a second diameter (D2) differing from the first diameter (D1). A thermally conductive material fills substantially the entire bore. The bore is in particular formed by laser drilling.
    Type: Grant
    Filed: January 28, 2017
    Date of Patent: April 30, 2019
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Nikolaus Bauer-Öppinger, ZhaoJian Chen, Yucun Dou, Wilhelm Tamm
  • Patent number: 10129974
    Abstract: A multi-layer circuit structure includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: November 13, 2018
    Assignees: Industrial Technology Research Institute, First Hi-tec Enterprise Co., Ltd., NEXCOM International Co., Ltd.
    Inventors: Chien-Min Hsu, Min-Lin Lee, Huey-Ru Chang, Hung-I Liu, Ching-shan Chang
  • Patent number: 10057991
    Abstract: Provided herein are layered structures and methods for forming the same, the layered structures including a conductive layer and an overcoat layer formed on a surface thereof, one or more electrical contacts formed on the surface of the conductive layers and via openings extending through the overcoat layer and reaching the electrical contacts.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 21, 2018
    Assignee: CAM Holding Corporation
    Inventor: Paul Mansky
  • Patent number: 9983725
    Abstract: An electronic device includes mutual capacitance sensing circuitry for a capacitive touch pad. The touch pad has pairs of transmit and receive electrodes. The sensing circuitry intermittently charges and discharges the transmit electrode, and then measures corresponding voltage level changes at the receive electrode. A non-linear voltage-to-current converter is used to detect the voltage level changes, which allows for great sensitivity to mutual capacitance changes.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 29, 2018
    Assignee: NXP USA, INC.
    Inventors: Xiaolei Wu, Liang Qiu
  • Patent number: 9955571
    Abstract: A PCB page blank includes a flexible substrate, a curable adhesive, a conductive layer, and a conductive layer support. The flexible substrate receives an opaque negative circuit pattern thereon. Portions of the curable adhesive not obscured by the circuit pattern may bond to portions of the conductive layer when exposed to light. The bonded portions of the conductive layer shear or tear from non-bonded portions of the conductive layer such that the bonded portions remain with the flexible substrate and the non-bonded portions remain with the conductive layer support when the flexible substrate and the conductive layer support are separated. The flexible substrate and the bonded portions of the conductive layer thus form a PCB prototype with the bonded portions of the conductive layer forming circuit traces of the circuit pattern.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 24, 2018
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventors: Jonathan Douglas Hatch, Stephen McGarry Hatch
  • Patent number: 9949372
    Abstract: A printed wiring board includes a laminate, a wiring layer formed on first main surface of the laminate and including conductor pads, via conductors including first and second via conductors and formed in the laminate such that each via conductor has diameter gradually reducing from the first main surface toward second main surface of the laminate, and conductor post formed on the first via conductors such that each conductor post includes a metal foil and a plating layer formed on the metal foil. The via conductors are formed such that the first via conductors are positioned in an outer edge portion of the laminate and have minimum-diameter-side surfaces positioned to form a same plane with the second main surface of the laminate and that the second via conductors are positioned in a central portion of the laminate and have minimum-diameter-side surfaces recessed from the second main surface of the laminate.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 17, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Hiroyuki Ban, Haiying Mei
  • Patent number: 9938187
    Abstract: A method of drilling multiple orifices in and texturing a substrate is disclosed and includes the following steps. Ultrafast laser pulses are passed through a beam splitting diffractive optical element and then multiple beams are passed through a distributive-focus lens focusing assembly. The relative distance and/or angle of said distributive-focus lens focusing assembly in relation to the laser source is adjusted focusing the pulses in a distributed focus configuration creating a principal focal waist and at least one secondary focal waist. The fluence level of the at least one secondary focal waists is adjusted such that it is or they are of sufficient intensity and number to ensure propagation of multiple filaments in the substrate. Photoacoustic compressive machining is performed and forms multiple volume(s) within the substrate.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: April 10, 2018
    Assignee: ROFIN-SINAR TECHNOLOGIES LLC
    Inventor: S. Abbas Hosseini
  • Patent number: 9936590
    Abstract: A method for fabricating a biocompatible hermetic housing including electrical feedthroughs, the method comprises providing a ceramic sheet having an upper surface and a lower surface, forming at least one via hole in said ceramic sheet extending from said upper surface to said lower surface, inserting a conductive thick film paste into said via hole, laminating the ceramic sheet with paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to form a laminated ceramic substrate, firing the laminated ceramic substrate to a temperature to sinter the laminated ceramic substrate and cause the paste filled via hole to form metalized via and cause the laminated ceramic substrate to form a hermetic seal around said metalized via, and removing the upper ceramic sheet and the lower ceramic sheet material from the fired laminated ceramic substrate to expose an upper and a lower surface of the metalized via.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: April 3, 2018
    Assignee: Second Sight Medical Products, Inc.
    Inventors: Jerry Ok, Robert J Greenberg
  • Patent number: 9907169
    Abstract: A process for forming an encapsulating mold compound into a molded solder mask on a bottom surface of a PCB is provided that allows the molded solder mask to have a very precise, preselected thickness, or height, while also ensuring that no gaps between the solder mask and side walls of the electrical contact pads exist. A circuit board and circuit board assembly that incorporate the molded solder mask are also provided. The molded solder mask is fabricated in such a way that overlap between the molded solder mask and the electrical contact pads and gaps between the molded solder mask and the side walls of the electrical contact pads are avoided. In addition, the molded solder mask allows the pitch between adjacent electrical contact pads to be greatly reduced compared to the pitch that is possible using a traditional solder mask formed by the traditional photolithographic approach.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 27, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nitesh Kumbhat, Li Sun, Aaron Lee, Deog-Soon Choi, Hyun-Mo Ku, Jack Ajoian
  • Patent number: 9888581
    Abstract: A method for manufacturing a wiring board includes preparing a core structure, forming on a first surface of the core structure a first buildup structure including insulation layers, and forming on a second surface of the core structure on the opposite side of the first surface of the core structure a second buildup structure including insulation layers and an inductor device. The insulation layers in the second buildup structure have thicknesses which are thinner than thicknesses of the insulation layers in the first buildup structure, and the forming of the second buildup structure includes forming the inductor device in the second buildup structure on the second surface of the core structure such that at least a portion of a conductive pattern formed in the core structure is included as a portion of the inductor device.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: February 6, 2018
    Assignee: IBIDEN CO., LTD.
    Inventor: Yoshinori Takenaka
  • Patent number: 9788427
    Abstract: A formation method of circuit board structure is disclosed. The formation method comprises: forming an intermediate substrate having interconnections therein and circuit patterns on both upper and lower surfaces, wherein the interconnections electrically connect the upper and lower circuit patterns; forming an upper dielectric layer overlying the upper circuit patterns, wherein the upper dielectric layer has a plurality of trenches therein; forming conductive wires in the trenches using e-less plating; and forming at least one protective layer overlying the conductive wires using a surface finishing process. The circuit board structure features formation of embedded conductive wires in the dielectric layer so that a short circuit can be avoid.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: October 10, 2017
    Inventor: Dyi-Chung Hu
  • Patent number: 9781825
    Abstract: A flex circuit including a plurality of layers folded on a first fold line and folded on a second fold line is disclosed. The plurality of layers may include a first conductive layer, an insulating layer adjacent the first conductive layer, and a second conductive layer adjacent the insulating layer. The flex circuit may include a plurality of slits extending through each layer of the plurality of layers, the plurality of slits disposed on the first fold line and the second fold line.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: October 3, 2017
    Assignee: Dell Products L.P.
    Inventors: Sandor Farkas, Girish Kumar Singh, Bhyrav M. Mutnury
  • Patent number: 9769936
    Abstract: A method for producing circuit board, including: adhering plastic deformable insulating material onto surface of laminate, which contains second-metal-layer of second metal, and first-metal-layer in pattern on second-metal-layer, and the surface of the laminate is surface of second-metal-layer where first-metal-layer is formed, and surface of first-metal-layer, followed by curing the material, and removing second-metal-layer to form plate structure to which first-metal-layer in pattern is formed; opening hole in cured material from surface of the plate structure opposite to surface thereof where first-metal-layer is formed, until the hole reaches first-metal-layer; filling the hole with electroconductive paste, to form the plate structure filled therewith; and laminating one plate structure filled therewith with the other plate structure filled therewith in manner that first-metal-layer of one plate structure filled therewith faces opening of the hole of other plate structure filled therewith, wherein first-m
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: September 19, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kenji Iida, Takashi Nakagawa, Seigo Yamawaki, Yasuhiro Karahashi, Junichi Kanai, Koji Komemura
  • Patent number: 9754632
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Patent number: 9691693
    Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: June 27, 2017
    Assignee: Invensas Corporation
    Inventors: Andrew Cao, Michael Newman
  • Patent number: 9691572
    Abstract: Disclosed is key button (4) that includes a display surface on which character section (A) is formed, and a side face extending in a direction to intersect the display surface. The key button further includes transmission section (6) made of a light transmissive material, which constitutes the display surface and the side face, and shielding section (7) made of a light shielding material, which covers only a part of transmission section (6) other than character section (A) of the display surface.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: June 27, 2017
    Assignee: NEC Platforms, Ltd.
    Inventor: Tadamine Toh
  • Patent number: 9564346
    Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 7, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen
  • Patent number: 9532468
    Abstract: A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: December 27, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Masatoshi Kunieda, Makoto Terui, Ryoujiro Tominaga, Takashi Kariya
  • Patent number: 9520365
    Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 13, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu, Wei Meng, Chee Siang Ong
  • Patent number: 9455219
    Abstract: A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and a second wiring layer formed under the first insulating layer and connected to the first wiring layer through the first via hole, and a re-wiring portion including a second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer, and a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through the second via hole. The re-wiring layer is formed of a seed layer and a metal plating layer provided on the seed layer, and the seed layer is equal to or wider in width than the metal plating layer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 27, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Akio Rokugawa, Toshinori Koyama
  • Patent number: 9433093
    Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: August 30, 2016
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 9295150
    Abstract: A printed circuit board includes a first, second, and third dielectric layers, and a first, second, and third trace layers. The first trace layer and the second trace layer are formed on opposite surfaces of the first dielectric layer. The second dielectric layer is formed on the second trace layer, a first blind hole is defined in the first surface and terminated at a position in the first dielectric layer, a first conductive via is formed in the first blind hole. A second blind hole is formed in the second dielectric layer and the first dielectric layer. A second conductive via is formed in the second blind hole. The third trace layer is electrically connected with the second conductive via. The first trace layer is electrically connected with the second trace layer through the first conductive via and the second conductive via.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 22, 2016
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventor: Wen-Hung Hu
  • Patent number: 9288914
    Abstract: A printed circuit board with circuit visible includes a wiring layer, a first adhesive layer, a first dielectric layer, and a cover film, which are stacked in described order, the wiring layer comprising at least one electrical contact pad. The cover film has at least one opening corresponding to the electrical contact pad. The cover film includes a second dielectric layer and a second adhesive layer. A flow initiation temperature of the first adhesive layer is in a range from 85 degrees centigrade to 90 degrees centigrade, and a hardening temperature of the first adhesive being lower than 150 degrees centigrade.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: March 15, 2016
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventors: Ming-Jaan Ho, Xian-Qin Hu
  • Patent number: 9286826
    Abstract: An electronic device may include a display. The display may be an organic light-emitting diode display. The organic light-emitting diode display may have a substrate layer, a layer of organic light-emitting diode structures, and a layer of sealant. Vias may be formed in the substrate layer by laser drilling. The vias may be filled with metal using electroplating or other metal deposition techniques. The vias may be connected to contacts on the rear surface of the display. Components such as flexible printed circuits, integrated circuits, connectors, and other circuitry may be mounted to the contacts on the rear surface of the display.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: March 15, 2016
    Assignee: Apple Inc.
    Inventors: Derek Wright, Fletcher R. Rothkopf, Scott A. Myers
  • Patent number: 9269645
    Abstract: A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: February 23, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Fu Lin, Chien-Li Kuo, Kuo-Ming Chen
  • Patent number: 9265159
    Abstract: An embodiment of a stacked structure includes: a first substrate that includes a first electrode; a second substrate that includes a second electrode; and an adhesive resin material that is provided between the first substrate and the second substrate and includes a plurality of conductive vias, the plurality of conductive vias electrically connecting the first electrode and the second electrode.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: February 16, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Takashi Kanda
  • Patent number: 9264010
    Abstract: The present invention relates to a via structure having an open stub and a printed circuit board having the same. In accordance with an embodiment of the present invention, a via structure having an open stub including: a signal transmission via passing through an insulating layer; upper and lower via pads for connecting first and second transmission lines, which are respectively formed on and under the insulating layer, and the signal transmission via; and at least one open stub connected to an outer periphery of each via pad to have a shunt capacitance with each ground pattern formed on and under the insulating layer is provided. Further, a printed circuit board with a via having an open stub is provided.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: February 16, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Hwan Lee, Seung Wook Park, Christian Romero, Young Do Kweon, Jin Gu Kim