Abstract: Devices and methods that can facilitate vertical dispersive readout of qubits of a lattice surface code architecture are provided. According to an embodiment, a device can comprise a first substrate that can have a first side and a second side that can be opposite the first side. The first substrate can comprise a read pad that can be located on the first side and a readout resonator that can be located on the second side. The device can further comprise a second substrate that can be connected to the first substrate. The second substrate can comprise a qubit. In some embodiments, the device can further comprise a recess that can be located on the first side of the first substrate. The recess can comprise the read pad.

Abstract: In one example, a semiconductor device comprises a first substrate comprising a first conductive structure, a first body over the first conductive structure and comprising an inner sidewall defining a cavity in the first body, a first interface dielectric over the first body, and a first internal interconnect in the first body and the first interface dielectric, and coupled with the first conductive structure. The semiconductor device further comprises a second substrate over the first substrate and comprising a second interface dielectric, a second body over the second interface dielectric, and a second conductive structure over the second body and comprising a second internal interconnect in the second body and the second interface dielectric. An electronic component is in the cavity, and the second internal interconnect is coupled with the first internal interconnect. Other examples and related methods are also disclosed herein.

Abstract: An electronic component comprising a coil component having an element body containing ceramic, a coil disposed in the element body, and an external electrode disposed in the element body and electrically connected to the coil; and a mold resin sealing the coil component. The electronic component further comprises an electrode film in contact with an outer surface of the mold resin; and a connection conductor disposed in the mold resin and electrically connecting the external electrode and the electrode film.

Abstract: A circuit module (100) includes a substrate (1), on one principal surface of which a first wiring pattern (2) is provided, first electronic components (3-6) constituting a first electronic circuit together with the first wiring pattern (2), a plurality of connection conductors (8), a plurality of external connection terminals, a first resin layer (9), and a second resin layer (12). At least one of the plurality of connection conductors (8) includes a first columnar conductor (8a) extending in a normal line direction of the one principal surface of the substrate (1), and a plate-like conductor (8b) extending in a direction parallel to the one principal surface of the substrate (1). At least one of the plurality of external connection terminals is a second columnar conductor (11) extending in the normal line direction of the one principal surface of the substrate (1).

Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

Abstract: A touch sensor according to an embodiment of the present invention includes a substrate layer, sensing electrodes arranged on a top surface of the substrate layer, the sensing electrodes having boundaries in which a plurality of convex portions are connected, and a dummy electrode disposed between the sensing electrodes, the dummy electrode having a boundary in which a plurality of convex portions are connected. The sensing electrodes include a first sensing electrode arranged in a column direction and a second sensing electrode arranged in a row direction. A convex portion in a region where the first sensing electrode, the second sensing electrode and the dummy electrode are adjacent to each other has a radius of curvature less than that of a convex portion in other regions.

Abstract: A continuous additive fabrication system comprises a bath of photopolymer resin and a light source assembly having a light source and a motorized variable aperture. The light source assembly is operable to generate a focus point in the bath of photopolymer resin, the shape of the focus point at a curing plane within the bath of photopolymer resin corresponding to the shape of the motorized variable aperture. The continuous additive fabrication system further comprises a platform configured to support a build object and a drive mechanism (coupled to at least one of the platform and the light source assembly) configured to continuously move the curing plane through the bath of photopolymer resin. A size and/or shape of the motorized variable aperture is changed while the curing plane in continuously moved through the bath of photopolymer resin.

Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

Abstract: A wiring substrate includes: a core layer having a first face, and a second face opposite to the first face; a through hole that penetrates the core layer; a first metal layer formed on an inner wall face of the through hole and formed on or above the first and second faces; a second metal layer that is formed on the first metal layer and fills the through hole, wherein the second metal layer has a first recess portion opposed to the through hole, and a second recess portion opposed to the first recess portion via the through hole; a third metal layer provided in the first recess portion; a fourth metal layer provided in the second recess portion; a fifth metal layer formed on the second metal layer and the third metal layer; and a sixth metal layer formed on the second metal layer and the fourth metal layer.

Abstract: A method of manufacturing a component carrier. The method includes forming a stack having at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, and embedding a filament in the stack.

Abstract: This invention is a flexible conductive ink composition comprising (A) a resin binder, (B) silver-plated core conductive particles, and (C) conductive particles having a surface area at least 1.0 m2/g.

Abstract: Systems and methods are provided for reducing crosstalk between differential signals in a printed circuit board (PCB) using fine pitch vias. A pair of contact pads are on the top surface of the PCB and configured to couple a PCB component to the PCB, the contacts a first distance from each other. A first via of a plurality of vias is electrically coupled to a first contact of the pair of contacts and a second via is electrically coupled to a second contact, the first via and second via a second distance from each other, the second distance being less than current standards for minimum via pitch. Each via comprises a via pad on the top surface and a plated through-hole extending from the top surface to a termination point. A separator gap is between the first via and the second via.

Abstract: System-in-package structures and methods of assembly are described. In an embodiment, a system-in-package includes opposing circuit boards, each including mounted components overlapping the mounted components of the opposing circuit board. A gap between the opposing circuit boards may be filled with a molding material, that additionally encapsulates the overlapping mounted components. In some embodiments, the opposing circuit boards are stacked on one another using one or more interposers that may provide mechanical or electrical connection.

Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.

Abstract: An integrated circuit and a method of securing the integrated circuit during its fabrication. The method includes delimitation of the integrated circuit into a first zone called a standard zone and a second zone called a security zone, and random degradation of an interconnection structure of the security zone thus forming a physical unclonable function modelled by random electrical continuity that can be queried by a challenge-response authentication protocol.

Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

Abstract: A printed circuit board includes a substrate having a first surface and a second surface, opposite to the first surface, and having a through-portion penetrating between the first surface and the second surface; and a through-via disposed in at least a portion of the through-portion, wherein the through-via includes a first metal layer having a first groove portion facing an interior of the through-portion from the first surface of the substrate and a second groove portion facing the interior of the through-portion from the second surface of the substrate, and the first metal layer has a first region, and a second region, having different average grain sizes.

Abstract: An inductor includes a body in which is disposed a coil connecting a plurality of coil patterns by a via. The via includes a first conductive layer and a second conductive layer disposed on the first conductive layer, and the via has an upper portion having a transverse cross-sectional area that is greater than a transverse cross-sectional area of a lower portion thereof. An interlayer contact area of coils may be increased, thereby improving electrical characteristics and connection reliability.

Abstract: Devices and methods that can facilitate vertical dispersive readout of qubits of a lattice surface code architecture are provided. According to an embodiment, a device can comprise a first substrate that can have a first side and a second side that can be opposite the first side. The first substrate can comprise a read pad that can be located on the first side and a readout resonator that can be located on the second side. The device can further comprise a second substrate that can be connected to the first substrate. The second substrate can comprise a qubit. In some embodiments, the device can further comprise a recess that can be located on the first side of the first substrate. The recess can comprise the read pad.

Abstract: A multilayer substrate includes a base including insulating layers stacked on one another, a first principal surface, and a second principal surface, a heat transfer member extending through a first insulating layer nearest to the first principal surface, a second coefficient of thermal conductivity of a material of the heat transfer member is higher than a first coefficient of thermal conductivity of a material of the insulating layers, a first metal film adhered to the first principal surface, the first metal film overlapping the heat transfer member when viewed from the layer stacking direction, and a first joining member disposed between the heat transfer member and the first metal film and being made of a material with a coefficient of thermal conductivity which is higher than the first coefficient of thermal conductivity of the material of the insulating layers.

Abstract: A method for manufacturing a circuit board includes forming recess structures on a transferring layer; forming a dielectric layer on the transferring layer to form a stacking structure, in which the dielectric layer is at least embedded with the recess structures; bonding the stacking structure a base board by pressing, such that the dielectric layer is in contact with the base board; patterning the dielectric layer, including performing an exposure process on the stacking structure through the transferring layer; and after the exposure process is finished, removing the transferring layer.

Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity.

Abstract: The printed wiring board of the present disclosure includes: a plurality of insulating layers laminated in a thickness direction; a plurality of wiring conductors respectively correspondingly positioned between the plurality of insulating layers; a through hole penetrating the plurality of insulating layers and the plurality of wiring conductors in the thickness direction; and a through-hole conductor positioned on a wall surface of the through hole; each of the plurality of wiring conductors has a first surface facing the through hole, each of the plurality of insulating layers has a second surface facing the through hole, and the first surface is farther away from a central axis penetrating the through hole in the thickness direction than the second surface.

Abstract: A method for measuring a contact resistance at an interface of an electrically conductive coating and a cross-ply surface of a composite layer having electrically conductive fibers. The method includes: placing a dielectric coating of a sensing pad in contact with the composite layer or with the electrically conductive coating on the cross-ply surface of the composite layer; electrically connecting first and second input terminals of a comparator to the sensing pad and to one side of a capacitor respectively; electrically connecting another side of the capacitor to a fixed resistance; electrically connecting the fixed resistance to an electrically conductive body inserted in a hole in the composite layer; supplying an alternating current to the electrically conductive body and to the fixed resistance; and outputting a characteristic voltage signal if an amplitude of the input signal at the first input terminal is at least equal to an amplitude of the input signal at the second input terminal.

Abstract: A conductive ink for a rollerball pen comprises an aqueous solvent and conductive particles comprising one or more metals dispersed therein at a concentration of at least about 30 wt. %. The conductive particles include conductive flakes and conductive nanoparticles. A dispersant coats the conductive particles at a loading level of at least about 0.1 mg/m2 to about 0.8 mg/m2. A conductive trace deposited on a substrate from a rollerball pen comprises a percolative network of conductive particles comprising one or more metals. The conductive particles include conductive flakes and conductive nanoparticles. The conductive trace has a conductivity of at least about 1% of a bulk metal conductivity and a reflectance of greater than 40%.

Abstract: A component carrier includes a layer stack formed of an electrically insulating structure and an electrically conductive structure. Furthermore, a bore extends into the layer stack and has a first bore section with a first diameter (D1) and a connected second bore section with a second diameter (D2) differing from the first diameter (D1). A thermally conductive material fills substantially the entire bore. The bore is in particular formed by laser drilling.

Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.

Abstract: An electronic device is provided and including a first substrate including a first glass substrate and a first conductive layer; a second substrate including: a second glass substrate which is disposed to be apart from the first conductive layer and includes a first surface opposed to the first conductive layer and a second surface opposite to the first surface, a second conductive layer disposed on the second surface, and a first hole penetrating the second glass substrate; and a connecting material electrically connecting the first conductive layer and the second conductive layer via the first hole, wherein the first hole is shaped as a funnel, and the connecting material includes a hollow part in which an insulative filling material is filled.

Abstract: According to a mode of the present invention, a method of manufacturing an electronic component includes: preparing a component main-body 110 including a first surface having an electrode-formed region having a plurality of bump electrodes 103, a second surface opposite to the first surface, and side peripheral surfaces connecting the first surface and the second surface; forming a mask section M1 on at least a peripheral portion of the first surface, the mask section surrounding the electrode-formed region, a height of the mask section being equal to or more than a height of the plurality of bump electrodes; bonding the mask section of the first surface to an adhesive layer 30 on a holder for holding a component; forming a protective film 105 on the component main-body, the protective film covering the second surface and the side peripheral surfaces; and removing the mask section M1 from the first surface.

Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.

Abstract: A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.

Abstract: An electronic component device includes a mount substrate including an outer electrode on one principal surface and a mount electrode on another principal surface, at least one substrate component including a terminal electrode on one principal surface, and that is mounted on the mount substrate by joining the terminal electrode to the mount electrode, and a sealing resin layer that is provided on the mount substrate on which the at least one substrate component is mounted. The sealing resin layer includes a region with a large thickness, and a top surface including an inclination.

Abstract: Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.

Abstract: A component carrier includes a layer stack formed of an electrically insulating structure and an electrically conductive structure. Furthermore, a bore extends into the layer stack and has a first bore section with a first diameter (D1) and a connected second bore section with a second diameter (D2) differing from the first diameter (D1). A thermally conductive material fills substantially the entire bore. The bore is in particular formed by laser drilling.

Abstract: A multi-layer circuit structure includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones.

Abstract: Provided herein are layered structures and methods for forming the same, the layered structures including a conductive layer and an overcoat layer formed on a surface thereof, one or more electrical contacts formed on the surface of the conductive layers and via openings extending through the overcoat layer and reaching the electrical contacts.

Abstract: An electronic device includes mutual capacitance sensing circuitry for a capacitive touch pad. The touch pad has pairs of transmit and receive electrodes. The sensing circuitry intermittently charges and discharges the transmit electrode, and then measures corresponding voltage level changes at the receive electrode. A non-linear voltage-to-current converter is used to detect the voltage level changes, which allows for great sensitivity to mutual capacitance changes.

Abstract: A PCB page blank includes a flexible substrate, a curable adhesive, a conductive layer, and a conductive layer support. The flexible substrate receives an opaque negative circuit pattern thereon. Portions of the curable adhesive not obscured by the circuit pattern may bond to portions of the conductive layer when exposed to light. The bonded portions of the conductive layer shear or tear from non-bonded portions of the conductive layer such that the bonded portions remain with the flexible substrate and the non-bonded portions remain with the conductive layer support when the flexible substrate and the conductive layer support are separated. The flexible substrate and the bonded portions of the conductive layer thus form a PCB prototype with the bonded portions of the conductive layer forming circuit traces of the circuit pattern.

Abstract: A printed wiring board includes a laminate, a wiring layer formed on first main surface of the laminate and including conductor pads, via conductors including first and second via conductors and formed in the laminate such that each via conductor has diameter gradually reducing from the first main surface toward second main surface of the laminate, and conductor post formed on the first via conductors such that each conductor post includes a metal foil and a plating layer formed on the metal foil. The via conductors are formed such that the first via conductors are positioned in an outer edge portion of the laminate and have minimum-diameter-side surfaces positioned to form a same plane with the second main surface of the laminate and that the second via conductors are positioned in a central portion of the laminate and have minimum-diameter-side surfaces recessed from the second main surface of the laminate.

Abstract: A method of drilling multiple orifices in and texturing a substrate is disclosed and includes the following steps. Ultrafast laser pulses are passed through a beam splitting diffractive optical element and then multiple beams are passed through a distributive-focus lens focusing assembly. The relative distance and/or angle of said distributive-focus lens focusing assembly in relation to the laser source is adjusted focusing the pulses in a distributed focus configuration creating a principal focal waist and at least one secondary focal waist. The fluence level of the at least one secondary focal waists is adjusted such that it is or they are of sufficient intensity and number to ensure propagation of multiple filaments in the substrate. Photoacoustic compressive machining is performed and forms multiple volume(s) within the substrate.

Abstract: A method for fabricating a biocompatible hermetic housing including electrical feedthroughs, the method comprises providing a ceramic sheet having an upper surface and a lower surface, forming at least one via hole in said ceramic sheet extending from said upper surface to said lower surface, inserting a conductive thick film paste into said via hole, laminating the ceramic sheet with paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to form a laminated ceramic substrate, firing the laminated ceramic substrate to a temperature to sinter the laminated ceramic substrate and cause the paste filled via hole to form metalized via and cause the laminated ceramic substrate to form a hermetic seal around said metalized via, and removing the upper ceramic sheet and the lower ceramic sheet material from the fired laminated ceramic substrate to expose an upper and a lower surface of the metalized via.

Abstract: A process for forming an encapsulating mold compound into a molded solder mask on a bottom surface of a PCB is provided that allows the molded solder mask to have a very precise, preselected thickness, or height, while also ensuring that no gaps between the solder mask and side walls of the electrical contact pads exist. A circuit board and circuit board assembly that incorporate the molded solder mask are also provided. The molded solder mask is fabricated in such a way that overlap between the molded solder mask and the electrical contact pads and gaps between the molded solder mask and the side walls of the electrical contact pads are avoided. In addition, the molded solder mask allows the pitch between adjacent electrical contact pads to be greatly reduced compared to the pitch that is possible using a traditional solder mask formed by the traditional photolithographic approach.

Abstract: A method for manufacturing a wiring board includes preparing a core structure, forming on a first surface of the core structure a first buildup structure including insulation layers, and forming on a second surface of the core structure on the opposite side of the first surface of the core structure a second buildup structure including insulation layers and an inductor device. The insulation layers in the second buildup structure have thicknesses which are thinner than thicknesses of the insulation layers in the first buildup structure, and the forming of the second buildup structure includes forming the inductor device in the second buildup structure on the second surface of the core structure such that at least a portion of a conductive pattern formed in the core structure is included as a portion of the inductor device.

Abstract: A formation method of circuit board structure is disclosed. The formation method comprises: forming an intermediate substrate having interconnections therein and circuit patterns on both upper and lower surfaces, wherein the interconnections electrically connect the upper and lower circuit patterns; forming an upper dielectric layer overlying the upper circuit patterns, wherein the upper dielectric layer has a plurality of trenches therein; forming conductive wires in the trenches using e-less plating; and forming at least one protective layer overlying the conductive wires using a surface finishing process. The circuit board structure features formation of embedded conductive wires in the dielectric layer so that a short circuit can be avoid.

Abstract: A flex circuit including a plurality of layers folded on a first fold line and folded on a second fold line is disclosed. The plurality of layers may include a first conductive layer, an insulating layer adjacent the first conductive layer, and a second conductive layer adjacent the insulating layer. The flex circuit may include a plurality of slits extending through each layer of the plurality of layers, the plurality of slits disposed on the first fold line and the second fold line.

Abstract: A method for producing circuit board, including: adhering plastic deformable insulating material onto surface of laminate, which contains second-metal-layer of second metal, and first-metal-layer in pattern on second-metal-layer, and the surface of the laminate is surface of second-metal-layer where first-metal-layer is formed, and surface of first-metal-layer, followed by curing the material, and removing second-metal-layer to form plate structure to which first-metal-layer in pattern is formed; opening hole in cured material from surface of the plate structure opposite to surface thereof where first-metal-layer is formed, until the hole reaches first-metal-layer; filling the hole with electroconductive paste, to form the plate structure filled therewith; and laminating one plate structure filled therewith with the other plate structure filled therewith in manner that first-metal-layer of one plate structure filled therewith faces opening of the hole of other plate structure filled therewith, wherein first-m

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

Abstract: Disclosed is key button (4) that includes a display surface on which character section (A) is formed, and a side face extending in a direction to intersect the display surface. The key button further includes transmission section (6) made of a light transmissive material, which constitutes the display surface and the side face, and shielding section (7) made of a light shielding material, which covers only a part of transmission section (6) other than character section (A) of the display surface.

Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.

Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.