Abstract: A circuit board module relates to the field of touch technologies. The above circuit board module includes a touch chip, a first circuit board, a second circuit board and at least one conductive connection portion. The touch chip includes at least one ground pin and a plurality of signal pins. The first circuit board includes a first ground portion and a plurality of signal pads; the signal pads are electrically connected to the signal pins; the first ground is electrically connected to the at least one ground pin. The second circuit board includes a second ground portion. The at least one conductive connection portion is electrically connected to the first ground portion and the second ground portion.

Abstract: Connection terminals of a semiconductor module are disposed appropriately in accordance with the connection destination of the semiconductor module. A semiconductor module which includes at least one semiconductor element is mounted on a first surface of a main substrate, which has the first surface on which a first circuit element is mounted and a second surface on which a second circuit element is mounted. A plurality of connection terminals include a first connection terminal group composed of a plurality of first connection terminals to be connected to the first circuit element via the main substrate, and a second connection terminal group composed of a plurality of second connection terminals to be connected to the second circuit element via the main substrate. The first connection terminal group is disposed on the outer peripheral side with respect to the second connection terminal group.

Abstract: A printed circuit board (PCB) and a method of manufacturing the same is described. The PCB includes a substrate defining a major plane and an integrated electromagnetic interference and compatibility (EMC/EMI) shielding enclosure configured to enclose the substrate. The shielding enclosure includes a metallic top layer deposited on top of the major plane of the substrate so as to envelop an uppermost layer of the substrate, a metallic bottom layer deposited on bottom of the major plane of the substrate so as to envelop a bottommost layer of the substrate, and a metallic side layer formed along a length of one or more edges of the substrate to electrically connect the metallic top layer and the metallic bottom layer.

Abstract: A printed circuit board includes: a first insulating layer having a recess portion in one surface of the first insulating layer; a first circuit pattern embedded in the first insulating layer and being in contact with a lower surface of the recess portion; a second insulating layer disposed on the one surface of the first insulating layer to be disposed in at least a portion of the recess portion; and a via penetrating through at least a portion of the second insulating layer, disposed in the recess portion, and connected to the first circuit pattern.

Abstract: An extensible and contractible mounting board that includes an extensible and contractible substrate; an extensible and contractible wiring line on one main surface of the extensible and contractible substrate; an electronic component electrically connected to the extensible and contractible wiring line; and a resin portion in contact with the extensible and contractible wiring line and overlapping an end portion of a connection region between the extensible and contractible wiring line and the electronic component in a plan view of the extensible and contractible mounting board, the resin portion having a cutout portion that overlaps the extensible and contractible wiring line. A Young's modulus of the resin portion is higher than a Young's modulus of the extensible and contractible substrate.

Abstract: A circuit board and a method of manufacturing the same are provided. The method includes the following steps of providing a first conductive layer; providing an adhesive material and at least one conductive bump, in which the adhesive material is electrically conductive; adhering at least one conductive bump to a surface of the first conductive layer using the adhesive material; providing an insulation layer; disposing the insulation layer on the surface of the first conductive layer and at least one conductive bump; and disposing a second conductive layer on the insulation layer.

Abstract: A printed circuit board includes: an insulating member; a first wiring layer disposed in the insulating member, and including first and second pattern layers spaced apart from each other based on a thickness direction of the printed circuit board; and a second wiring layer disposed in the insulating member, and spaced apart from the first pattern layer over the first pattern layer based on the thickness direction. Based on the thickness direction, an insulation distance between the first pattern layer and the second pattern layer is smaller than an insulation distance between the first pattern layer and the second wiring layer, and each of the first and second pattern layers is thinner than the second wiring layer.

Abstract: The present application provides a method for manufacturing a printed circuit board and a printed circuit board. The method for manufacturing a printed circuit board includes: providing a core board, wherein the core board includes an insulating baseplate, and a first surface and/or a second surface opposite to the first surface of the insulating baseplate is provided with a plurality of pads; and laminating a medium layer on a side of the insulating baseplate provided with the plurality of pads to form a laminated layer at least partially embedded among the plurality of pads.

Abstract: A flexible printed circuit board includes a power wiring layer transmitting power and a signal wiring layer insulated and stacked over or under the power wiring layer. The flexible printed circuit board may also include an upper wiring layer and a lower wiring layer insulated and stacked each other, and the power wiring layer and the signal wiring layer are provided between the upper wiring layer and the lower wiring layer.

Abstract: A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.

Abstract: An integrated substrate structure includes a redistribution film, a circuit substrate, and a plurality of conductive features. The redistribution film includes a fine redistribution circuitry, a circuit substrate is disposed over the redistribution film and includes a core layer and a coarse redistribution circuitry disposed in and on the core layer. The circuit substrate is thicker and more rigid than the redistribution film, and a layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry. The conductive features are interposed between the circuit substrate and the redistribution film to be connected to the fine redistribution circuitry and the coarse redistribution circuitry. A redistribution structure and manufacturing methods are also provided.

Abstract: Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.

Abstract: A semiconductor device includes first and second metal-insulator-metal structures. The first metal-insulator-metal structure includes a first bottom conductor plate, a first portion of a first dielectric layer, a first middle conductor plate, a first portion of a second dielectric layer, and a first top conductor plate stacked up one over another. The second metal-insulator-metal structure includes a second bottom conductor plate, a second portion of the first dielectric layer, a second middle conductor plate, a second portion of the second dielectric layer, and a second top conductor plate stacked up one over another. In a cross-sectional view, the first bottom conductor plate is wider than the first middle conductor plate that is wider than the first top conductor plate, and the second bottom conductor plate is narrower than the second middle conductor plate that is narrower than the first top conductor plate.

Abstract: An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.

Abstract: The present invention provides a multilayer circuit board and a method for manufacturing the same for improving a bowing problem that occurs when manufacturing the multilayer circuit board. A multilayer circuit board according to the present invention is a board having a patterned layer that functions as a circuit a base layer, and includes: a second pattern layer formed on one side of the base layer; a first pattern layer formed on the second pattern layer; and an interlayer insulating layer formed between the first pattern layer and the second pattern layer, the interlayer insulating layer being partially formed on the second pattern layer so as to correspond to a region where the first pattern layer is formed.

Abstract: According to a touch panel and a display panel provided in embodiments of the present application, a first connecting structure for connecting adjacent two first electrode units and a second connecting structure for connecting adjacent two second electrode units are improved. In this way, graphic design is performed on the second connecting structure and a wired manner of the first connecting structure is designed, so that an area of an intersection between the first connecting structure and the second connecting structure can be reduced, thereby reducing parasitic capacitance between the first connecting structure and the second connecting structure, and further improving or eliminating an impact of a bridging point of a touch electrode on touch linearity of a touch panel, to ensure better stability of the touch panel in use.

Abstract: A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than s second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.

Abstract: A multilayer coil component includes a multilayer body that contain a coil. The coil includes coil conductors. A lamination direction of the multilayer body and an axial direction of the coil are parallel to a first main surface. A distance between the coil conductors adjacent to each other in the lamination direction is from 4 ?m to 8 ?m. Each coil conductor includes a line portion and a land portion that is disposed at an end portion of the line portion. The land portions of the coil conductors adjacent to each other in the lamination direction are connected to each other with a via conductor interposed therebetween. A width of the line portion is from 30 ?m to 50 ?m. An inner diameter of each coil conductor is from 50 ?m to 100 ?m.

Abstract: According to one embodiment, a substrate includes a first dielectric substrate with a first through-hole, a second dielectric substrate with a first conductive via, a first signal line provided between the first dielectric substrate and the second dielectric substrate, a third dielectric substrate with a second conductive via, a first planar conductor provided between the second and third dielectric substrates and located away from the first and second conductive vias, a fourth dielectric substrate, and a second signal line provided between the third and fourth dielectric substrates. At least a part of a first inner wall of the first through-hole is not covered with a conductor. The first through-hole and the first conductive via partially overlap in a first direction. The first and second conductive vias partially overlap in the first direction. The second conductive via and the second signal line partially overlap in the first direction.

Abstract: A method for manufacturing a multilayer substrate including first and second insulating resin base material layers including different materials, includes configuring a conductor film-attached insulating resin base material with a conductor film on the first insulating resin base material layer, or a second conductor film-attached insulating resin base material with a conductor film on a main surface of the first insulating resin base material layer including a main surface of a stacked body including at least the first insulating resin base material layer, and stacking the first or second conductor film-attached insulating resin base material and another base material layer such that the conductor film is in contact with the second insulating resin base material layer. An adhesion strength of the first insulating resin base material layer to the conductor film is higher than an adhesion strength of the second insulating resin base material layer to the conductor film.

Abstract: A substrate structure, a manufacturing method thereof, and an electronic device. The substrate structure includes a substrate, conductive wires and conductive members. Multiple through holes penetrate through the substrate body of the substrate. Multiple first conductive pads are arranged on the first surface of the substrate body. Multiple second conductive pads are arranged on the second surface of the substrate body. The conductive wires are accommodated in the through holes and each has a first end in the first opening of corresponding through hole and a second end in the second opening of corresponding through hole. The conductive members are distributed on the first and second surfaces, and both ends thereof are connected to the corresponding first and second conductive pads through the conductive members. At least part of each conductive wire does not contact the hole wall of each through hole in a direct manner.

Abstract: A printed circuit board stack structure includes a first printed circuit board, a second printed circuit board, and a filling glue layer. The first printed circuit board has at least one overflow groove, and includes first pads and a retaining wall surrounding the first pads. The second printed circuit board is disposed on the first printed circuit board, and includes second pads and conductive pillars located on some of the second pads. The conductive pillars are respectively connected to some of the first pads to electrically connect the second printed circuit board to the first printed circuit board. The filling glue layer fills between the first and the second printed circuit boards, and covers the first pads, the second pads, and the conductive pillars. The retaining wall blocks the filling glue layer so that a portion of the filling glue layer is accommodated in the overflow groove.

Abstract: A circuit apparatus includes: a stacked body; and a plurality of terminals. The stacked body includes a plurality of layers. A plurality of holes that extend through the plurality of layers are formed in the stacked body. Each of the plurality of layers includes a connection member that is formed of a conductor. The connection member includes: a plurality of connection portions that are provided at positions corresponding to the plurality of holes; and a joining portion that connects the plurality of connection portions to each other. The plurality of terminals include a plurality of types of terminals that correspond to the plurality of layers. Each of the plurality of types of terminals can be selectively connected to the connection portion of a corresponding one of the plurality of layers by being inserted into a predetermined one of the plurality of holes.

Abstract: A display device including a substrate including a display area and a non-display area, a plurality of signal lines disposed in the display area and extending along a first direction and from the non-display area to the display area, a connection line extending from the non-display area and electrically connected to a respective signal line of the plurality of signal lines in the non-display area, and an initialization voltage line extending in a second direction intersecting the first direction, wherein the connection line overlaps the initialization voltage line in a thickness direction of the display device.

Abstract: A wiring substrate includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, a connection conductor penetrating through the insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer and adhering the first conductor layer and the insulating layer. The first conductor layer includes a conductor pad in contact with the connection conductor such that the conductor pad has a surface having a first region and a second region on second conductor layer side and that surface roughness of the first region is different from surface roughness of the second region, and the conductor pad of the first conductor layer is formed such that the first region is covered by the coating film and that the second region is covered by the connection conductor.

Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.

Abstract: A conductive pattern has been disclosed. The conductive pattern includes a pair of conductive traces. Each of the conductive traces comprises a linear portion and a terminal portion. The terminal portions are arranged adjacent to each other and comprises a pair of circular arc profile with a pair of complementary notches facing toward each other.

Abstract: A wiring substrate includes an insulating layer having a through hole, a first conductor layer formed on a first surface of the insulating layer, a second conductor layer formed on a second surface of the insulating layer, an interlayer connection conductor formed in the through hole such that the interlayer connection conductor is connecting the first and second conductor layers, and a resin body formed in the through hole of the insulating layer such that a volume occupancy rate of the resin body is in a range of 30% to 55% in the through hole. The interlayer connection conductor is formed such that the interlayer connection conductor has a length in a range of 1000 ?m to 2000 ?m in a thickness direction of the insulating layer and that a volume occupancy rate of the interlayer connection conductor is in a range of 45% to 70% in the through hole.

Abstract: A vertical interconnection structure of a multi-layer substrate includes a first via pad disposed in a first layer of metal interconnect of the multi-layer substrate; a second via pad disposed in a second layer of metal interconnect of the multi-layer substrate; a signal via electrically connecting the first via pad to the second via pad; a non-circular first ground plane disposed in the first layer of metal interconnect of the multi-layer substrate and surrounding the first via pad; and a non-circular first ground pullback region between the first via pad and the non-circular first ground plane for electrically isolating the first via pad from the non-circular first ground plane.

Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.

Abstract: An inductor structure is provided that is positioned within a via of a printed circuit board. The inductor structure includes a via extending through a printed circuit board. The inductor structure includes at least one coil of an electrically conductive material beginning at a first opening to the via continuously present on a sidewall of the via encircling a center of the via extending to a second opening of the via opposite the first opening of the via. It further includes at least electrode present in contact with an end of the coil at said first or second opening.

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, a semiconductor chip on the redistribution substrate and including a chip pad electrically connected to the redistribution substrate, and a conductive terminal on the redistribution substrate. The redistribution substrate includes a first dielectric layer, a first redistribution pattern, a second dielectric layer, a second redistribution pattern, and a first insulative pattern. The first redistribution pattern electrically connects the chip pad and the second redistribution pattern. The first insulative pattern has a first surface in contact with the first redistribution pattern and a second surface in contact with the second redistribution pattern. The second surface is opposite to the first surface. A width at the first surface of the first insulative pattern is the same as or greater than a width at the second surface of the first insulative pattern.

Abstract: An electrostatic chuck includes: a ceramic plate; an adsorption electrode that is built in the ceramic plate; and a plurality of connection pads that are built in the ceramic plate to be electrically connected to the adsorption electrode. The connection pads are arranged stepwise.

Abstract: A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and exposed through the cavity; wherein the second insulating layer includes a first portion disposed on an upper surface of the first insulating layer in a region where the cavity is formed; and a second portion other than the first portion, and wherein a thickness of the first portion is smaller than a thickness of the second portion.

Abstract: An electronic board includes: a board including an upper surface ground on an upper surface; at least one first land formed on the upper surface and connected to a first signal line; at least one second land formed on the upper surface and connected to a second signal line; at least one third land disposed on the upper surface between the first land and the second land and connected to the upper surface ground; and at least one fourth land disposed on the upper surface on a side opposite to the third land and connected to the upper surface ground, the first land being interposed between the third land and the fourth land.

Abstract: A composite material structure that prevents occurrence of galvanic corrosion while exposing a part of a conductor embedded in a conductive resin portion as a connecting portion, is provided. The composite material structure includes a conductive resin portion formed of an electrically conductive reinforced resin in which conductive fibers are contained in a base material, a conductor formed of a conductive material and embedded in the conductive resin portion with a part of the conductor exposed as a connecting portion for electrical connection with another component, and an insulator that is formed of an insulating material and that is at least partially embedded in the conductive resin portion so as to be interposed between the conductive reinforced resin and the conductor so as to prevent the connecting portion of the conductor from contacting the conductive reinforced resin.

Abstract: An electronics module for a transmission control unit may including one or more of the following: a printed circuit board populated with electronic components that are attached to an upper surface and/or a lower surface of the printed circuit board, and electrically connected thereto, and a media-tight protective layer, which covers one or more electronic components and connecting points between the one or more electronic components and the printed circuit board, where there is a cooling element for cooling the electronic components on one side of the printed circuit board, where the cooling element is connected to the printed circuit board and houses the electronic components that are to be cooled, and where the media-tight protective layer covers a transition region between the printed circuit board and the cooling element along the entire periphery of the cooling element.

Abstract: A multilayer resin substrate includes a stacked body including first resin layers made of a thermoplastic resin, conductor patterns on the stacked body, and a protective layer including a second resin layer made of a thermosetting resin. The stacked body includes first and second main surfaces, and a bent portion. One of the conductor patterns located at the bent portion is located only inside the stacked body. The protective layer covers at least the bent portion, on the main surface of the stacked body.

Abstract: A printed wiring board includes a resin insulating layer, via conductors formed in the resin insulating layer, metal posts formed on the via conductors, respectively, and a solder resist layer formed on the resin insulating layer such that the metal posts have lower portions embedded in the solder resist layer and upper portions exposed from the solder resist layer, respectively. The metal posts are formed such that each of the metal posts has a top portion having a diameter in a range of 0.8 to 0.9 times a diameter of a respective one of the lower portions of the metal posts.

Abstract: A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.

Abstract: A wiring substrate includes a first insulation layer, a first through hole extending through the first insulation layer in a thickness-wise direction, a first via wiring formed in the first through hole, a second insulation layer formed on an upper surface of the first insulation layer, a first recess formed in a lower surface of the second insulation layer and connected to the first through hole, an opening formed in an upper surface of the second insulation layer and connected to the first recess, a second recess formed in an upper surface of the first via wiring and connected to the first recess, a second via wiring formed in the opening, the first recess, and the second recess, and a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring.

Abstract: A broadside coupled coplanar inductor device includes first and second coplanar inductors in which the conductors of the first and second coplanar inductors are broadside coupled. The conductors are located one above the other at a first distance and the return paths are located to the side of the respective first and second conductor signal paths at a second distance. One or both of the dimensions of the first and second first distances is defined so as to maximize a mutual inductance between the conductors. First and second driver circuit apply voltages across each conductor. The input pulse width modulation signals applied to the first and second driver circuits are 180 degrees out of phase.

Abstract: A component carrier includes a glass core having a first main surface and a second main surface; a first electrically insulating layer structure applied on the first main surface of the glass core; a first electrically conductive layer structure applied on the first electrically insulating layer structure; and at least one inner hole extending through the glass core and the first electrically insulating layer structure.

Abstract: A method for producing a metal-ceramic substrate with a plurality of electrically conductive vias includes: attaching a first metal layer in a planar manner to a first surface side of a ceramic layer; after attaching the first metal layer, introducing a copper hydroxide or copper acetate brine into a plurality of holes in the ceramic layer delimiting a via, to form an assembly; converting the copper hydroxide or copper acetate brine into copper oxide; subjecting the assembly to a high-temperature step above 500° C. in which the copper oxide forms a copper body in the plurality of holes; and after converting the copper hydroxide or copper acetate brine into the copper oxide, attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side. The copper body produces an electrically conductive connection between the first and the second metal layers.

Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.

Abstract: A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.

Abstract: A transmission line includes first, second, and third signal lines defining a parallel portion. No conductor connecting the first ground conductor and the second ground conductor is between the first signal line and the second signal line, and the first signal line is closer to the ground connection conductor than the second signal line. A closest frequency difference between a fundamental wave of one of the first signal and the second signal and a fundamental wave or a higher harmonic wave of the other of the first signal and the second signal is equal to or larger than a closest frequency difference between a fundamental wave of one of the first signal and the third signal and a fundamental wave or a higher harmonic wave of the other of the first signal and the third signal.

Abstract: A semiconductor device and related manufacturing methods are provided. The semiconductor device includes one interconnection structure including: a substrate; a first insulating dielectric layer underneath a lower surface of the substrate; a second insulating dielectric layer on an upper surface of the substrate; a first connecting pad disposed within the first insulating dielectric layer; a metal connection member penetrating through a portion of the second insulating dielectric layer, the substrate and a portion of the first insulating dielectric layer to connect the first connecting pad; and a second connecting pad disposed within the second insulating dielectric layer and connecting the metal connection member. The metal connection member may be a Through-Silicon Via (TSV). The device includes a confined air gap surrounding the metal connection member, which improves the performance and reliability of the device.

Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.