Feedthrough Patents (Class 174/262)
  • Patent number: 10726878
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Patent number: 10727190
    Abstract: A multilayer circuit board having a central conductor and core layers between a first set of alternating layers and a second set of alternating layers. The central conductor includes a first compound via through the first set of alternating layers, and a second compound via through the second set of alternating layers. A gap extends from a first side of the multilayer circuit board to a second side of the multilayer circuit board. A first array of ground protrusions surrounds the gap and is arranged in a first pattern on the first side of the multilayer circuit board. A second array of ground protrusions surrounds the gap and is arranged in a second pattern on the second side of the multilayer circuit board. A ground path connects the first array of ground protrusions to the second array of ground protrusions.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Tektronix, Inc.
    Inventor: George S. Curtis
  • Patent number: 10715111
    Abstract: An elastic wave filter device includes first and second reception filters, an input terminal, output terminals, and reference terminals provided on a piezoelectric substrate. The first reception filter includes series resonators and parallel resonators, and the second reception filter includes series resonators and parallel resonators. The reference terminal connected to the parallel resonator connected so as to be closest to the output terminal among the parallel resonators included in the first reception filter, and the reference terminal connected to the parallel resonator connected so as to be closest to the output terminal among the parallel resonators included in the second reception filter, are separated from each other on the piezoelectric substrate.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 14, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Motoki Ozasa
  • Patent number: 10707009
    Abstract: A thin film-type inductor includes a body including a support member having a through-hole filled with a magnetic material and a via hole, a coil disposed on at least one side of the support member and including a plurality of coil patterns, and a magnetic material sealing the support member and the coil. Each of the coil patterns includes a first conductor layer, a second conductor layer, and a third conductor layer. The second conductor layer is disposed on a side surface of the via hole, and is disposed to seal a lower surface of the via hole.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Joung Gul Ryu, Byeong Cheol Moon, Jin Hyuk Jang
  • Patent number: 10701800
    Abstract: An example method includes linking a transmit line and receive line to a respective via, and printing two paths to each via, wherein each path is interrupted by two pairs of contacts. When a first resistor is in a first pair of contacts at a receive via, first signal is formed between a receive point of a first connector and the receive line. When a first capacitor is in first pair of contacts at a transmit via, second signal is formed between transmit point of first connector and the transmit line. When a second resistor is in second pair of contacts at receive via, third signal is formed between receive point of a second connector and the receive line. When a second capacitor is in second pair of contacts at transmit via, fourth signal is formed between a transmit point of second connector and the transmit line.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vincent Nguyen, Sung Hsia Kuo, Ho M Lai
  • Patent number: 10693440
    Abstract: An acoustic wave device includes: a first substrate having a first surface on which an acoustic wave element is located; a second substrate having a second surface on which a functional element is located; a third substrate having a third surface, which faces the first and second surfaces, and a fourth surface being opposite to the third surface, a first metal layer separated from the acoustic wave element and a wiring line in the first substrate and connecting the first and third surfaces; a second metal layer separated from the functional element and a wiring line in the second substrate and connecting the second and third surfaces; a first metal pattern located on the third surface, being in contact with the first and second metal layers, and connecting the first and second metal layers; and a terminal located on the fourth surface and electrically connectable to the first metal pattern.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Satoru Ohkubo, Kazuyuki Imagawa, Ryo Miyamoto
  • Patent number: 10692737
    Abstract: An electronics package includes a multilayer interconnect structure comprising insulating substrate layers and conductor layers. The electronics package also includes an electrical component comprising I/O pads electrically coupled to the conductor layers and conductive through vias extending through at least two insulating substrate layers and electrically connected to at least a portion of the I/O pads. The conductor layers include a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming direct electrical and physical connections with a conductive through via electrically connected to a ground I/O pad of the plurality of I/O pads. The conductor layers also include a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming direct electrical and physical connections with a conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: June 23, 2020
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kaustubh Ravindra Nagarkar
  • Patent number: 10665662
    Abstract: A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: May 26, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JinHee Jung, HyungSang Park, SungSoo Kim
  • Patent number: 10667390
    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 26, 2020
    Assignee: SANMINA CORPORATION
    Inventors: Shinichi Iketani, Dale Kersten, George Dudnikov, Jr.
  • Patent number: 10638598
    Abstract: The present invention aims to provide a ground member that can be mounted on any position, wherein misalignment is less likely to occur between conductive filler particles of the ground member and a shielding layer of a shielding film when a shielded printed wiring board including the ground member is repeatedly heated and cooled to mount components thereon. The ground member of the present invention includes: a conductive external connection member having a first main surface and a second main surface opposite to the first main surface; conductive filler particles disposed adjacent to the first main surface; and an adhesive resin for fixing the conductive filler particles to the first main surface, wherein each conductive filler particle includes a low-melting-point metal.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 28, 2020
    Assignee: TATSUTA ELECTRIC WIRE & CABLE CO., LTD.
    Inventors: Yuusuke Haruna, Takahiko Katsuki, Tsuyoshi Hasegawa, Hiroshi Tajima
  • Patent number: 10622330
    Abstract: A flexible display panel, a preparation method thereof and a flexible display device are provided. The flexible display panel includes a flexible substrate; a back protective film arranged on a back surface of the flexible substrate; an adhesive layer arranged between the flexible substrate and the back protective film; and a support structure arranged in the adhesive layer between the flexible substrate and the back protective film and in a position corresponding to each of integrated circuit bumps, the support structure being configured to support the integrated circuit bumps in the adhesive layer.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: April 14, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tao Sun, Liqiang Chen, Hongli Wang
  • Patent number: 10595407
    Abstract: The present disclosure relates to a PCB laminated structure, including a first substrate; a second substrate disposed to overlap with the first substrate on the top and bottom; and an interposer assembly provided between the first substrate and the second substrate to allow electromagnetic connection between the first and second substrates, wherein the interposer assembly includes a housing configured to form a closed region along a top surface circumference of the first substrate and a bottom surface circumference of the second substrate to support the first and second substrates; a signal via connected to the first and second substrates, respectively, to transmit electromagnetic signals between the first substrate and the second substrate; and a ground via connected to the housing to serve as a ground, and spaced a set distance from the signal via at one side of the signal via.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: March 17, 2020
    Assignee: LG Electronics Inc.
    Inventors: Jaehyuk Kim, Kyungcheol Paek, Chaejoo Lim
  • Patent number: 10559399
    Abstract: A multi-phase busbar can include a first conducting layer, a first conducting pin, a first insulating layer, and a second conducting layer. The first conducting layer can include a sheet metal coated with an electrically insulating material. The first conducting pin can be mounted to the first conducting layer. The first conducting pin can extend in a direction perpendicular to the first conducting layer. The first insulating layer of a rigid insulating material can be arranged on the first conducting layer. The first insulating layer can define an opening through which the first conducting pin projects. The second conducting layer can include a sheet metal coated with an electrically insulating material, the second conducting layer comprising a first pinhole through which the first conducting pin projects and a second conducting pin which extends in a direction parallel to the first conducting pin.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: February 11, 2020
    Assignee: ABB Schweiz AG
    Inventors: Rudi Velthuis, Andrej Krivda, Jens Rocks
  • Patent number: 10561017
    Abstract: A circuit board includes a first wiring layer and a build-up structure. The build-up structure includes at least one dielectric layer and at least one second wiring layer. Each dielectric layer and each second wiring layer are alternately arranged. The at least one dielectric layer comprises an outermost dielectric layer. The at least one second wiring layer is formed on a side of the outermost dielectric layer, and comprises an outermost second wiring layer. A portion of the first wiring layer is embedded in a side of the outermost dielectric layer facing away the outermost second wiring layer, a remaining portion of the first wiring layer protrudes from the outermost dielectric layer. A method for manufacturing a circuit board is provided.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: February 11, 2020
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Chih-Chieh Fu
  • Patent number: 10524399
    Abstract: A device is provided with a PWM signal generating circuit, a gate driver and a transmission line connecting them. The transmission line transmits a PWM signal output from the PWM generator as an input signal for the gate driver. A noise suppression member is provided to at least a part of a periphery of the transmission line. The noise suppression member has a structure that magnetic powder is dispersed in a binder and has an imaginary part ?? of a complex magnetic permeability that is greater than or equal to 5 and smaller than or equal to 30 in a range of 500 MHz to 3 GHz. The noise suppression member has a thickness t greater than or equal to 20 ?m. The noise suppression member is disposed apart from a conducting wire of the transmission line by a distance greater than 0.05 mm or smaller than or equal to 5 mm.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: December 31, 2019
    Assignee: TOKIN CORPORATION
    Inventors: Masaki Kurimoto, Koichi Kondo, Masashi Ikeda
  • Patent number: 10524353
    Abstract: To enhance the isolation between signal lines for transmitting high-frequency signals included in a circuit board. A circuit board includes a plurality of signal lines for transmitting high-frequency signals, a ground electrode positioned between the plurality of signal lines and spaced apart from each of the plurality of signal lines, and a plurality of via conductors connected to the ground electrode. When the circuit board is seen in plan view, the ground electrode has a protruded and recessed area in at least a section of an outer edge thereof, the protruded and recessed area outwardly protruded and inwardly recessed. The plurality of via conductors is positioned in the protruded and recessed area so as to match with a protruded and recessed shape of the protruded and recessed area.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 31, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takeshi Kogure
  • Patent number: 10512173
    Abstract: A wiring board of the present disclosure includes: an insulating base having a first surface including a mounting region and a second surface connected to an external board; a power supply conductor including a first planar conductor, and first linear conductors; a grounding conductor including a second planar conductor, and second linear conductors; power supply terminals, being electrically connected to the first planar conductor; and grounding terminals being electrically connected to the second planar conductor.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: December 17, 2019
    Assignee: Kyocera Corporation
    Inventors: Toshihiro Hiwatashi, Rintaro Kamimura
  • Patent number: 10497847
    Abstract: A heat dissipation substrate structure includes a multilayer circuit board including a core board and build-up boards, a heat conduction layer, a cavity structure, bonding pads, and vias. The heat conduction layer is disposed within the core board, or on a surface of the core board, or on a surface of one of the build-up boards. The cavity structure is in the multilayer circuit board with respect to the heat conduction layer and exposes a first surface of the heat conduction layer. The bonding pads are on the surface of the multilayer circuit board at a side of a second surface of the heat conduction layer. The portions of the vias are connected to portions of the bonding pads and the heat conduction layer. Accordingly, heat flow can be distributed via a heat dissipation path from the bonding pads through the vias to the heat conduction layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 3, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Wen-Fang Liu, Shao-Chien Lee, Chen-Wei Tseng, Zong-Hua Li
  • Patent number: 10490887
    Abstract: A method for producing an intermediate printed circuit board product (80) with an antenna structure (5), including steps of providing a ground layer (10) including optionally a release layer (20) that is removably positioned (22) on an antenna subarea (12) of an exterior side (11) of the ground layer (10); attaching a dielectric insulating layer (30) on the exterior side (11) of the ground layer (10) that is if applicable partly covered by the release layer (20); attaching a conducting layer (40) on an exterior side (31) of the dielectric insulating layer (30); laminating of the layers (10, 20, 30, 40) to receive a first semi-finished product (50); manufacturing of an antenna cavity (60) throughout the conducting layer (40) and the dielectric insulating layer (30) with a ground-plane area (62) that is if applicable made up of the release layer (20); attaching a compound signal layer (70) on the conducting layer (40) covering the antenna cavity (60); and laminating of the layers (50, 70) to receive the interme
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 26, 2019
    Assignee: AT&S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
    Inventor: Erich Schlaffer
  • Patent number: 10485097
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: November 19, 2019
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 10483666
    Abstract: A socket comprises a housing made of an insulating board and a plurality of contacts arranged on a first surface of the housing. The housing has a plurality of passageways each extending through the housing and having an inner wall surface plated with a conductive material. The housing also has a conductive pad formed on the first surface of the housing that is electrically continuous with the conductive material of the inner wall surface. Each of the contacts includes a contact portion positioned above the first surface of the housing and configured to be elastically deformed by a contact pad electrically connected with the contact, an insertion portion inserted into one of the passageways and configured to be elastically deformed and pressed by the inner wall surface of the passageway, and a joint portion joined to the conductive pad.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 19, 2019
    Assignee: Tyco Electronics Japan G.K.
    Inventor: Hidenori Taguchi
  • Patent number: 10485102
    Abstract: A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 ?m, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: November 19, 2019
    Assignees: Sumitomo Electric Industries, Ltd., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Shingo Kaimori, Masaaki Yamauchi, Kentaro Okamoto, Satoshi Kiya, Kazuo Murata
  • Patent number: 10475733
    Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: November 12, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
  • Patent number: 10461004
    Abstract: An integrated circuit substrate and its method of production are described. The integrated circuit substrate comprises at least an internal conductive trace layer formed by one or more internal conductive traces that is deposited on a partially or completely removable carrier; and a dielectric layer encapsulating the internal conductive trace layer through a lamination process or a printing process. The top surface of the topmost internal conductive trace layer and bottom surface of the bottommost internal conductive trace layer are exposed and not covered by the dielectric layer. External conductive trace layer can also be deposited outside of the dielectric layer. The internal conductive trace layers are deposited through plating or printing of an electronically conductive material, whereas the external conductive trace layer is deposited through electroless and electroplating, or printing of the electronically conductive layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 29, 2019
    Assignee: QDOS FLEXCIRCUITS SDN BHD
    Inventors: Zalina Binti Abdullah, Roslan Bin Ahmad, Poh Cheng Ang, Poh Choon Whong, Hai San Tew, Shin Hung Hwang, Chee Can Lee, Tiyagarajan S/O Arumugham
  • Patent number: 10453803
    Abstract: A semiconductor wiring substrate includes a first wiring layer, a second wiring layer stacked on the first wiring layer, and a dielectric layer sandwiched between the first wiring layer and the second wiring layer. The first wiring layer includes first signal lines and first grounding lines which are interleaved and spaced apart in the first wiring layer. The second wiring layer includes second signal lines and second grounding lines which are interleaved and spaced apart in the second wiring layer. An orthographic projection of one of the second signal lines to the first wiring layer is located between each two adjacent ones of the first signal lines.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 22, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hsuan Wang, Ting-Hao Wang, Yen-Chih Chiu
  • Patent number: 10448509
    Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Choon Kuan Lee, Chin Hui Chong
  • Patent number: 10424823
    Abstract: A transmission line of the disclosure includes: a first line; a second line having characteristic impedance higher than characteristic impedance of the first line; and a third line. The transmission line transmits a symbol that corresponds to a combination of signals in the first line, the second line, and the third line.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: September 24, 2019
    Assignee: Sony Corporation
    Inventor: Tatsuya Sugioka
  • Patent number: 10420213
    Abstract: Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 17, 2019
    Assignee: Apple Inc.
    Inventors: Mark J. Beesley, Albert A. Onderick, II, Anne M. Mason, Craig A. Gammel, Shawn X. Arnold
  • Patent number: 10410683
    Abstract: Systems and methods for tightly coupled differential vias are described. the storage system device includes a storage drive and a printed circuit board (PCB) of the storage drive. In some embodiments a first via is connected to a first trace routed on a first layer of the PCB, and a second via is connected to a second trace routed on the first layer of the PCB. In some cases, a distance between the first via and the second via is about 1.5 times or less a spacing between the first trace and the second trace.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 10, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Vinod Arjun Huddar
  • Patent number: 10405418
    Abstract: A differential signal transmitting circuit board includes a substrate, at least two differential conductive elements, and at least one insulating element. The differential conductive elements are disposed in the substrate. The insulating element is disposed in the substrate. The insulating element is close to or contacted to the differential conductive elements. A material of the substrate has a first equivalent dielectric constant. A material of the insulating element has a second equivalent dielectric constant. The first equivalent dielectric constant is different from the second equivalent dielectric constant.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 3, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Min Hsu, Shih-Hsien Wu
  • Patent number: 10405428
    Abstract: According to one embodiment, an electronic device includes a first substrate including a first basement and a first conductive layer, a second substrate including a second basement which is disposed to be apart from the first conductive layer and includes a first surface opposed to the first conductive layer and a second surface opposite to the first surface, and a second conductive layer disposed on the second surface, the second substrate including a first hole passing through the second basement, and a connecting material passing through the first hole to electrically connect the first conductive layer and the second conductive layer, wherein the first hole is shaped as a funnel.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Japan Display Inc.
    Inventors: Shuichi Osawa, Yoshikatsu Imazeki, Yoichi Kamijo, Yoshihiro Watanabe
  • Patent number: 10405426
    Abstract: A printed wiring board includes: a core substrate having a core layer, first and second conductor layers, and through-hole conductors penetrating through the core layer and connecting the conductor layers; and first and second build-up layers each including an insulating layer, an inner side conductor layer, an outermost insulating layer, an outermost conductor layer, and a solder resist layer. Each of the conductor layers includes conductor circuits having substantially a trapezoid cross-sectional shape, and spaces between adjacent conductor circuits, and includes a metal foil, a seed layer, and an electrolytic plating film. The inner side conductor layers have the smallest minimum circuit width, the smallest minimum space width and the largest base angle among the conductor layers. The insulating layers have the smallest ten-point average roughness rz3, rz7 among the ten-point average roughness rz3, rz7, rz1, rz2, rz5 and rz9 of the core layer, insulating layers and outermost insulating layers.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 3, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Toshihide Makino, Hidetoshi Noguchi
  • Patent number: 10390430
    Abstract: A circuit board includes a board defining a holding slot and a connector. The connector includes a conductive column and a pad fixed to one end of the conductive column. The pad is received within the holding slot. The conductive column is fixed within the board. The pad is soldered to a connecting portion of an electrical component. The pad defines a first through hole receiving solder when the connecting portion of the electrical component is soldered to the pad.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 20, 2019
    Assignees: HONGFUJIN PRECISION INDUSTRY (WUHAN) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hou-Yuan Chou, Yi-Chih Wu
  • Patent number: 10375838
    Abstract: A printed circuit board, and a method of fabricating the printed circuit board is disclosed. The printed circuit board includes at least one coaxial via. A hollow via is disposed in the printed circuit board. A metal sleeve is formed around the circumference of said hollow via. An inner conductive path is disposed in the hollow via. Additionally, an insulating material is disposed in the hollow via, between the conducting path and the metal sleeve. The conductive path is used to connect signal traces disposed on two different layers of the printed circuit board. In some embodiments, these signal traces carry signals having a frequency above 1 GHz, although the disclosure is not limited to this embodiment.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: August 6, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Glenn A. Brigham, Richard J. Stanley, Bradley Thomas Perry, Patrick J. Bell
  • Patent number: 10375822
    Abstract: Various circuit boards and systems are disclosed. In one aspect a system includes a circuit board and n differential signal via pairs. Each of the n differential signal via pairs has a first signal via and a second signal via and an electrical wall between the first signal via and the second signal via. There is a midline between every two adjacent differential via pairs. There are n ground return path vias. Each of the n ground return path vias is positioned substantially along one of the midlines and not on one of the electrical walls.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 6, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yuan Li, James R. Foppiano, Jonathan P. Dowling, Gerald J. Merits, Manjunath Shivappa, Wasim I. Ullah, Claude Hilbert
  • Patent number: 10374386
    Abstract: A chip may include a first substantially planar isolation layer with a first surface and a second surface opposite the first surface. The chip may include a first substantially planar conduction layer with a first surface positioned adjacent to the second surface of the first isolation layer and a second surface opposite the first surface. The chip may include a second substantially planar isolation layer with a first surface positioned adjacent to the second surface of the first conduction layer and a second surface opposite the first surface. The chip may include a second conduction layer etched on the second surface of the second isolation layer. The second conduction layer may include an anode trace, a cathode trace, and an optical transmitter positioned on the cathode trace. The chip may include one or more vias through the second isolation layer electrically coupling the anode trace with the first conduction layer.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 6, 2019
    Assignee: FINISAR CORPORATION
    Inventors: Jianwei Mu, Frank Lei Ding, Tao Wu, Hongyu Deng, Maziar Amirkiai
  • Patent number: 10375828
    Abstract: A printed wiring board includes: a core substrate having a core layer and first and second conductor layers; a first build-up layer including a first insulating layer, an inner first conductor layer, an outermost first insulating layer, and an outermost first conductor layer; and a second build-up layer including a second insulating layer, an inner second conductor layer, an outermost second insulating layer, and an outermost second conductor layer. Each conductor layer includes metal foil, seed layer, and electrolytic plating film, t1/T1, t2/T2, u1/U1 and u2/U2 are smaller than 1, and s1/S1 and s2/S2 are larger than 1, where t1, t2, u1, u2, s1 and s2 are electrolytic plating film thicknesses of the first and second and outermost and inner first and second conductor layers, T1, T2, U1, U2, S1 and S2 are metal foil thicknesses of the first and second and outermost and inner first and second conductor layers.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 6, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Toshihide Makino, Hidetoshi Noguchi
  • Patent number: 10362672
    Abstract: A resin multilayer substrate includes a laminate including a plurality of resin layers and an interlayer connecting conductor which extends through at least one of the plurality of resin layers and is directly exposed to an outside of the laminate.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: July 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Daisuke Tsuruga
  • Patent number: 10356897
    Abstract: A first land and a first ground pattern generate a first parasitic capacitance CLAND by capacitive coupling with a first insulating layer interposed therebetween. Then, the first parasitic capacitance CLAND is defined as a predetermined capacitance that suppresses an impedance of a via part from changing due to a change in an inductance component of the via part with respect to a first transmission line. As a result, it is possible to match the impedance of the via part with a impedance of the first transmission line by adjusting the first parasitic capacitance CLAND caused by the first land and the first ground pattern. Therefore, it is possible to prevent the transmission characteristics of the multilayer substrate from deteriorating without requiring the disposition of cavities such as through holes in the multilayer substrate.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 16, 2019
    Assignee: DENSO CORPORATION
    Inventors: Kiyokazu Akiyama, Yasunari Yanagiba
  • Patent number: 10340214
    Abstract: A carrier base material-added wiring substrate includes a wiring substrate and a carrier base material. The wiring substrate includes an insulation layer, a wiring layer arranged on a lower surface of the insulation layer, and a solder resist layer that covers the lower surface of the insulation layer and includes an opening that exposes a portion of the wiring layer as an external connection terminal. The carrier base material is adhered by an adhesive layer to the solder resist layer. The carrier base material includes an opening that is in communication with the opening of the solder resist layer and exposes the external connection terminal. The opening of the carrier base material has a diameter that is smaller than that of the opening of the solder resist layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 2, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Junji Sato, Hitoshi Kondo, Katsuya Fukase
  • Patent number: 10340182
    Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 2, 2019
    Assignee: International Business Machines corporation
    Inventors: James P. Doyle, Geraud Dubois, Nicholas C. Fuller, Teddie P. Magbitang, Robert D. Miller, Sampath Purushothaman, Willi Volksen
  • Patent number: 10332903
    Abstract: A method for manufacturing a multi-layer structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a substrate, and the stack includes a multi-layer area and a contact area adjacent to the multi-layer area. Next, a plurality of first openings are formed in the contact area. Then, a conductive connecting structure is formed on the stack and into the first openings. Thereafter, the stack is patterned. The conductive connecting structure continuously extends on the contact area and into the first openings to maintain an electrical connection among the conductive layers while the stack is patterned.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: June 25, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10334719
    Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 25, 2019
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Patent number: 10334740
    Abstract: An electronic-component mount substrate includes a substrate having a first principal surface and a second principal surface opposite to the first principal surface; a mount electrode for mounting an electronic component on the first principal surface, the mount electrode having a first slit and sandwiching the first slit; a plane electrode surrounding the mount electrode in a plan view and having a second slit; a connection electrode connecting the mount electrode with the plane electrode; and an outer electrode on the second principal surface. The connection electrode overlaps the outer electrode and an outer edge of the outer electrode surrounds the connection electrode in a perspective plan view.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 25, 2019
    Assignee: Kyocera Corporation
    Inventor: Kensaku Murakami
  • Patent number: 10327340
    Abstract: A method for producing circuit board, including: adhering plastic deformable insulating material onto surface of laminate, which contains second-metal-layer of second metal, and first-metal-layer in pattern on second-metal-layer, and the surface of the laminate is surface of second-metal-layer where first-metal-layer is formed, and surface of first-metal-layer, followed by curing the material, and removing second-metal-layer to form plate structure to which first-metal-layer in pattern is formed; opening hole in cured material from surface of the plate structure opposite to surface thereof where first-metal-layer is formed, until the hole reaches first-metal-layer; filling the hole with electroconductive paste, to form the plate structure filled therewith; and laminating one plate structure filled therewith with the other plate structure filled therewith in manner that first-metal-layer of one plate structure filled therewith faces opening of the hole of other plate structure filled therewith, wherein first-m
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: June 18, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kenji Iida, Takashi Nakagawa, Seigo Yamawaki, Yasuhiro Karahashi, Junichi Kanai, Koji Komemura
  • Patent number: 10303838
    Abstract: Dynamic electronic printed circuit board (PCB) design is provided. A test net on a PCB is dynamically created utilizing a first rule defining a net parameter and a second rule defining a padstack geometric parameter. A first evaluation of one or more nets having a first padstack is performed against the first rule. A second evaluation of both the first padstack and a reference padstack determined to be adjacently positioned to the first padstack is performed against the second rule. Based on the evaluations, a potential test net having a potential test padstack is dynamically selected from the evaluated nets. The selected potential test net is dynamically transformed into the test net. The dynamic transformation includes modifying the potential test padstack and/or the reference padstack utilizing the second rule. The dynamic creation of the test net improves the efficiency of electronic PCB design by mitigating time and footprint consumption.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Christo, David L. Green, Julio A. Maldonado, Diana D. Zurovetz
  • Patent number: 10285269
    Abstract: A multilayer substrate is manufactured by first manufacturing a first substrate by stacking and hot-pressing resin base materials of the first substrate and then adjacently stacking and hot-pressing the first substrate and resin base materials that constitute a second substrate at a position overlapping with each other in a stacking direction. The position in the stacking direction between the resin base materials in the first substrate is located at almost a middle position in the stacking direction of a resin base material of the second substrate, and is different from the position between the layers of the resin base materials of the second substrate.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: May 7, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kuniaki Yosui
  • Patent number: 10285260
    Abstract: The flexible printed circuit board includes a base layer, a first circuit layer and a second circuit layer, the first circuit and the second circuit layer formed on both sides of the base layer; conducting holes extending through the base layer and the first copper layer, the conducting holes include annular copper ring embedded in the first circuit layer. A height difference between a surface of the annular copper ring and a surface of the first circuit layer is in a range from 0 to 3 micrometers. A method for manufacturing the flexible printed circuit board is also provided.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 7, 2019
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Xian-Qin Hu, Yan-Lu Li, Li-Bo Zhang
  • Patent number: 10276909
    Abstract: A structure can include a first element and a carrier bonded to the first element along an interface. A waveguide can be defined at least in part along the interface between the first element and the carrier. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel, as viewed from a side cross-section of the structure. Various millimeter-wave or sub-terahertz components or circuit structures can also be created based on the waveguide structures disclosed herein.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 30, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Javier A. DeLaCruz, Belgacem Haba
  • Patent number: 10263352
    Abstract: An electrical contact pad for electrically contacting a connector includes a first region having a first length in a longitudinal direction, and a second region having a second length in the longitudinal direction that is greater than the first length. The first region is arranged to contact a first arm of the connector and the second region is arranged to contact a second arm of the connector. The first length being smaller than the second length results in a beneficial increases the impedance of the electrical contact pad. A chamfered edge of the contact pad results in an additional beneficial increase in the impedance of the electrical contact pad.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 16, 2019
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Graham Harry Smith, Jr., Scott Eric Walton, Michael Frank Cina