Feedthrough Patents (Class 174/262)
  • Patent number: 11044805
    Abstract: The present disclosure provides a double-sided two-dimensional coding, includes a transparent medium layer on which a metal layer is plated, and a two-dimensional coding image is fused through the metal layer. The present disclosure also provides a flexible printed circuit and manufacturing method for a double-sided two-dimensional coding. By lasering the metal layer corresponding to the transparent medium layer, the metal layer is fused through to form a two-dimensional coding image, and the transparent medium layer is retained as a carrier of the two-dimensional coding image, and an effect of reading the two-dimensional coding on both sides can be achieved.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 22, 2021
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO.LTD.
    Inventor: Hao-Yang Xiao
  • Patent number: 11039535
    Abstract: A method includes providing an electrically conductive layer structure on top of an electrically insulating layer structure, forming a window in the electrically conductive layer structure and removing material of the electrically insulating layer structure below the window by a first laser beam, and subsequently removing further material of the electrically insulating layer structure below the window by a second laser beam having a smaller size than a size of the window.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 15, 2021
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Seok Kim Tay, Abderrazzaq Ifis, Haina Wu
  • Patent number: 11031329
    Abstract: A method of fabricating a packaging substrate is provided, which includes: forming on a carrier a conductor layer having a plurality of openings; forming a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body disposed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with the conductive pad and less in width than the conductive pad; forming a plurality of conductive posts on the conductive pads; forming on the carrier a first insulating layer that encapsulates the conductive bumps and the conductive posts; removing the carrier; and removing the entire conductor layer to expose the post bodies from a first surface of the first insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 8, 2021
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chu-Chin Hu, Shih-Ping Hsu, Che-Wei Hsu, Chin-Ming Liu, Chih-Kuai Yang
  • Patent number: 11032917
    Abstract: A circuit carrier board includes a first substrate and a second substrate bonding to the first substrate. The first substrate includes a first circuit layer connecting to a plurality of conductive structure. The conductive structures connect to electronic elements. The second substrate contacts the first circuit layer. The second substrate includes a plurality of stacked dielectric layers, and a plurality of second circuit layers are disposed in the dielectric layers. The bottommost layer of the second circuit layers is exposed outside of the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first circuit layer. The conductive structure includes a pad and a conductive via. The pad electrically connects to the first circuit layer. A linewidth of the first circuit layer is smaller than a linewidth of the second circuit layer. A manufacturing method of the circuit carrier board is also provided.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: June 8, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Fu-Yang Chen
  • Patent number: 11011551
    Abstract: An array substrate and display apparatus, the array substrate comprising a base substrate (10) and signal lines (VDD, VSS) provided on the base substrate (10), wherein at least one electrically conductive element (12) corresponding to the signal lines (VDD, VSS) is further provided on the base substrate (10), the signal lines (VDD, VSS) are connected in parallel with corresponding electrically conductive elements (12), and the electrically conductive elements (12) corresponding to different signal lines (VDD, VSS) are insulated from one another. Thus, resistance of the signal lines (VDD, VSS) can be reduced and the display effect can be improved.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 18, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiangdan Dong, Young Yik Ko, Jinsan Park
  • Patent number: 10998258
    Abstract: A circuit carrier includes a substrate, a laminar circuit structure, a metal heat slug, a first fixing piece, and a second fixing piece. The laminar circuit structure is disposed over the substrate and includes a plurality of dielectric layers and circuits in the dielectric layers. The metal heat slug is disposed in the laminar circuit structure. The first fixing piece is disposed on the first side of the upper surface of the metal heat slug. The second fixing piece is disposed on the second side of the upper surface of the metal heat slug, wherein the first side is perpendicular to the second side. A method of manufacturing a circuit carrier is also provided herein.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Unimicron Technology Corp.
    Inventor: Tzu-Hsuan Wang
  • Patent number: 10999939
    Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Patent number: 10993313
    Abstract: A component carrier including a stack with a plurality of electrically insulating layer structures and/or a plurality of electrically conductive layer structures, and a non-uniform magnetic foil integrated in the stack.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 27, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Gerald Weidinger, Jonathan Silvano de Sousa
  • Patent number: 10971914
    Abstract: The heat dissipation of a circuit assembly is improved. A circuit assembly includes: a relay that includes a terminal and generates heat when energized/as a result of energization/due to being energized; a base member to which the relay is attached and in which a through hole is formed; a heat dissipation member that is provided on a side of the base member opposite to a side on which the relay is attached; a first busbar that is connected to the terminal of the relay at a position spaced apart from the base member; and a heat transfer member that is inserted into the through hole so as to be movable in a direction along the axial direction of the through hole, and that comes into contact with the first busbar and the heat dissipation member.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: April 6, 2021
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD. <
    Inventors: Yuki Fujimura, Ryoya Okamoto, Hiroshi Shimizu
  • Patent number: 10966326
    Abstract: A wiring substrate includes a laminate having a through hole and including conductor layers and insulating layers interposed between the conductor layers, solder resist layers formed on the laminate and including a first solder resist layer covering first surface of the laminate and a second solder resist layer covering second surface of the laminate and that the first and second solder resist layers have openings exposing the through hole, and a resin film covering the laminate not covered by the solder resist layers such that the resin film is formed on the first and second surfaces of the laminate inside the openings of the first and second solder resist layers without overlapping with the solder resist layers on the first and second surfaces and that the resin film covers inner wall surface inside the through hole and at least part of the first and second surfaces exposed inside the openings.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: March 30, 2021
    Assignee: IBIDEN CO., LTD.
    Inventors: Kotaro Takagi, Yoji Mori
  • Patent number: 10930594
    Abstract: In a case of a multilayer wiring structure in which an insulating layer provided between wires is made of a material having high transmittance of light in a visible range containing ultraviolet rays, wires in the upper layer and those in a lower layer may be recognized together when defects of an upper layer are visually inspected. In this case, the lower layer may be noise for the inspection of the wires in the upper layer, lowering inspection accuracy. This lowered inspection accuracy has inhibited improvement in manufacturing yields and reliability. In order to solve this issue, a multilayer wiring substrate of the disclosure includes: a substrate; and a first wire and a second wire that are provided on the substrate with an insulating layer having a light transmitting property in between, and one or both of which are subjected to a surface treatment.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: February 23, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Toshihiko Watanabe
  • Patent number: 10932373
    Abstract: Provided is a circuit board for reducing a likelihood of so-called through-hole disconnection, and enhancing connection reliability on both sides of a substrate via a through-hole. The circuit board has a substrate with the through-hole, a first conductive part covering an opening of the through-hole on one surface of the substrate in a manner blocking the opening, having a portion inserted into the through-hole from the one surface, and a second conductive part covering a second opening of the through-hole on the other surface of the substrate in a manner blocking the second opening, having a portion inserted into the through-hole from the other surface. The portion of the first conductive part inserted in the through-hole has a columnar shape forming a columnar portion having a diameter smaller than the through-hole.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: February 23, 2021
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Akihiko Hanya
  • Patent number: 10930989
    Abstract: It has been difficult to suppress electromagnetic wave that propagates within a suspended substrate. The structure according to the present invention is provided with: a first conductor plane and a second conductor plane that are disposed parallel to each other; a dielectric plane that is disposed between the first and second conductor planes via a hollow region so as to be parallel to the first and second conductor planes; a first transmission line disposed on a surface that is of the dielectric plane and that opposes the first conductor plane; and a second transmission line disposed on a surface that is of the dielectric plane and that opposes the second conductor plane, wherein the first transmission line and the second transmission line are electrically connected to each other.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 23, 2021
    Assignee: NEC CORPORATION
    Inventors: Takahide Yoshida, Hiroshi Toyao, Eiji Hankui
  • Patent number: 10905007
    Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 26, 2021
    Assignee: Qorvo US, Inc.
    Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
  • Patent number: 10904998
    Abstract: A signal trace on a printed circuit board (PCB) includes a first trace segment on a first layer of the PCB, the first trace segment having a first end coupled to a transmitter, having a second end, and having a first characteristic impedance that is matched to the transmitter. The signal trace further includes a signal via passing from the first layer of the PCB to a second layer of the PCB, the signal via having a first contact connected to the second end of the first trace segment, having a second contact on the second layer, and having a second characteristic impedance different from the first characteristic impedance. The second characteristic impedance is determined based upon a first distance between the transmitter and the first via.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: January 26, 2021
    Assignee: Dell Products, L.P.
    Inventors: Mallikarjun Vasa, Bhyrav M. Mutnury
  • Patent number: 10905013
    Abstract: In a wiring base body of a printed wiring board, a conductive post including a wiring portion and a wiring are embedded in an insulating resin film. Therefore, even in a region in which a wiring portion is formed, the wiring base body is not increased in thickness. In addition, even in a region in which a wiring is formed, the wiring base body is not increased in thickness. Therefore, it is possible to obtain a printed wiring board having high flatness by stacking a plurality of wiring base bodies and constituting a printed wiring board.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 26, 2021
    Assignee: TDK CORPORATION
    Inventors: Takaaki Morita, Seiichi Tajima, Takashi Kariya
  • Patent number: 10887989
    Abstract: A printed wiring board of the present invention includes an insulating substrate layer; a first conductive layer laminated to one surface of the substrate layer; a second conductive layer laminated to another surface of the substrate layer; and a via hole formed along an inner surface of a connection hole that is provided, in a thickness direction, through the substrate layer and the first conductive layer, the via hole electrically coupling the first conductive layer and the second conductive layer. A cross-sectional shape of the connection hole along at least one surface of the substrate layer is an irregular shape.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: January 5, 2021
    Assignees: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tadahiro Kaibuki, Daisuke Sato, Haruna Oya, Yoshiaki Yanagimoto, Atsushi Kimura, Shigeki Shimada
  • Patent number: 10887985
    Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 5, 2021
    Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
  • Patent number: 10886211
    Abstract: A wiring board includes: a Cu pad; an insulating layer covering the Cu pad and having an opening portion; a first metallic layer formed on the Cu pad in the opening portion; and a connecting terminal formed on the first metallic layer to extend from the opening portion to above an upper surface of the insulating layer. The connecting terminal includes: a seed layer formed on the first metallic layer; and a second metallic layer formed on the seed layer. A stacked body is formed of the first metallic layer and the connecting terminal and includes a constricted portion. The constricted portion is located in a certain position of the first metallic layer in a thickness direction of the first metallic layer, and a sectional area of the stacked body is the smallest at the constricted portion.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 5, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yasuyuki Yamaguchi
  • Patent number: 10887980
    Abstract: A coupled via structure includes a plate via penetrating through an board body and having first and second plates spaced apart from each other by a first gap distance, a contact pad connected to the plate via on a surface of the board body and having first and second contacts connected to the first and second plates, respectively, and a connection line connected to the contact pad on the surface of the board body and having first and second lines connected to the first and second contacts, respectively, and spaced apart from the first line by a second gap distance. Accordingly, the deviation of the characteristic impedance is reduced (or, alternatively, minimized) between the coupled via structure and the coupled signal line.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: January 5, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNKYUNKWAN UNIVERSITY
    Inventors: Dong-Yoon Seo, Jea-Eun Lee, WanSoo Nah
  • Patent number: 10888001
    Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 5, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
  • Patent number: 10877534
    Abstract: Disclosed herein is a power supply apparatus that includes a bearing plate, insulation material and a plurality of pins. The insulation material is formed on two opposite surfaces of the bearing plate. The plurality of pins are electrically connected to the bearing plate and allocated along lateral sides of the insulation material.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 29, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Jian-Hong Zeng
  • Patent number: 10872878
    Abstract: Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chuei-Tang Wang, Monsen Liu, Chen-Hua Yu
  • Patent number: 10874015
    Abstract: Provided are flexible hybrid interconnect circuits and methods of forming thereof. A flexible hybrid interconnect circuit comprises multiple conductive layers, stacked and spaced apart along the thickness of the circuit. Each conductive layer comprises one or more conductive elements, one of which is operable as a high frequency (HF) signal line. Other conductive elements, in the same and other conductive layers, form an electromagnetic shield around the HF signal line. Some conductive elements in the same circuit are used for electrical power transmission. All conductive elements are supported by one or more inner dielectric layers and enclosed by outer dielectric layers. The overall stack is thin and flexible and may be conformally attached to a non-planar surface. Each conductive layer may be formed by patterning the same metallic sheet. Multiple pattern sheets are laminated together with inner and outer dielectric layers to form a flexible hybrid interconnect circuit.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: December 22, 2020
    Assignee: CELLINK CORPORATION
    Inventors: Kevin Michael Coakley, Malcolm Parker Brown, Jose Juarez, Emily Hernandez, Joseph Pratt, Peter Stone, Vidya Viswanath, Will Findlay
  • Patent number: 10868103
    Abstract: A wiring structure and a manufacture method thereof, an organic light-emitting diode (OLED) array substrate and a display device are provided, the wiring structure includes: a base substrate, the base substrate includes a first surface and a second surface which are opposite to each other; a first conductive pattern arranged on the first surface of the base substrate and a second conductive pattern arranged on the second surface of the base substrate; the first conductive pattern is connected with the second conductive pattern through a via hole pattern penetrating through the base substrate. In the case that the wiring structure is applied to the organic light-emitting diode (OLED) array substrate, the display uniformity can be improved.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: December 15, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Li Xiao, Minghua Xuan, Shengji Yang, Xiaochuan Chen, Lei Wang, Jie Fu, Pengcheng Lu, Dongni Liu
  • Patent number: 10861914
    Abstract: A display apparatus includes a first transistor, a first pixel electrode, a second transistor, and a second pixel electrode. The first transistor includes a first drain electrode. The first pixel electrode is positioned between an edge of the display apparatus and a center of the display apparatus and includes a first recessed structure. The first recessed structure directly contacts the first drain electrode. The second transistor includes a second drain electrode. The second pixel electrode is positioned between the edge of the display apparatus and the first pixel electrode and includes at least one recessed structure. The at least one recessed structure includes a second recessed structure. The second recessed structure directly contacts the second drain electrode. A total maximum width of the at least one recessed structure is greater than a maximum width of the first recessed structure.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 8, 2020
    Inventors: Eonjoo Lee, Hyoeng-Ki Kim, Kwangwoo Park, Dongki Lee, Jin-Whan Jung
  • Patent number: 10856454
    Abstract: Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Yew San Lim, Jia Yan Go, Tin Poay Chuah, Eng Huat Goh
  • Patent number: 10856408
    Abstract: A substrate-integrated device includes a substrate layer with a first dielectric constant and one or more dielectric vias, the one or more dielectric vias each includes a via-hole extending through the substrate layer, and a dielectric material with a second dielectric constant contained within the via-hole. The second dielectric constant is larger than, preferably at least two times, the first dielectric constant.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 1, 2020
    Assignee: City University of Hong Kong
    Inventors: Kwok Wa Leung, Wai Ki Lee, Hauke Ingolf Kremer
  • Patent number: 10856406
    Abstract: A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: December 1, 2020
    Assignee: Rohm Co., Ltd.
    Inventor: Masashi Nagasato
  • Patent number: 10845553
    Abstract: Multichannel RF Feedthroughs. In some examples, a multichannel RF feedthrough includes an internal portion and an external portion. The internal portion includes a top surface on which first and second sets of traces are formed. Each set of traces is configured as an electrical communication channel to carry electrical data signals. The external portion includes a bottom surface on which the first set of traces is formed and a top surface on which the second set of traces is formed. A set of vias connects the first set of traces between the top surface of the internal portion and the bottom surface of the external portion.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 24, 2020
    Assignee: II-VI Delaware Inc.
    Inventors: Yan yang Zhao, Bernd Huebner, Tengda Du, Yuheng Lee
  • Patent number: 10842018
    Abstract: An interlayer transmission line includes a plurality of dielectric layers stacked on each other, a signal via that penetrates the plurality of dielectric layers in a stacking direction, and mutually connects signal patterns disposed on two external faces of the plurality of dielectric layers externally exposed, a ground plane that is disposed between the dielectric layers, and covers an area surrounding a circular removal region centered around the signal via, and a plurality of ground vias that penetrate at least one layer of the dielectric layers in the stacking direction of the dielectric layers, are disposed along a plurality of concentric circles centered around the signal via, and are electrically connected with the ground plane.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 17, 2020
    Assignee: DENSO CORPORATION
    Inventors: Kazumasa Sakurai, Kazuya Wakita
  • Patent number: 10840010
    Abstract: Disclosed herein is a coil component that includes a coil part in which a plurality of conductor layers and a plurality of interlayer insulting layers are alternately laminated, and an external terminal. Each of the conductor layers has a coil conductor pattern and an electrode pattern exposed from the coil part. The electrode patterns are connected to each other through a plurality of via conductors penetrating the interlayer insulating layers. At least one of the interlayer insulating layers is exposed from the coil part positioned between the plurality of electrode patterns. The external terminal is formed on the electrode patterns exposed from the coil part so as to avoid an exposed part of the interlayer insulating layer.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 17, 2020
    Assignee: TDK CORPORATION
    Inventors: Naoaki Fujii, Tomonaga Nishikawa, Kouji Kawamura, Nobuya Takahashi
  • Patent number: 10827613
    Abstract: A multilayer circuit board includes a laminate of insulating layers, conductive patterns each provided at an interlayer in the laminate, a via conductor extending through at least one of the insulating layers, and external terminals on a lower main surface of the laminate. A shield electrode layer connected to a ground potential is provided on at least one side surface of the laminate. At least one surrounding conductive pattern surrounding an element to be shielded is provided at an interlayer between corresponding ones of the insulating layers. Both ends of the surrounding conductive pattern are connected to the shield electrode layer.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 3, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shinya Matsushita
  • Patent number: 10818602
    Abstract: A electronic device includes an embedded ball land substrate and a semiconductor die. The embedded ball land substrate includes a top surface, a bottom surface opposite the top surface, and one or more side surfaces adjacent the top surface and the bottom surface. The embedded ball land substrate further includes a mold layer on the bottom surface, contact pads on the top surface, and ball lands embedded in the mold layer and electrically connected to the contact pads. The semiconductor die includes a first surface, a second surface opposite the first surface, one or more side surfaces adjacent the first surface and the second surface, and attachment structures along the second surface. The semiconductor die is operatively coupled to the contact pads via the attachment structures.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 27, 2020
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Corey Reichman, Ronald Huemoeller
  • Patent number: 10811350
    Abstract: A primary-side electrode and a secondary-side electrode of a power device are disposed so as to straddle plural separate primary and secondary wires in a first conductive layer, a second conductive layer includes plural separate primary and secondary wires, an insulating part is disposed in a first insulating layer in a region between the primary and secondary wires and directly below the power device, an intralayer insulating part is disposed in the second conductive layer in a region between the primary and secondary wires and directly below the power device, and a via that connects the primary wire in the first conductive layer and the primary wire in the second conductive layer and connects the secondary wire in the first conductive layer and the secondary wire in the second conductive layer is disposed in the first insulating layer directly below the primary-side and secondary-side electrodes of the power device.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 20, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroki Kanai, Tomotoshi Satoh, Kenichi Tanaka
  • Patent number: 10804633
    Abstract: An electrical contact point including: a first contact and a second contact capable of forming an electrical contact each other, wherein: the first contact includes an alloy containing layer having alloy parts made of an alloy containing tin and palladium and a tin part made of tin or an alloy having a higher ratio of tin to palladium than the alloy parts with both the alloy parts and the tin part exposed on an outermost surface; and the second contact includes a dissimilar metal layer made of metal having a higher hardness than the alloy containing layer and containing neither tin nor palladium on an outermost surface.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: October 13, 2020
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Akihiro Kato, Hajime Watanabe, Yoshiyasu Tsuchiya
  • Patent number: 10785865
    Abstract: A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
  • Patent number: 10779418
    Abstract: A manufacturing method of a double layer circuit board comprises forming a connecting pillar on a first circuit, wherein the connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the connecting pillar; drilling the substrate to expose a portion of the second end of the connecting pillar, wherein the other portion of the second end of the connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 15, 2020
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 10779407
    Abstract: A multilayer circuit board and a manufacturing method thereof are provided. The multilayer circuit board includes: a first board having a first conductive via hole; a first conductive layer formed on the first board and the first conductive via hole; a second board disposed on the first board and the first conductive layer and having a second conductive via hole; and a second conductive layer formed on the second board and the second conductive via hole. The first conductive layer and the second conductive layer contact with each other and cooperatively define a connecting part, and the connecting part of the first conductive layer and the second conductive layer includes concave-convex surfaces for engaging with each other.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 15, 2020
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Yi-Chun Chen, Chao-Chiang Liu
  • Patent number: 10743408
    Abstract: Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 11, 2020
    Assignee: Alcatel Lucent
    Inventors: James M. Schriel, Alex L. Chan, Paul J. Brown
  • Patent number: 10734282
    Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Harold Ryan Chase, Mihir K Roy, Mathew J Manusharow, Mark Hlad
  • Patent number: 10736209
    Abstract: A conductive transmission line structure includes a first conductive transmission line and a second conductive transmission line. A first segment and a second segment of the first conductive transmission line are respectively disposed adjacent to a third segment and a fourth segment of the second conductive transmission line. Line widths of the first segment and the third segment are respectively smaller than line widths of the second segment and the fourth segment. A spacing between the first segment and the third segment is smaller than a spacing between the second segment and the fourth segment. The first segment and the third segment provide a first impedance, and the second segment and the fourth segment provide a second impedance. The first impedance is smaller than the second impedance. The first and the third signal transmission nodes receive a differential signal pair.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 4, 2020
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Fan Yang, Yuan-Hung Lin, Yu-Cheng Sun
  • Patent number: 10726878
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Patent number: 10727190
    Abstract: A multilayer circuit board having a central conductor and core layers between a first set of alternating layers and a second set of alternating layers. The central conductor includes a first compound via through the first set of alternating layers, and a second compound via through the second set of alternating layers. A gap extends from a first side of the multilayer circuit board to a second side of the multilayer circuit board. A first array of ground protrusions surrounds the gap and is arranged in a first pattern on the first side of the multilayer circuit board. A second array of ground protrusions surrounds the gap and is arranged in a second pattern on the second side of the multilayer circuit board. A ground path connects the first array of ground protrusions to the second array of ground protrusions.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Tektronix, Inc.
    Inventor: George S. Curtis
  • Patent number: 10715111
    Abstract: An elastic wave filter device includes first and second reception filters, an input terminal, output terminals, and reference terminals provided on a piezoelectric substrate. The first reception filter includes series resonators and parallel resonators, and the second reception filter includes series resonators and parallel resonators. The reference terminal connected to the parallel resonator connected so as to be closest to the output terminal among the parallel resonators included in the first reception filter, and the reference terminal connected to the parallel resonator connected so as to be closest to the output terminal among the parallel resonators included in the second reception filter, are separated from each other on the piezoelectric substrate.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 14, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Motoki Ozasa
  • Patent number: 10707009
    Abstract: A thin film-type inductor includes a body including a support member having a through-hole filled with a magnetic material and a via hole, a coil disposed on at least one side of the support member and including a plurality of coil patterns, and a magnetic material sealing the support member and the coil. Each of the coil patterns includes a first conductor layer, a second conductor layer, and a third conductor layer. The second conductor layer is disposed on a side surface of the via hole, and is disposed to seal a lower surface of the via hole.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Joung Gul Ryu, Byeong Cheol Moon, Jin Hyuk Jang
  • Patent number: 10701800
    Abstract: An example method includes linking a transmit line and receive line to a respective via, and printing two paths to each via, wherein each path is interrupted by two pairs of contacts. When a first resistor is in a first pair of contacts at a receive via, first signal is formed between a receive point of a first connector and the receive line. When a first capacitor is in first pair of contacts at a transmit via, second signal is formed between transmit point of first connector and the transmit line. When a second resistor is in second pair of contacts at receive via, third signal is formed between receive point of a second connector and the receive line. When a second capacitor is in second pair of contacts at transmit via, fourth signal is formed between a transmit point of second connector and the transmit line.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vincent Nguyen, Sung Hsia Kuo, Ho M Lai
  • Patent number: 10692737
    Abstract: An electronics package includes a multilayer interconnect structure comprising insulating substrate layers and conductor layers. The electronics package also includes an electrical component comprising I/O pads electrically coupled to the conductor layers and conductive through vias extending through at least two insulating substrate layers and electrically connected to at least a portion of the I/O pads. The conductor layers include a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming direct electrical and physical connections with a conductive through via electrically connected to a ground I/O pad of the plurality of I/O pads. The conductor layers also include a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming direct electrical and physical connections with a conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: June 23, 2020
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kaustubh Ravindra Nagarkar
  • Patent number: 10693440
    Abstract: An acoustic wave device includes: a first substrate having a first surface on which an acoustic wave element is located; a second substrate having a second surface on which a functional element is located; a third substrate having a third surface, which faces the first and second surfaces, and a fourth surface being opposite to the third surface, a first metal layer separated from the acoustic wave element and a wiring line in the first substrate and connecting the first and third surfaces; a second metal layer separated from the functional element and a wiring line in the second substrate and connecting the second and third surfaces; a first metal pattern located on the third surface, being in contact with the first and second metal layers, and connecting the first and second metal layers; and a terminal located on the fourth surface and electrically connectable to the first metal pattern.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Satoru Ohkubo, Kazuyuki Imagawa, Ryo Miyamoto
  • Patent number: 10667390
    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 26, 2020
    Assignee: SANMINA CORPORATION
    Inventors: Shinichi Iketani, Dale Kersten, George Dudnikov, Jr.