Feedthrough Patents (Class 174/262)
  • Patent number: 11929195
    Abstract: A multilayer coil component includes a multilayer body that contain a coil. The coil includes coil conductors. A lamination direction of the multilayer body and an axial direction of the coil are parallel to a first main surface. A distance between the coil conductors adjacent to each other in the lamination direction is from 4 ?m to 8 ?m. Each coil conductor includes a line portion and a land portion that is disposed at an end portion of the line portion. The land portions of the coil conductors adjacent to each other in the lamination direction are connected to each other with a via conductor interposed therebetween. A width of the line portion is from 30 ?m to 50 ?m. An inner diameter of each coil conductor is from 50 ?m to 100 ?m.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: March 12, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Atsuo Hirukawa
  • Patent number: 11924967
    Abstract: According to one embodiment, a substrate includes a first dielectric substrate with a first through-hole, a second dielectric substrate with a first conductive via, a first signal line provided between the first dielectric substrate and the second dielectric substrate, a third dielectric substrate with a second conductive via, a first planar conductor provided between the second and third dielectric substrates and located away from the first and second conductive vias, a fourth dielectric substrate, and a second signal line provided between the third and fourth dielectric substrates. At least a part of a first inner wall of the first through-hole is not covered with a conductor. The first through-hole and the first conductive via partially overlap in a first direction. The first and second conductive vias partially overlap in the first direction. The second conductive via and the second signal line partially overlap in the first direction.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 5, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Makoto Sano
  • Patent number: 11924980
    Abstract: A method for manufacturing a multilayer substrate including first and second insulating resin base material layers including different materials, includes configuring a conductor film-attached insulating resin base material with a conductor film on the first insulating resin base material layer, or a second conductor film-attached insulating resin base material with a conductor film on a main surface of the first insulating resin base material layer including a main surface of a stacked body including at least the first insulating resin base material layer, and stacking the first or second conductor film-attached insulating resin base material and another base material layer such that the conductor film is in contact with the second insulating resin base material layer. An adhesion strength of the first insulating resin base material layer to the conductor film is higher than an adhesion strength of the second insulating resin base material layer to the conductor film.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: March 5, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yusuke Kamitsubo, Tomohiro Furumura
  • Patent number: 11917758
    Abstract: A substrate structure, a manufacturing method thereof, and an electronic device. The substrate structure includes a substrate, conductive wires and conductive members. Multiple through holes penetrate through the substrate body of the substrate. Multiple first conductive pads are arranged on the first surface of the substrate body. Multiple second conductive pads are arranged on the second surface of the substrate body. The conductive wires are accommodated in the through holes and each has a first end in the first opening of corresponding through hole and a second end in the second opening of corresponding through hole. The conductive members are distributed on the first and second surfaces, and both ends thereof are connected to the corresponding first and second conductive pads through the conductive members. At least part of each conductive wire does not contact the hole wall of each through hole in a direct manner.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: February 27, 2024
    Assignee: PANELSEMI CORPORATION
    Inventor: Ya-Che Hsueh
  • Patent number: 11910535
    Abstract: A printed circuit board stack structure includes a first printed circuit board, a second printed circuit board, and a filling glue layer. The first printed circuit board has at least one overflow groove, and includes first pads and a retaining wall surrounding the first pads. The second printed circuit board is disposed on the first printed circuit board, and includes second pads and conductive pillars located on some of the second pads. The conductive pillars are respectively connected to some of the first pads to electrically connect the second printed circuit board to the first printed circuit board. The filling glue layer fills between the first and the second printed circuit boards, and covers the first pads, the second pads, and the conductive pillars. The retaining wall blocks the filling glue layer so that a portion of the filling glue layer is accommodated in the overflow groove.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 20, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Hao Wu, Shih-Lian Cheng
  • Patent number: 11894626
    Abstract: A circuit apparatus includes: a stacked body; and a plurality of terminals. The stacked body includes a plurality of layers. A plurality of holes that extend through the plurality of layers are formed in the stacked body. Each of the plurality of layers includes a connection member that is formed of a conductor. The connection member includes: a plurality of connection portions that are provided at positions corresponding to the plurality of holes; and a joining portion that connects the plurality of connection portions to each other. The plurality of terminals include a plurality of types of terminals that correspond to the plurality of layers. Each of the plurality of types of terminals can be selectively connected to the connection portion of a corresponding one of the plurality of layers by being inserted into a predetermined one of the plurality of holes.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: February 6, 2024
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takamune Kikuta
  • Patent number: 11887547
    Abstract: A display device including a substrate including a display area and a non-display area, a plurality of signal lines disposed in the display area and extending along a first direction and from the non-display area to the display area, a connection line extending from the non-display area and electrically connected to a respective signal line of the plurality of signal lines in the non-display area, and an initialization voltage line extending in a second direction intersecting the first direction, wherein the connection line overlaps the initialization voltage line in a thickness direction of the display device.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Hwan Cho, Ki Nyeng Kang, Sang Hoon Lee, Sun Ho Kim, Tae Woo Kim, Tae Hoon Yang, Jong Hyun Choi
  • Patent number: 11882656
    Abstract: A wiring substrate includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, a connection conductor penetrating through the insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer and adhering the first conductor layer and the insulating layer. The first conductor layer includes a conductor pad in contact with the connection conductor such that the conductor pad has a surface having a first region and a second region on second conductor layer side and that surface roughness of the first region is different from surface roughness of the second region, and the conductor pad of the first conductor layer is formed such that the first region is covered by the coating film and that the second region is covered by the connection conductor.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 23, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Daisuke Minoura
  • Patent number: 11876026
    Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: January 16, 2024
    Assignee: Medtronic, Inc.
    Inventors: Chunho Kim, Mark E. Henschel
  • Patent number: 11871515
    Abstract: A wiring substrate includes an insulating layer having a through hole, a first conductor layer formed on a first surface of the insulating layer, a second conductor layer formed on a second surface of the insulating layer, an interlayer connection conductor formed in the through hole such that the interlayer connection conductor is connecting the first and second conductor layers, and a resin body formed in the through hole of the insulating layer such that a volume occupancy rate of the resin body is in a range of 30% to 55% in the through hole. The interlayer connection conductor is formed such that the interlayer connection conductor has a length in a range of 1000 ?m to 2000 ?m in a thickness direction of the insulating layer and that a volume occupancy rate of the interlayer connection conductor is in a range of 45% to 70% in the through hole.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 9, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Yasuki Kimishima, Satoru Kawai
  • Patent number: 11871510
    Abstract: A conductive pattern has been disclosed. The conductive pattern includes a pair of conductive traces. Each of the conductive traces comprises a linear portion and a terminal portion. The terminal portions are arranged adjacent to each other and comprises a pair of circular arc profile with a pair of complementary notches facing toward each other.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: January 9, 2024
    Assignee: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD.
    Inventors: Hou-Yuan Chou, Yi-Chih Wu, Feng-Hua Deng, Ming-Fang Chen
  • Patent number: 11864315
    Abstract: A vertical interconnection structure of a multi-layer substrate includes a first via pad disposed in a first layer of metal interconnect of the multi-layer substrate; a second via pad disposed in a second layer of metal interconnect of the multi-layer substrate; a signal via electrically connecting the first via pad to the second via pad; a non-circular first ground plane disposed in the first layer of metal interconnect of the multi-layer substrate and surrounding the first via pad; and a non-circular first ground pullback region between the first via pad and the non-circular first ground plane for electrically isolating the first via pad from the non-circular first ground plane.
    Type: Grant
    Filed: November 8, 2020
    Date of Patent: January 2, 2024
    Assignee: MEDIATEK INC.
    Inventor: Yi-Chieh Lin
  • Patent number: 11862596
    Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, a semiconductor chip on the redistribution substrate and including a chip pad electrically connected to the redistribution substrate, and a conductive terminal on the redistribution substrate. The redistribution substrate includes a first dielectric layer, a first redistribution pattern, a second dielectric layer, a second redistribution pattern, and a first insulative pattern. The first redistribution pattern electrically connects the chip pad and the second redistribution pattern. The first insulative pattern has a first surface in contact with the first redistribution pattern and a second surface in contact with the second redistribution pattern. The second surface is opposite to the first surface. A width at the first surface of the first insulative pattern is the same as or greater than a width at the second surface of the first insulative pattern.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Namhoon Kim, Seunghoon Yeon, Yonghoe Cho
  • Patent number: 11864327
    Abstract: An inductor structure is provided that is positioned within a via of a printed circuit board. The inductor structure includes a via extending through a printed circuit board. The inductor structure includes at least one coil of an electrically conductive material beginning at a first opening to the via continuously present on a sidewall of the via encircling a center of the via extending to a second opening of the via opposite the first opening of the via. It further includes at least electrode present in contact with an end of the coil at said first or second opening.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 2, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald Bartley, Darryl Becker, Matthew Doyle, Mark Jeanson
  • Patent number: 11862580
    Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11848224
    Abstract: An electrostatic chuck includes: a ceramic plate; an adsorption electrode that is built in the ceramic plate; and a plurality of connection pads that are built in the ceramic plate to be electrically connected to the adsorption electrode. The connection pads are arranged stepwise.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: December 19, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Naoyuki Koizumi, Kazunori Shimizu, Kentaro Kobayashi
  • Patent number: 11842893
    Abstract: A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and exposed through the cavity; wherein the second insulating layer includes a first portion disposed on an upper surface of the first insulating layer in a region where the cavity is formed; and a second portion other than the first portion, and wherein a thickness of the first portion is smaller than a thickness of the second portion.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 12, 2023
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Se Woong Na, Se Ho Myeong
  • Patent number: 11844174
    Abstract: An electronic board includes: a board including an upper surface ground on an upper surface; at least one first land formed on the upper surface and connected to a first signal line; at least one second land formed on the upper surface and connected to a second signal line; at least one third land disposed on the upper surface between the first land and the second land and connected to the upper surface ground; and at least one fourth land disposed on the upper surface on a side opposite to the third land and connected to the upper surface ground, the first land being interposed between the third land and the fourth land.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: December 12, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shinkuro Fujino, Tomokazu Deki, Hiroyuki Tahara, Takao Takeshita
  • Patent number: 11837832
    Abstract: A composite material structure that prevents occurrence of galvanic corrosion while exposing a part of a conductor embedded in a conductive resin portion as a connecting portion, is provided. The composite material structure includes a conductive resin portion formed of an electrically conductive reinforced resin in which conductive fibers are contained in a base material, a conductor formed of a conductive material and embedded in the conductive resin portion with a part of the conductor exposed as a connecting portion for electrical connection with another component, and an insulator that is formed of an insulating material and that is at least partially embedded in the conductive resin portion so as to be interposed between the conductive reinforced resin and the conductor so as to prevent the connecting portion of the conductor from contacting the conductive reinforced resin.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 5, 2023
    Assignee: YAZAKI CORPORATION
    Inventor: Terukazu Kosako
  • Patent number: 11832397
    Abstract: A printed wiring board includes a resin insulating layer, via conductors formed in the resin insulating layer, metal posts formed on the via conductors, respectively, and a solder resist layer formed on the resin insulating layer such that the metal posts have lower portions embedded in the solder resist layer and upper portions exposed from the solder resist layer, respectively. The metal posts are formed such that each of the metal posts has a top portion having a diameter in a range of 0.8 to 0.9 times a diameter of a respective one of the lower portions of the metal posts.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: November 28, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Masashi Awazu, Keisuke Kojima
  • Patent number: 11832384
    Abstract: A multilayer resin substrate includes a stacked body including first resin layers made of a thermoplastic resin, conductor patterns on the stacked body, and a protective layer including a second resin layer made of a thermosetting resin. The stacked body includes first and second main surfaces, and a bent portion. One of the conductor patterns located at the bent portion is located only inside the stacked body. The protective layer covers at least the bent portion, on the main surface of the stacked body.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: November 28, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takahiro Baba
  • Patent number: 11832399
    Abstract: An electronics module for a transmission control unit may including one or more of the following: a printed circuit board populated with electronic components that are attached to an upper surface and/or a lower surface of the printed circuit board, and electrically connected thereto, and a media-tight protective layer, which covers one or more electronic components and connecting points between the one or more electronic components and the printed circuit board, where there is a cooling element for cooling the electronic components on one side of the printed circuit board, where the cooling element is connected to the printed circuit board and houses the electronic components that are to be cooled, and where the media-tight protective layer covers a transition region between the printed circuit board and the cooling element along the entire periphery of the cooling element.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 28, 2023
    Assignee: ZF Friedrichshafen AG
    Inventors: Josef Loibl, Hermann Josef Robin
  • Patent number: 11824249
    Abstract: A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jun-De Jin
  • Patent number: 11823993
    Abstract: A wiring substrate includes a first insulation layer, a first through hole extending through the first insulation layer in a thickness-wise direction, a first via wiring formed in the first through hole, a second insulation layer formed on an upper surface of the first insulation layer, a first recess formed in a lower surface of the second insulation layer and connected to the first through hole, an opening formed in an upper surface of the second insulation layer and connected to the first recess, a second recess formed in an upper surface of the first via wiring and connected to the first recess, a second via wiring formed in the opening, the first recess, and the second recess, and a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: November 21, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD
    Inventor: Masataka Muroga
  • Patent number: 11817250
    Abstract: A broadside coupled coplanar inductor device includes first and second coplanar inductors in which the conductors of the first and second coplanar inductors are broadside coupled. The conductors are located one above the other at a first distance and the return paths are located to the side of the respective first and second conductor signal paths at a second distance. One or both of the dimensions of the first and second first distances is defined so as to maximize a mutual inductance between the conductors. First and second driver circuit apply voltages across each conductor. The input pulse width modulation signals applied to the first and second driver circuits are 180 degrees out of phase.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Todd E. Takken, Xin Zhang
  • Patent number: 11810844
    Abstract: A component carrier includes a glass core having a first main surface and a second main surface; a first electrically insulating layer structure applied on the first main surface of the glass core; a first electrically conductive layer structure applied on the first electrically insulating layer structure; and at least one inner hole extending through the glass core and the first electrically insulating layer structure.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 7, 2023
    Assignee: AT&S(Chongqing) Company Limited
    Inventor: Jeesoo Mok
  • Patent number: 11804383
    Abstract: A method for producing a metal-ceramic substrate with a plurality of electrically conductive vias includes: attaching a first metal layer in a planar manner to a first surface side of a ceramic layer; after attaching the first metal layer, introducing a copper hydroxide or copper acetate brine into a plurality of holes in the ceramic layer delimiting a via, to form an assembly; converting the copper hydroxide or copper acetate brine into copper oxide; subjecting the assembly to a high-temperature step above 500° C. in which the copper oxide forms a copper body in the plurality of holes; and after converting the copper hydroxide or copper acetate brine into the copper oxide, attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side. The copper body produces an electrically conductive connection between the first and the second metal layers.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: October 31, 2023
    Assignee: Infineon Technologies AG
    Inventor: Alexander Roth
  • Patent number: 11800636
    Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: October 24, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Snehamay Sinha, Tapobrata Bandyopadhyay, Markarand Ramkrishna Kulkarni
  • Patent number: 11798903
    Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: October 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Chintan Buch, Roman Gouk, Steven Verhaverbeke
  • Patent number: 11792918
    Abstract: A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.
    Type: Grant
    Filed: November 21, 2021
    Date of Patent: October 17, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Pei-Wei Wang, Heng-Ming Nien, Ching-Sheng Chen, Yi-Pin Lin, Shih-Liang Cheng
  • Patent number: 11784383
    Abstract: A transmission line includes first, second, and third signal lines defining a parallel portion. No conductor connecting the first ground conductor and the second ground conductor is between the first signal line and the second signal line, and the first signal line is closer to the ground connection conductor than the second signal line. A closest frequency difference between a fundamental wave of one of the first signal and the second signal and a fundamental wave or a higher harmonic wave of the other of the first signal and the second signal is equal to or larger than a closest frequency difference between a fundamental wave of one of the first signal and the third signal and a fundamental wave or a higher harmonic wave of the other of the first signal and the third signal.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tomohiro Nagai
  • Patent number: 11776848
    Abstract: A semiconductor device and related manufacturing methods are provided. The semiconductor device includes one interconnection structure including: a substrate; a first insulating dielectric layer underneath a lower surface of the substrate; a second insulating dielectric layer on an upper surface of the substrate; a first connecting pad disposed within the first insulating dielectric layer; a metal connection member penetrating through a portion of the second insulating dielectric layer, the substrate and a portion of the first insulating dielectric layer to connect the first connecting pad; and a second connecting pad disposed within the second insulating dielectric layer and connecting the metal connection member. The metal connection member may be a Through-Silicon Via (TSV). The device includes a confined air gap surrounding the metal connection member, which improves the performance and reliability of the device.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: October 3, 2023
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Chih-Wei Chang
  • Patent number: 11776899
    Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: October 3, 2023
    Assignee: MEDIATEK INC.
    Inventors: Che-Hung Kuo, Hsing-Chih Liu
  • Patent number: 11769739
    Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The semiconductor device is disposed on the redistribution circuit structure opposite to the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is partially embedded in the redistribution circuit structure and is partially embedded in the insulating encapsulation. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. The reinforcement structure is electrically floating.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
  • Patent number: 11763975
    Abstract: An inductor built-in substrate includes a core substrate having an opening, a magnetic resin body having a through hole and including a magnetic resin filled in the opening of the core substrate, and a plating film formed in the through hole of the magnetic resin body and including an electrolytic plating film such that the electrolytic plating film is formed in contact with the magnetic resin body.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 19, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroaki Kodama, Atsushi Ishida, Kazuro Nishiwaki
  • Patent number: 11765813
    Abstract: A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: September 19, 2023
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 11758644
    Abstract: A circuit board may include a traditional via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board and a slotted via formed within the circuit board proximate to the traditional via, the slotted via comprising an opening through a first surface and a second surface of the circuit board and a layer of conductive material formed on interior walls of the opening.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: September 12, 2023
    Assignee: Dell Products L.P.
    Inventors: Jason Pritchard, Charles W. Ziegler, IV, Qianwen Wang, Lingyu Kong
  • Patent number: 11756846
    Abstract: A glass core, a multilayer circuit board, and a method of manufacturing a glass core that appropriately form copper wiring, and suppresses crack and the like, a glass core includes: a glass plate; a first metal layer provided on the glass plate; a first electrolytic copper plating layer provided on the first metal layer; a dielectric layer provided above the first electrolytic copper plating layer; a second metal layer provided on the dielectric layer; an electroless nickel plating layer provided on the second metal layer and having a phosphorus content of less than 5 mass %; and a second electrolytic copper plating layer provided on the electroless nickel plating layer.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: September 12, 2023
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Tetsuyuki Tsuchida
  • Patent number: 11758648
    Abstract: A high-frequency board includes an insulating substrate, a first line conductor, a second line conductor, a capacitor, a first bond, and a second bond. The insulating substrate has a recess on its upper surface. The first line conductor extends from an edge of the recess on the upper surface of the insulating substrate. The second line conductor faces the first line conductor across the recess on the upper surface of the insulating substrate. The capacitor overlaps the recess. The first bond joins the capacitor to the first line conductor. The second bond joins the capacitor to the second line conductor, and is spaced from the first bond.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: September 12, 2023
    Assignee: KYOCERA Corporation
    Inventor: Yoshiki Kawazu
  • Patent number: 11758655
    Abstract: A printed circuit board includes a first insulating layer, a second insulating layer disposed on a lower surface of the first insulating layer, an electronic component embedded in the second insulating layer and at least partially in contact with the first insulating layer, a first wiring layer disposed on an upper surface of the first insulating layer, a second wiring layer disposed on a lower surface of the second insulating layer, and a first wiring via penetrating through the first and second insulating layers and connecting at least portions of the first and second wiring layers to each other.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: September 12, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Eun Lee, Jae Woong Choi, Joo Hwan Jung, Yong Hoon Kim, Jin Won Lee
  • Patent number: 11758642
    Abstract: In one embodiment, a grounding structure for a printed circuit board (PCB) of an information handling system includes: a first ground via electrically coupled to a ground layer of the PCB; a second ground via electrically coupled to the ground layer of the PCB; and a conductive strip electrically coupling the first ground via to the second ground via, the conductive strip providing a vertical ground reference for a signal transferred from a first surface of the PCB to a second surface of the PCB through a signal via disposed on the PCB.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: September 12, 2023
    Assignee: Dell Products L.P.
    Inventors: Fong-An Kan, Chian-Ting Chen, Po Hsiang Chuang
  • Patent number: 11751323
    Abstract: A printed circuit board (PCB) is provided for transmitting a differential signal. The PCB includes first and second conductive signal layers. The first conductive signal layer includes a first positive trace of the differential signal and a first negative trace of the differential signal. The second conductive signal layer includes a second positive trace of the differential signal and a second negative trace of the differential signal. The first positive trace is adjacent to the first negative trace, and the second positive trace is adjacent to the second negative trace and directly below the first negative trace.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: September 5, 2023
    Assignee: Dell Products L.P.
    Inventors: Sandor Farkas, Bhyrav Mutnury
  • Patent number: 11749596
    Abstract: A wiring substrate includes a conductor pad, an insulating layer formed on the conductor pad such that the insulating layer is covering the conductor pad and has a through hole, a bump formed on the conductor pad such that the bump is formed in the through hole penetrating through the insulating layer. The conductor pad is formed such that the conductor pad has a connecting surface connected to the bump, a concave part formed on the connecting surface of the conductor pad to the bump, and a convex part formed in the concave part.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: September 5, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Katsuyuki Sano, Yoji Sawada
  • Patent number: 11729912
    Abstract: A wiring substrate includes an insulating layer including inorganic fillers and resin, and a conductor layer formed on a surface of the insulating layer and having a conductor pattern. The surface of the insulating layer has an arithmetic average roughness Ra in the range of 0.05 ?m to 0.5 ?m, the conductor layer includes a metal film formed on the surface of the insulating layer, and the inorganic fillers include a first inorganic filler including particles such that each of the particles has a portion of a surface separated from the resin and forming a gap with respect to the resin of the insulating layer and that the metal film of the conductor layer includes part formed in the gap between the first inorganic filler and the resin.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: August 15, 2023
    Assignee: IBIDEN CO., LTD.
    Inventor: Kosuke Ikeda
  • Patent number: 11728258
    Abstract: A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Veronica Strong, Kristof Darmawikarta, Arnab Sarkar
  • Patent number: 11728243
    Abstract: A through electrode substrate includes a substrate having a through hole extending through between a first face and a second face, a diameter of the through hole not having a minimum value inside the through hole; and a conductor arranged inside the through hole, wherein the through hole has a shape having a value obtained by summing a first to an eighth inclination angle at a first to an eighth position, respectively, of an inner face of the through hole of 8.0° or more, each of the first to the eighth inclination angle is an angle of the inner face with respect to a center axis of the through hole, and the first to the eighth position correspond to positions at distances of 6.25%, 18.75%, 31.25%, 43.75%, 56.25%, 68.75%, 81.25%, and 93.75%, respectively, from the first face in a section from the first face to the second face.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 15, 2023
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventor: Satoru Kuramochi
  • Patent number: 11723150
    Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Patent number: 11721614
    Abstract: A System in Package, SiP semiconductor device includes a substrate of laser direct structuring, LDS, material. First and second semiconductor die are arranged at a first and a second leadframe structure at opposite surfaces of the substrate of LDS material. Package LDS material is molded onto the second surface of the substrate of LDS material. The first semiconductor die and the package LDS material lie on opposite sides of the substrate of LDS material. A set of electrical contact formations are at a surface of the package molding material opposite the substrate of LDS material. The leadframe structures include laser beam processed LDS material. The substrate of LDS material and the package LDS material include laser beam processed LDS material forming at least one electrically-conductive via providing at least a portion of an electrically-conductive line between the first semiconductor die and an electrical contact formation at the surface of the package molding material opposite the substrate.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 8, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Derai, Dario Vitello
  • Patent number: 11716814
    Abstract: A display panel includes a plastic substrate and a first inner lead bonding (ILB) electrode on the plastic substrate. The first ILB electrode includes a first bonding segment, a second bonding segment, and a first connection segment. The first bonding segment is extended in a first direction oblique to a vertical direction of the display panel. The first connection segment is configured to provide an electrical connection between the first bonding segment and the second bonding segment. The first ILB electrode is configured to be bonded to an integrated circuit chip using one of the first bonding segment or the second bonding segment.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: August 1, 2023
    Assignee: Synaptics Incorporated
    Inventors: Toshifumi Ogata, Atsushi Maruyama, Goro Sakamaki
  • Patent number: 11715806
    Abstract: A solar module and a method for fabricating a solar module comprising a plurality of rear contact solar cells are described. Rear contact solar cells (1) are provided with a large size of e.g. 156×156 mm2. Soldering pad arrangements (13, 15) applied on emitter contacts (5) and base contacts (7) are provided with one or more soldering pads (9, 11) arranged linearly. The soldering pad arrangements (13, 15) are arranged asymmetrically with respect to a longitudinal axis (17). Each solar cell (1) is then separated into first and second cell portions (19, 21) along a line (23) perpendicular to the longitudinal axis (17).
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 1, 2023
    Assignee: REC SOLAR PTE. LTD.
    Inventors: Philipp Johannes Rostan, Robert Wade, Noel G. Diesta, Shankar Gauri Sridhara, Anders Soreng