Feedthrough Patents (Class 174/262)
  • Patent number: 12016133
    Abstract: A circuit board and a method of manufacturing the same are provided. The method includes the following steps of providing a first conductive layer; providing an adhesive material and at least one conductive bump, in which the adhesive material is electrically conductive; adhering at least one conductive bump to a surface of the first conductive layer using the adhesive material; providing an insulation layer; disposing the insulation layer on the surface of the first conductive layer and at least one conductive bump; and disposing a second conductive layer on the insulation layer.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: June 18, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Hao Wu, Hsuan-Wei Chen
  • Patent number: 12016117
    Abstract: An extensible and contractible mounting board that includes an extensible and contractible substrate; an extensible and contractible wiring line on one main surface of the extensible and contractible substrate; an electronic component electrically connected to the extensible and contractible wiring line; and a resin portion in contact with the extensible and contractible wiring line and overlapping an end portion of a connection region between the extensible and contractible wiring line and the electronic component in a plan view of the extensible and contractible mounting board, the resin portion having a cutout portion that overlaps the extensible and contractible wiring line. A Young's modulus of the resin portion is higher than a Young's modulus of the extensible and contractible substrate.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: June 18, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takahito Tomoda
  • Patent number: 12004296
    Abstract: A printed circuit board includes: an insulating member; a first wiring layer disposed in the insulating member, and including first and second pattern layers spaced apart from each other based on a thickness direction of the printed circuit board; and a second wiring layer disposed in the insulating member, and spaced apart from the first pattern layer over the first pattern layer based on the thickness direction. Based on the thickness direction, an insulation distance between the first pattern layer and the second pattern layer is smaller than an insulation distance between the first pattern layer and the second wiring layer, and each of the first and second pattern layers is thinner than the second wiring layer.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: June 4, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Uk Lee, Chi Won Hwang, Eun Sun Kim, Yong Wan Ji, Young Hun You
  • Patent number: 11997799
    Abstract: The present application provides a method for manufacturing a printed circuit board and a printed circuit board. The method for manufacturing a printed circuit board includes: providing a core board, wherein the core board includes an insulating baseplate, and a first surface and/or a second surface opposite to the first surface of the insulating baseplate is provided with a plurality of pads; and laminating a medium layer on a side of the insulating baseplate provided with the plurality of pads to form a laminated layer at least partially embedded among the plurality of pads.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: May 28, 2024
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventor: Changsheng Tang
  • Patent number: 11990442
    Abstract: A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 21, 2024
    Assignee: STMicroelectron S.r.l.
    Inventors: Cristina Somma, Aurora Sanna, Damian Halicki
  • Patent number: 11991826
    Abstract: A flexible printed circuit board includes a power wiring layer transmitting power and a signal wiring layer insulated and stacked over or under the power wiring layer. The flexible printed circuit board may also include an upper wiring layer and a lower wiring layer insulated and stacked each other, and the power wiring layer and the signal wiring layer are provided between the upper wiring layer and the lower wiring layer.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: May 21, 2024
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Jongmin Kim, Dong Pil Park, Yoonho Huh
  • Patent number: 11984403
    Abstract: An integrated substrate structure includes a redistribution film, a circuit substrate, and a plurality of conductive features. The redistribution film includes a fine redistribution circuitry, a circuit substrate is disposed over the redistribution film and includes a core layer and a coarse redistribution circuitry disposed in and on the core layer. The circuit substrate is thicker and more rigid than the redistribution film, and a layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry. The conductive features are interposed between the circuit substrate and the redistribution film to be connected to the fine redistribution circuitry and the coarse redistribution circuitry. A redistribution structure and manufacturing methods are also provided.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: May 14, 2024
    Inventor: Dyi-Chung Hu
  • Patent number: 11973034
    Abstract: Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: April 30, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Eric J. Bergman, John L. Klocke, Marvin L. Bernt, Jing Xu, Kwan Wook Roh
  • Patent number: 11961794
    Abstract: An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 16, 2024
    Assignee: Amikor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Ji Young Chung
  • Patent number: 11961880
    Abstract: A semiconductor device includes first and second metal-insulator-metal structures. The first metal-insulator-metal structure includes a first bottom conductor plate, a first portion of a first dielectric layer, a first middle conductor plate, a first portion of a second dielectric layer, and a first top conductor plate stacked up one over another. The second metal-insulator-metal structure includes a second bottom conductor plate, a second portion of the first dielectric layer, a second middle conductor plate, a second portion of the second dielectric layer, and a second top conductor plate stacked up one over another. In a cross-sectional view, the first bottom conductor plate is wider than the first middle conductor plate that is wider than the first top conductor plate, and the second bottom conductor plate is narrower than the second middle conductor plate that is narrower than the first top conductor plate.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Tsung-Chieh Hsiao, Ying-Yao Lai, Dian-Hau Chen
  • Patent number: 11956904
    Abstract: The present invention provides a multilayer circuit board and a method for manufacturing the same for improving a bowing problem that occurs when manufacturing the multilayer circuit board. A multilayer circuit board according to the present invention is a board having a patterned layer that functions as a circuit a base layer, and includes: a second pattern layer formed on one side of the base layer; a first pattern layer formed on the second pattern layer; and an interlayer insulating layer formed between the first pattern layer and the second pattern layer, the interlayer insulating layer being partially formed on the second pattern layer so as to correspond to a region where the first pattern layer is formed.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: April 9, 2024
    Assignee: STEMCO CO., LTD.
    Inventors: Jae Soo Lee, Hyo Jin Park, Sung Jin Lee, Dong Gon Kim
  • Patent number: 11947765
    Abstract: According to a touch panel and a display panel provided in embodiments of the present application, a first connecting structure for connecting adjacent two first electrode units and a second connecting structure for connecting adjacent two second electrode units are improved. In this way, graphic design is performed on the second connecting structure and a wired manner of the first connecting structure is designed, so that an area of an intersection between the first connecting structure and the second connecting structure can be reduced, thereby reducing parasitic capacitance between the first connecting structure and the second connecting structure, and further improving or eliminating an impact of a bridging point of a touch electrode on touch linearity of a touch panel, to ensure better stability of the touch panel in use.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: April 2, 2024
    Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd.
    Inventor: Yichao Deng
  • Patent number: 11942406
    Abstract: A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than s second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Kyu Oh Lee, Dilan Seneviratne, Ravindranadh T Eluri
  • Patent number: 11929195
    Abstract: A multilayer coil component includes a multilayer body that contain a coil. The coil includes coil conductors. A lamination direction of the multilayer body and an axial direction of the coil are parallel to a first main surface. A distance between the coil conductors adjacent to each other in the lamination direction is from 4 ?m to 8 ?m. Each coil conductor includes a line portion and a land portion that is disposed at an end portion of the line portion. The land portions of the coil conductors adjacent to each other in the lamination direction are connected to each other with a via conductor interposed therebetween. A width of the line portion is from 30 ?m to 50 ?m. An inner diameter of each coil conductor is from 50 ?m to 100 ?m.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: March 12, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Atsuo Hirukawa
  • Patent number: 11924980
    Abstract: A method for manufacturing a multilayer substrate including first and second insulating resin base material layers including different materials, includes configuring a conductor film-attached insulating resin base material with a conductor film on the first insulating resin base material layer, or a second conductor film-attached insulating resin base material with a conductor film on a main surface of the first insulating resin base material layer including a main surface of a stacked body including at least the first insulating resin base material layer, and stacking the first or second conductor film-attached insulating resin base material and another base material layer such that the conductor film is in contact with the second insulating resin base material layer. An adhesion strength of the first insulating resin base material layer to the conductor film is higher than an adhesion strength of the second insulating resin base material layer to the conductor film.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: March 5, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yusuke Kamitsubo, Tomohiro Furumura
  • Patent number: 11924967
    Abstract: According to one embodiment, a substrate includes a first dielectric substrate with a first through-hole, a second dielectric substrate with a first conductive via, a first signal line provided between the first dielectric substrate and the second dielectric substrate, a third dielectric substrate with a second conductive via, a first planar conductor provided between the second and third dielectric substrates and located away from the first and second conductive vias, a fourth dielectric substrate, and a second signal line provided between the third and fourth dielectric substrates. At least a part of a first inner wall of the first through-hole is not covered with a conductor. The first through-hole and the first conductive via partially overlap in a first direction. The first and second conductive vias partially overlap in the first direction. The second conductive via and the second signal line partially overlap in the first direction.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 5, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Makoto Sano
  • Patent number: 11917758
    Abstract: A substrate structure, a manufacturing method thereof, and an electronic device. The substrate structure includes a substrate, conductive wires and conductive members. Multiple through holes penetrate through the substrate body of the substrate. Multiple first conductive pads are arranged on the first surface of the substrate body. Multiple second conductive pads are arranged on the second surface of the substrate body. The conductive wires are accommodated in the through holes and each has a first end in the first opening of corresponding through hole and a second end in the second opening of corresponding through hole. The conductive members are distributed on the first and second surfaces, and both ends thereof are connected to the corresponding first and second conductive pads through the conductive members. At least part of each conductive wire does not contact the hole wall of each through hole in a direct manner.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: February 27, 2024
    Assignee: PANELSEMI CORPORATION
    Inventor: Ya-Che Hsueh
  • Patent number: 11910535
    Abstract: A printed circuit board stack structure includes a first printed circuit board, a second printed circuit board, and a filling glue layer. The first printed circuit board has at least one overflow groove, and includes first pads and a retaining wall surrounding the first pads. The second printed circuit board is disposed on the first printed circuit board, and includes second pads and conductive pillars located on some of the second pads. The conductive pillars are respectively connected to some of the first pads to electrically connect the second printed circuit board to the first printed circuit board. The filling glue layer fills between the first and the second printed circuit boards, and covers the first pads, the second pads, and the conductive pillars. The retaining wall blocks the filling glue layer so that a portion of the filling glue layer is accommodated in the overflow groove.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 20, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Hao Wu, Shih-Lian Cheng
  • Patent number: 11894626
    Abstract: A circuit apparatus includes: a stacked body; and a plurality of terminals. The stacked body includes a plurality of layers. A plurality of holes that extend through the plurality of layers are formed in the stacked body. Each of the plurality of layers includes a connection member that is formed of a conductor. The connection member includes: a plurality of connection portions that are provided at positions corresponding to the plurality of holes; and a joining portion that connects the plurality of connection portions to each other. The plurality of terminals include a plurality of types of terminals that correspond to the plurality of layers. Each of the plurality of types of terminals can be selectively connected to the connection portion of a corresponding one of the plurality of layers by being inserted into a predetermined one of the plurality of holes.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: February 6, 2024
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takamune Kikuta
  • Patent number: 11887547
    Abstract: A display device including a substrate including a display area and a non-display area, a plurality of signal lines disposed in the display area and extending along a first direction and from the non-display area to the display area, a connection line extending from the non-display area and electrically connected to a respective signal line of the plurality of signal lines in the non-display area, and an initialization voltage line extending in a second direction intersecting the first direction, wherein the connection line overlaps the initialization voltage line in a thickness direction of the display device.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Hwan Cho, Ki Nyeng Kang, Sang Hoon Lee, Sun Ho Kim, Tae Woo Kim, Tae Hoon Yang, Jong Hyun Choi
  • Patent number: 11882656
    Abstract: A wiring substrate includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, a connection conductor penetrating through the insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer and adhering the first conductor layer and the insulating layer. The first conductor layer includes a conductor pad in contact with the connection conductor such that the conductor pad has a surface having a first region and a second region on second conductor layer side and that surface roughness of the first region is different from surface roughness of the second region, and the conductor pad of the first conductor layer is formed such that the first region is covered by the coating film and that the second region is covered by the connection conductor.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 23, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Daisuke Minoura
  • Patent number: 11876026
    Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: January 16, 2024
    Assignee: Medtronic, Inc.
    Inventors: Chunho Kim, Mark E. Henschel
  • Patent number: 11871515
    Abstract: A wiring substrate includes an insulating layer having a through hole, a first conductor layer formed on a first surface of the insulating layer, a second conductor layer formed on a second surface of the insulating layer, an interlayer connection conductor formed in the through hole such that the interlayer connection conductor is connecting the first and second conductor layers, and a resin body formed in the through hole of the insulating layer such that a volume occupancy rate of the resin body is in a range of 30% to 55% in the through hole. The interlayer connection conductor is formed such that the interlayer connection conductor has a length in a range of 1000 ?m to 2000 ?m in a thickness direction of the insulating layer and that a volume occupancy rate of the interlayer connection conductor is in a range of 45% to 70% in the through hole.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 9, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Yasuki Kimishima, Satoru Kawai
  • Patent number: 11871510
    Abstract: A conductive pattern has been disclosed. The conductive pattern includes a pair of conductive traces. Each of the conductive traces comprises a linear portion and a terminal portion. The terminal portions are arranged adjacent to each other and comprises a pair of circular arc profile with a pair of complementary notches facing toward each other.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: January 9, 2024
    Assignee: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD.
    Inventors: Hou-Yuan Chou, Yi-Chih Wu, Feng-Hua Deng, Ming-Fang Chen
  • Patent number: 11864315
    Abstract: A vertical interconnection structure of a multi-layer substrate includes a first via pad disposed in a first layer of metal interconnect of the multi-layer substrate; a second via pad disposed in a second layer of metal interconnect of the multi-layer substrate; a signal via electrically connecting the first via pad to the second via pad; a non-circular first ground plane disposed in the first layer of metal interconnect of the multi-layer substrate and surrounding the first via pad; and a non-circular first ground pullback region between the first via pad and the non-circular first ground plane for electrically isolating the first via pad from the non-circular first ground plane.
    Type: Grant
    Filed: November 8, 2020
    Date of Patent: January 2, 2024
    Assignee: MEDIATEK INC.
    Inventor: Yi-Chieh Lin
  • Patent number: 11862596
    Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, a semiconductor chip on the redistribution substrate and including a chip pad electrically connected to the redistribution substrate, and a conductive terminal on the redistribution substrate. The redistribution substrate includes a first dielectric layer, a first redistribution pattern, a second dielectric layer, a second redistribution pattern, and a first insulative pattern. The first redistribution pattern electrically connects the chip pad and the second redistribution pattern. The first insulative pattern has a first surface in contact with the first redistribution pattern and a second surface in contact with the second redistribution pattern. The second surface is opposite to the first surface. A width at the first surface of the first insulative pattern is the same as or greater than a width at the second surface of the first insulative pattern.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Namhoon Kim, Seunghoon Yeon, Yonghoe Cho
  • Patent number: 11864327
    Abstract: An inductor structure is provided that is positioned within a via of a printed circuit board. The inductor structure includes a via extending through a printed circuit board. The inductor structure includes at least one coil of an electrically conductive material beginning at a first opening to the via continuously present on a sidewall of the via encircling a center of the via extending to a second opening of the via opposite the first opening of the via. It further includes at least electrode present in contact with an end of the coil at said first or second opening.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 2, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald Bartley, Darryl Becker, Matthew Doyle, Mark Jeanson
  • Patent number: 11862580
    Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11848224
    Abstract: An electrostatic chuck includes: a ceramic plate; an adsorption electrode that is built in the ceramic plate; and a plurality of connection pads that are built in the ceramic plate to be electrically connected to the adsorption electrode. The connection pads are arranged stepwise.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: December 19, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Naoyuki Koizumi, Kazunori Shimizu, Kentaro Kobayashi
  • Patent number: 11842893
    Abstract: A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and exposed through the cavity; wherein the second insulating layer includes a first portion disposed on an upper surface of the first insulating layer in a region where the cavity is formed; and a second portion other than the first portion, and wherein a thickness of the first portion is smaller than a thickness of the second portion.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 12, 2023
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Se Woong Na, Se Ho Myeong
  • Patent number: 11844174
    Abstract: An electronic board includes: a board including an upper surface ground on an upper surface; at least one first land formed on the upper surface and connected to a first signal line; at least one second land formed on the upper surface and connected to a second signal line; at least one third land disposed on the upper surface between the first land and the second land and connected to the upper surface ground; and at least one fourth land disposed on the upper surface on a side opposite to the third land and connected to the upper surface ground, the first land being interposed between the third land and the fourth land.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: December 12, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shinkuro Fujino, Tomokazu Deki, Hiroyuki Tahara, Takao Takeshita
  • Patent number: 11837832
    Abstract: A composite material structure that prevents occurrence of galvanic corrosion while exposing a part of a conductor embedded in a conductive resin portion as a connecting portion, is provided. The composite material structure includes a conductive resin portion formed of an electrically conductive reinforced resin in which conductive fibers are contained in a base material, a conductor formed of a conductive material and embedded in the conductive resin portion with a part of the conductor exposed as a connecting portion for electrical connection with another component, and an insulator that is formed of an insulating material and that is at least partially embedded in the conductive resin portion so as to be interposed between the conductive reinforced resin and the conductor so as to prevent the connecting portion of the conductor from contacting the conductive reinforced resin.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 5, 2023
    Assignee: YAZAKI CORPORATION
    Inventor: Terukazu Kosako
  • Patent number: 11832397
    Abstract: A printed wiring board includes a resin insulating layer, via conductors formed in the resin insulating layer, metal posts formed on the via conductors, respectively, and a solder resist layer formed on the resin insulating layer such that the metal posts have lower portions embedded in the solder resist layer and upper portions exposed from the solder resist layer, respectively. The metal posts are formed such that each of the metal posts has a top portion having a diameter in a range of 0.8 to 0.9 times a diameter of a respective one of the lower portions of the metal posts.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: November 28, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Masashi Awazu, Keisuke Kojima
  • Patent number: 11832384
    Abstract: A multilayer resin substrate includes a stacked body including first resin layers made of a thermoplastic resin, conductor patterns on the stacked body, and a protective layer including a second resin layer made of a thermosetting resin. The stacked body includes first and second main surfaces, and a bent portion. One of the conductor patterns located at the bent portion is located only inside the stacked body. The protective layer covers at least the bent portion, on the main surface of the stacked body.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: November 28, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takahiro Baba
  • Patent number: 11832399
    Abstract: An electronics module for a transmission control unit may including one or more of the following: a printed circuit board populated with electronic components that are attached to an upper surface and/or a lower surface of the printed circuit board, and electrically connected thereto, and a media-tight protective layer, which covers one or more electronic components and connecting points between the one or more electronic components and the printed circuit board, where there is a cooling element for cooling the electronic components on one side of the printed circuit board, where the cooling element is connected to the printed circuit board and houses the electronic components that are to be cooled, and where the media-tight protective layer covers a transition region between the printed circuit board and the cooling element along the entire periphery of the cooling element.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 28, 2023
    Assignee: ZF Friedrichshafen AG
    Inventors: Josef Loibl, Hermann Josef Robin
  • Patent number: 11824249
    Abstract: A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jun-De Jin
  • Patent number: 11823993
    Abstract: A wiring substrate includes a first insulation layer, a first through hole extending through the first insulation layer in a thickness-wise direction, a first via wiring formed in the first through hole, a second insulation layer formed on an upper surface of the first insulation layer, a first recess formed in a lower surface of the second insulation layer and connected to the first through hole, an opening formed in an upper surface of the second insulation layer and connected to the first recess, a second recess formed in an upper surface of the first via wiring and connected to the first recess, a second via wiring formed in the opening, the first recess, and the second recess, and a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: November 21, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD
    Inventor: Masataka Muroga
  • Patent number: 11817250
    Abstract: A broadside coupled coplanar inductor device includes first and second coplanar inductors in which the conductors of the first and second coplanar inductors are broadside coupled. The conductors are located one above the other at a first distance and the return paths are located to the side of the respective first and second conductor signal paths at a second distance. One or both of the dimensions of the first and second first distances is defined so as to maximize a mutual inductance between the conductors. First and second driver circuit apply voltages across each conductor. The input pulse width modulation signals applied to the first and second driver circuits are 180 degrees out of phase.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Todd E. Takken, Xin Zhang
  • Patent number: 11810844
    Abstract: A component carrier includes a glass core having a first main surface and a second main surface; a first electrically insulating layer structure applied on the first main surface of the glass core; a first electrically conductive layer structure applied on the first electrically insulating layer structure; and at least one inner hole extending through the glass core and the first electrically insulating layer structure.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 7, 2023
    Assignee: AT&S(Chongqing) Company Limited
    Inventor: Jeesoo Mok
  • Patent number: 11804383
    Abstract: A method for producing a metal-ceramic substrate with a plurality of electrically conductive vias includes: attaching a first metal layer in a planar manner to a first surface side of a ceramic layer; after attaching the first metal layer, introducing a copper hydroxide or copper acetate brine into a plurality of holes in the ceramic layer delimiting a via, to form an assembly; converting the copper hydroxide or copper acetate brine into copper oxide; subjecting the assembly to a high-temperature step above 500° C. in which the copper oxide forms a copper body in the plurality of holes; and after converting the copper hydroxide or copper acetate brine into the copper oxide, attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side. The copper body produces an electrically conductive connection between the first and the second metal layers.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: October 31, 2023
    Assignee: Infineon Technologies AG
    Inventor: Alexander Roth
  • Patent number: 11800636
    Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: October 24, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Snehamay Sinha, Tapobrata Bandyopadhyay, Markarand Ramkrishna Kulkarni
  • Patent number: 11798903
    Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: October 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Chintan Buch, Roman Gouk, Steven Verhaverbeke
  • Patent number: 11792918
    Abstract: A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.
    Type: Grant
    Filed: November 21, 2021
    Date of Patent: October 17, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Pei-Wei Wang, Heng-Ming Nien, Ching-Sheng Chen, Yi-Pin Lin, Shih-Liang Cheng
  • Patent number: 11784383
    Abstract: A transmission line includes first, second, and third signal lines defining a parallel portion. No conductor connecting the first ground conductor and the second ground conductor is between the first signal line and the second signal line, and the first signal line is closer to the ground connection conductor than the second signal line. A closest frequency difference between a fundamental wave of one of the first signal and the second signal and a fundamental wave or a higher harmonic wave of the other of the first signal and the second signal is equal to or larger than a closest frequency difference between a fundamental wave of one of the first signal and the third signal and a fundamental wave or a higher harmonic wave of the other of the first signal and the third signal.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tomohiro Nagai
  • Patent number: 11776848
    Abstract: A semiconductor device and related manufacturing methods are provided. The semiconductor device includes one interconnection structure including: a substrate; a first insulating dielectric layer underneath a lower surface of the substrate; a second insulating dielectric layer on an upper surface of the substrate; a first connecting pad disposed within the first insulating dielectric layer; a metal connection member penetrating through a portion of the second insulating dielectric layer, the substrate and a portion of the first insulating dielectric layer to connect the first connecting pad; and a second connecting pad disposed within the second insulating dielectric layer and connecting the metal connection member. The metal connection member may be a Through-Silicon Via (TSV). The device includes a confined air gap surrounding the metal connection member, which improves the performance and reliability of the device.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: October 3, 2023
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Chih-Wei Chang
  • Patent number: 11776899
    Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: October 3, 2023
    Assignee: MEDIATEK INC.
    Inventors: Che-Hung Kuo, Hsing-Chih Liu
  • Patent number: 11769739
    Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The semiconductor device is disposed on the redistribution circuit structure opposite to the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is partially embedded in the redistribution circuit structure and is partially embedded in the insulating encapsulation. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. The reinforcement structure is electrically floating.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
  • Patent number: 11763975
    Abstract: An inductor built-in substrate includes a core substrate having an opening, a magnetic resin body having a through hole and including a magnetic resin filled in the opening of the core substrate, and a plating film formed in the through hole of the magnetic resin body and including an electrolytic plating film such that the electrolytic plating film is formed in contact with the magnetic resin body.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 19, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroaki Kodama, Atsushi Ishida, Kazuro Nishiwaki
  • Patent number: 11765813
    Abstract: A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: September 19, 2023
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 11758644
    Abstract: A circuit board may include a traditional via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board and a slotted via formed within the circuit board proximate to the traditional via, the slotted via comprising an opening through a first surface and a second surface of the circuit board and a layer of conductive material formed on interior walls of the opening.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: September 12, 2023
    Assignee: Dell Products L.P.
    Inventors: Jason Pritchard, Charles W. Ziegler, IV, Qianwen Wang, Lingyu Kong