Feedthrough Patents (Class 174/262)
  • Patent number: 10375828
    Abstract: A printed wiring board includes: a core substrate having a core layer and first and second conductor layers; a first build-up layer including a first insulating layer, an inner first conductor layer, an outermost first insulating layer, and an outermost first conductor layer; and a second build-up layer including a second insulating layer, an inner second conductor layer, an outermost second insulating layer, and an outermost second conductor layer. Each conductor layer includes metal foil, seed layer, and electrolytic plating film, t1/T1, t2/T2, u1/U1 and u2/U2 are smaller than 1, and s1/S1 and s2/S2 are larger than 1, where t1, t2, u1, u2, s1 and s2 are electrolytic plating film thicknesses of the first and second and outermost and inner first and second conductor layers, T1, T2, U1, U2, S1 and S2 are metal foil thicknesses of the first and second and outermost and inner first and second conductor layers.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 6, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Toshihide Makino, Hidetoshi Noguchi
  • Patent number: 10375838
    Abstract: A printed circuit board, and a method of fabricating the printed circuit board is disclosed. The printed circuit board includes at least one coaxial via. A hollow via is disposed in the printed circuit board. A metal sleeve is formed around the circumference of said hollow via. An inner conductive path is disposed in the hollow via. Additionally, an insulating material is disposed in the hollow via, between the conducting path and the metal sleeve. The conductive path is used to connect signal traces disposed on two different layers of the printed circuit board. In some embodiments, these signal traces carry signals having a frequency above 1 GHz, although the disclosure is not limited to this embodiment.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: August 6, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Glenn A. Brigham, Richard J. Stanley, Bradley Thomas Perry, Patrick J. Bell
  • Patent number: 10375822
    Abstract: Various circuit boards and systems are disclosed. In one aspect a system includes a circuit board and n differential signal via pairs. Each of the n differential signal via pairs has a first signal via and a second signal via and an electrical wall between the first signal via and the second signal via. There is a midline between every two adjacent differential via pairs. There are n ground return path vias. Each of the n ground return path vias is positioned substantially along one of the midlines and not on one of the electrical walls.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 6, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yuan Li, James R. Foppiano, Jonathan P. Dowling, Gerald J. Merits, Manjunath Shivappa, Wasim I. Ullah, Claude Hilbert
  • Patent number: 10374386
    Abstract: A chip may include a first substantially planar isolation layer with a first surface and a second surface opposite the first surface. The chip may include a first substantially planar conduction layer with a first surface positioned adjacent to the second surface of the first isolation layer and a second surface opposite the first surface. The chip may include a second substantially planar isolation layer with a first surface positioned adjacent to the second surface of the first conduction layer and a second surface opposite the first surface. The chip may include a second conduction layer etched on the second surface of the second isolation layer. The second conduction layer may include an anode trace, a cathode trace, and an optical transmitter positioned on the cathode trace. The chip may include one or more vias through the second isolation layer electrically coupling the anode trace with the first conduction layer.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 6, 2019
    Assignee: FINISAR CORPORATION
    Inventors: Jianwei Mu, Frank Lei Ding, Tao Wu, Hongyu Deng, Maziar Amirkiai
  • Patent number: 10362672
    Abstract: A resin multilayer substrate includes a laminate including a plurality of resin layers and an interlayer connecting conductor which extends through at least one of the plurality of resin layers and is directly exposed to an outside of the laminate.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: July 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Daisuke Tsuruga
  • Patent number: 10356897
    Abstract: A first land and a first ground pattern generate a first parasitic capacitance CLAND by capacitive coupling with a first insulating layer interposed therebetween. Then, the first parasitic capacitance CLAND is defined as a predetermined capacitance that suppresses an impedance of a via part from changing due to a change in an inductance component of the via part with respect to a first transmission line. As a result, it is possible to match the impedance of the via part with a impedance of the first transmission line by adjusting the first parasitic capacitance CLAND caused by the first land and the first ground pattern. Therefore, it is possible to prevent the transmission characteristics of the multilayer substrate from deteriorating without requiring the disposition of cavities such as through holes in the multilayer substrate.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 16, 2019
    Assignee: DENSO CORPORATION
    Inventors: Kiyokazu Akiyama, Yasunari Yanagiba
  • Patent number: 10340214
    Abstract: A carrier base material-added wiring substrate includes a wiring substrate and a carrier base material. The wiring substrate includes an insulation layer, a wiring layer arranged on a lower surface of the insulation layer, and a solder resist layer that covers the lower surface of the insulation layer and includes an opening that exposes a portion of the wiring layer as an external connection terminal. The carrier base material is adhered by an adhesive layer to the solder resist layer. The carrier base material includes an opening that is in communication with the opening of the solder resist layer and exposes the external connection terminal. The opening of the carrier base material has a diameter that is smaller than that of the opening of the solder resist layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 2, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Junji Sato, Hitoshi Kondo, Katsuya Fukase
  • Patent number: 10340182
    Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 2, 2019
    Assignee: International Business Machines corporation
    Inventors: James P. Doyle, Geraud Dubois, Nicholas C. Fuller, Teddie P. Magbitang, Robert D. Miller, Sampath Purushothaman, Willi Volksen
  • Patent number: 10334719
    Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 25, 2019
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Patent number: 10332903
    Abstract: A method for manufacturing a multi-layer structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a substrate, and the stack includes a multi-layer area and a contact area adjacent to the multi-layer area. Next, a plurality of first openings are formed in the contact area. Then, a conductive connecting structure is formed on the stack and into the first openings. Thereafter, the stack is patterned. The conductive connecting structure continuously extends on the contact area and into the first openings to maintain an electrical connection among the conductive layers while the stack is patterned.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: June 25, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10334740
    Abstract: An electronic-component mount substrate includes a substrate having a first principal surface and a second principal surface opposite to the first principal surface; a mount electrode for mounting an electronic component on the first principal surface, the mount electrode having a first slit and sandwiching the first slit; a plane electrode surrounding the mount electrode in a plan view and having a second slit; a connection electrode connecting the mount electrode with the plane electrode; and an outer electrode on the second principal surface. The connection electrode overlaps the outer electrode and an outer edge of the outer electrode surrounds the connection electrode in a perspective plan view.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 25, 2019
    Assignee: Kyocera Corporation
    Inventor: Kensaku Murakami
  • Patent number: 10327340
    Abstract: A method for producing circuit board, including: adhering plastic deformable insulating material onto surface of laminate, which contains second-metal-layer of second metal, and first-metal-layer in pattern on second-metal-layer, and the surface of the laminate is surface of second-metal-layer where first-metal-layer is formed, and surface of first-metal-layer, followed by curing the material, and removing second-metal-layer to form plate structure to which first-metal-layer in pattern is formed; opening hole in cured material from surface of the plate structure opposite to surface thereof where first-metal-layer is formed, until the hole reaches first-metal-layer; filling the hole with electroconductive paste, to form the plate structure filled therewith; and laminating one plate structure filled therewith with the other plate structure filled therewith in manner that first-metal-layer of one plate structure filled therewith faces opening of the hole of other plate structure filled therewith, wherein first-m
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: June 18, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kenji Iida, Takashi Nakagawa, Seigo Yamawaki, Yasuhiro Karahashi, Junichi Kanai, Koji Komemura
  • Patent number: 10303838
    Abstract: Dynamic electronic printed circuit board (PCB) design is provided. A test net on a PCB is dynamically created utilizing a first rule defining a net parameter and a second rule defining a padstack geometric parameter. A first evaluation of one or more nets having a first padstack is performed against the first rule. A second evaluation of both the first padstack and a reference padstack determined to be adjacently positioned to the first padstack is performed against the second rule. Based on the evaluations, a potential test net having a potential test padstack is dynamically selected from the evaluated nets. The selected potential test net is dynamically transformed into the test net. The dynamic transformation includes modifying the potential test padstack and/or the reference padstack utilizing the second rule. The dynamic creation of the test net improves the efficiency of electronic PCB design by mitigating time and footprint consumption.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Christo, David L. Green, Julio A. Maldonado, Diana D. Zurovetz
  • Patent number: 10285269
    Abstract: A multilayer substrate is manufactured by first manufacturing a first substrate by stacking and hot-pressing resin base materials of the first substrate and then adjacently stacking and hot-pressing the first substrate and resin base materials that constitute a second substrate at a position overlapping with each other in a stacking direction. The position in the stacking direction between the resin base materials in the first substrate is located at almost a middle position in the stacking direction of a resin base material of the second substrate, and is different from the position between the layers of the resin base materials of the second substrate.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: May 7, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kuniaki Yosui
  • Patent number: 10285260
    Abstract: The flexible printed circuit board includes a base layer, a first circuit layer and a second circuit layer, the first circuit and the second circuit layer formed on both sides of the base layer; conducting holes extending through the base layer and the first copper layer, the conducting holes include annular copper ring embedded in the first circuit layer. A height difference between a surface of the annular copper ring and a surface of the first circuit layer is in a range from 0 to 3 micrometers. A method for manufacturing the flexible printed circuit board is also provided.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 7, 2019
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Xian-Qin Hu, Yan-Lu Li, Li-Bo Zhang
  • Patent number: 10276909
    Abstract: A structure can include a first element and a carrier bonded to the first element along an interface. A waveguide can be defined at least in part along the interface between the first element and the carrier. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel, as viewed from a side cross-section of the structure. Various millimeter-wave or sub-terahertz components or circuit structures can also be created based on the waveguide structures disclosed herein.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 30, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Javier A. DeLaCruz, Belgacem Haba
  • Patent number: 10263352
    Abstract: An electrical contact pad for electrically contacting a connector includes a first region having a first length in a longitudinal direction, and a second region having a second length in the longitudinal direction that is greater than the first length. The first region is arranged to contact a first arm of the connector and the second region is arranged to contact a second arm of the connector. The first length being smaller than the second length results in a beneficial increases the impedance of the electrical contact pad. A chamfered edge of the contact pad results in an additional beneficial increase in the impedance of the electrical contact pad.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 16, 2019
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Graham Harry Smith, Jr., Scott Eric Walton, Michael Frank Cina
  • Patent number: 10242972
    Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: March 26, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen, Guang-Hwa Ma, Cheng-Hsu Hsiao
  • Patent number: 10234975
    Abstract: A flexible display device, a flexible display device fabrication method and an electronic device are provided. The flexible display device comprises a flexible display panel having a first surface for displaying images; a flexible insulating layer disposed on the first surface of the flexible display panel and divided into a plurality of flexible insulating blocks; and a touch control unit disposed on the flexible insulating layer and comprising a first touch control electrode layer in direct contact with the flexible insulating layer. The first touch control electrode layer includes a plurality of first touch control electrodes. Any one of the plurality of flexible insulating blocks corresponds to at least one of the plurality of first touch control electrodes. In a direction perpendicular to the flexible display panel, a gap between any two adjacent flexible insulating blocks overlaps with a gap between two adjacent first touch control electrodes.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 19, 2019
    Assignee: Shanghai Tianma Micro-Electronics Co., Ltd.
    Inventor: Yingteng Zhai
  • Patent number: 10231325
    Abstract: In some examples, an electronic device includes a printed circuit board (PCB) device that includes a first trace electrically connected to a first pad of a first trace via on a first layer and a second trace electrically connected to a second pad of a second trace via on a second layer. In some examples, the PCB device also includes four ground pads on the first layer and an antipad surrounding the two trace vias, where a first ground pad is positioned between the first trace and the second trace, where the first ground pad and the second ground pad are approximately symmetrically positioned about a perpendicular bisector of a line from the first pad to the second pad, and wherein the third ground pad and the fourth ground pad are approximately symmetrically positioned about the perpendicular bisector of the line from the first pad to the second pad.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: March 12, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: David P. Chengson, Edward C. Chang, Ranjeeth Doppalapudi, Santosh Kumar Pappu
  • Patent number: 10231327
    Abstract: There is provided an optical module including an optical subassembly including an optical element, a printed circuit board, and a connection substrate. The connection substrate includes a first connection portion connected to a first signal line conductor strip disposed on a first surface and a first ground conductor layer disposed on a second surface. The first connection portion includes a first signal line pad portion, a first ground pad portion, both disposed on the first surface, a second signal line pad portion disposed, and a second ground pad portion, both disposed on the second surface. In the connection substrate, a distance between the first signal line pad portion and the first ground pad portion in a first region is narrower than that in a second region farther from an inner end portion on the gap portion side than the first region in plan view.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: March 12, 2019
    Assignee: Oclaro Japan, Inc.
    Inventor: Daisuke Murakami
  • Patent number: 10217557
    Abstract: One object is to provide a laminated inductor having a reduced thickness without reduction in the magnetic characteristic and the insulation quality. The laminated inductor includes a first magnetic layer, an internal conductor, second magnetic layers, third magnetic layers, and a pair of external electrodes. The first magnetic layer includes three or more magnetic alloy particles arranged in the thickness direction and an oxide film binding the magnetic alloy particles together and containing Cr. The three or more magnetic alloy particles have an average particle diameter of 4 ?m or smaller. The internal conductor includes a plurality of conductive patterned portions electrically connected to each other via the first magnetic layer. The second magnetic layers are composed of magnetic alloy particles and disposed around the conductive patterned portions. The third magnetic layers are composed of magnetic alloy particles and disposed so as to be opposed to each other in thickness direction.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: February 26, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Takayuki Arai, Ryuichi Kondou, Akiko Yamaguchi, Shinsuke Takeoka, Kazuhiko Oyama, Kenji Otake
  • Patent number: 10219387
    Abstract: A process for manufacturing a printed circuit board having high-density microvias formed in a thick substrate is disclosed. The method includes the steps of forming one or more holes in a thick substrate using a laser drilling technique, electroplating the one or more holes with a conductive material, wherein the conductive material does not completely fill the one or more holes, and filling the one or more plated holes with a non-conductive material.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 26, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Leilei Zhang, Ronilo V. Boja, Abraham Fong Yee, Zuhair Bokharey
  • Patent number: 10211119
    Abstract: An electronic component built-in substrate includes an insulating base material having a first surface and a second surface opposite to the first surface, an electronic component embedded in the insulating base material and having an electrode on a side surface thereof, a first wiring layer embedded in an area outside the electrode of the electronic component in the insulating base material with a surface of the first wiring layer being exposed from the first surface of the insulating base material, a via conductor reaching from the second surface of the insulating base material to a side surface of the electrode of the electronic component and the first wiring layer, and a second wiring layer formed on the second surface of the insulating base material and connected to the via conductor.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 19, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yasuhiko Kusama, Hironobu Hashimoto, Takeshi Chino, Kazuhiro Kobayashi
  • Patent number: 10212807
    Abstract: A circuit board and package assembly electrically connecting a die to a circuit board. The circuit board has signal paths terminating in a signal pad located on an insulating layer. The circuit board also includes a ground pad on the insulating layer that has a concave shaped side forming a recess, the with a signal pad at least partially within the recess. A package has package ground pads aligned with the circuit board ground pads and package signal pads aligned with circuit board signal pads. The package ground pads extend through the package to connect to package ground paths, which extend toward the die. The package signal pads extend through the package to connect to package signal paths and the package signal paths extend toward the die, maintaining a consistent distance from the package ground paths. Multiple-tier bond wires connect the package bond locations to the die bond pads.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 19, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Alfredo Moncayo
  • Patent number: 10206281
    Abstract: A multilayer substrate includes plural layers of circuit patterns. Each circuit pattern includes a ground conductor surrounding a wiring region provided with a conductive wiring pattern. Each ground conductor includes a slit connecting between the outside of the multilayer substrate and the wiring region. In the multilayer substrate, the slit of the ground conductor provided at one of adjacent two layers of the circuit patterns and the slit of the ground conductor provided at the other circuit pattern are formed at positions not overlapping with each other. That is, these slits are formed at such positions that a view in an upper-to-lower direction is blocked. The shape of the slit of each ground conductor is in such a shape that a view from an end side of the multilayer substrate to a wiring region side is blocked.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 12, 2019
    Assignee: Onkyo Corporation
    Inventor: Makoto Yoshida
  • Patent number: 10201098
    Abstract: The embodiments herein relate to an apparatus and medium for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The apparatus and medium implement a step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 5, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Stig Kallman, Tomas Bergsten
  • Patent number: 10199337
    Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Hyun Park, Han Kim, Kang Heon Hur, Young Gwan Ko, Jung Ho Shim
  • Patent number: 10201109
    Abstract: The present invention provides an apparatus and/or method for modular, scalable and nestable parallel data processing and process control systems from molecular to module/enclosure level, comprised of calculable inter- and intra-modular processing time standards and shorter look-ahead propagation paths; based on regular and irregular hexagonal and dodecagonal prisms, derivative dumbbells and variants as actual and/or approximated tilings/tessellations which may be arranged in columns, rows, stacks and arrays with or without rounding and/or a sliding fit. Non-sliding fit systems are fundamentally solid. Sliding fit systems modules have a central cavity with systems as follows: cage assembly, optional patch panels, anchoring, thermal management, interconnect enclosures, power, hot swap, fail over, positioning, and interconnects with optional quick disconnects and retractors.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: February 5, 2019
    Inventor: Richard Anthony Dunn, Jr.
  • Patent number: 10192673
    Abstract: An inductor includes a body including a coil part therein. The coil part includes a support member and first and second coil patterns respectively formed on an upper surface and a lower surface of the support member, and 1.15?b/a?1.45, where a is a length from a central plane between the upper surface and the lower surface of the support member to an upper surface of the body, and b is a length from the central plane of the support member to a lower surface of the body.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chan Yoon, Dong Hwan Lee, Young Ghyu Ahn
  • Patent number: 10181411
    Abstract: An insulating second element is provided and overlies a surface of a first element which consists essentially of a material having a CTE of less than 10 ppm/° C. and has a first thickness in a first direction normal to the surface. Openings extend in the first direction through the second element. The first element is abraded to produce a thinned first element having a second thickness less than the first thickness. Conductive elements are formed at a first side of the interposer coincident with or adjacent to a surface of the thinned first element remote from the second element. A conductive structure extends through the openings in the second element, wherein the conductive elements are electrically connected with terminals of the interposer through the conductive structure, and the terminals are disposed at a second side of the interposer opposite from the first side.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 15, 2019
    Assignee: Invensas Corporation
    Inventors: Michael Newman, Cyprian Uzoh, Charles G. Woychik, Pezhman Monadgemi, Terrence Caskey
  • Patent number: 10179950
    Abstract: Reliability of a plating process and reliability of a component manufactured through the plating process can be improved by suppressing peeling between plating layers formed by electroless plating. In a plating method, a plated component manufactured by the plating method, and a plating system 1 configured to manufacture the plated component by the plating method, a second electroless plating layer 39, which is made of a copper alloy and formed by the electroless plating, is formed on a surface of a first electroless plating layer 38 formed by the electroless plating. The first electroless plating layer 38 is a barrier layer configured to suppress diffusion of copper and is made of cobalt or a cobalt alloy. The second electroless plating layer 39 is a seed layer for forming an electrolytic plating layer of copper on a surface thereof and is made of an alloy of copper and nickel.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 15, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuichiro Inatomi, Takashi Tanaka, Nobutaka Mizutani
  • Patent number: 10181431
    Abstract: Package substrate and a method of manufacturing the same is disclosed. The package substrate includes an insulating layer having first circuit patterns embedded in a first surface of the insulating layer, and a protruded circuit pattern formed above at least one of the embedded first circuit patterns, wherein a width of the protruded circuit pattern is greater than a width of each of the embedded first circuit patterns. Accordingly, a flip chip and a wire bonding chip may be installed at the same time owing to an embedded structure of circuit pattern and a protruded structure of circuit pattern realized together on a surface where an electronic component is to be installed. Moreover, a fine circuit pattern may be formed, and a surface treatment layer may be selectively formed at desired portions without forming an additional seed layer for electroplating, thereby possibly simplifying manufacturing processes and saving manufacturing costs.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 15, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong-Uk Lee, Young-Gon Kim, Jin-Young Yoon
  • Patent number: 10109579
    Abstract: A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10070536
    Abstract: Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A dicing process is performed, such that at least one slit is formed in the glass film. A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on the glass film. A polymer layer is formed on the first circuit layer. The polymer layer covers surfaces of the first circuit layer and the glass film. A plurality of second conductive vias are formed in the polymer layer. A second circuit layer is formed on the polymer layer, such that a first circuit board structure is formed. A singulation process is performed, such that the first circuit board structure is divided into a plurality of second circuit board structures.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: September 4, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Chien-Tsai Li, Chien-Te Wu, Cheng-Chung Lo
  • Patent number: 10070525
    Abstract: Methods/structures of forming package structures are described. Those methods/structures may include forming a first sub-laminated board comprising a first horseshoe structure that is disposed on a top surface of a first outer ground structure, forming a second sub-laminated board comprising a second horseshoe structure disposed on a second outer ground structure, wherein the second sub-laminated board comprises a stripline trace on a top surface of the second sub-laminated board, and laminating the first sub-laminated board to the second sub-laminated board, wherein the first and second horseshoe structures are in contact with each other during the lamination process.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Adrian Rodriguez, Matthew G. Priolo
  • Patent number: 10070511
    Abstract: A wiring board includes an insulating resin layer including resin material and filler, and a conductive circuit layer laminated on a surface of the insulating resin layer and having wiring patterns. The filler has particle diameters of 15% or less of a minimum width of the wiring patterns when the particle diameters of the filler is measured in a unit range defined such that the unit range has a width and a length where the length is measured from the surface of the insulating resin layer and is selected from a smaller of twice the minimum width of the wiring patterns and a plate thickness of the insulating resin layer, and the width is twice the minimum width of the wiring patterns.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 4, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoshinori Takenaka, Hiroyasu Noto
  • Patent number: 10068851
    Abstract: A semiconductor package structure includes a first dielectric layer, a conductive element, a first circuit structure, a semiconductor die and an encapsulant. The first dielectric layer defines at least one through hole. The conductive element is disposed in the through hole and including a first portion and a second portion. A first surface of the first portion is substantially coplanar with a first surface of the first dielectric layer, and a portion of a first surface of the second portion is recessed from the first surface of the first dielectric layer. The first circuit structure is disposed on the first dielectric layer. The semiconductor die is electrically connected to the first circuit structure. The encapsulant covers the semiconductor die.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: September 4, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10062627
    Abstract: According to one embodiment, a semiconductor device includes a substrate, semiconductor chips mounted on the substrate, a sealing resin layer that seals the semiconductor chips, and a film covering at least an upper surface of the sealing resin layer, the film made from a material selected from the group consisting of zinc, aluminum, manganese, alloys thereof, metal oxides, metal nitrides, and metal oxynitrides.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: August 28, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masaji Iwamoto
  • Patent number: 10050004
    Abstract: A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating layer over the temporary carrier. Conductive pads can be formed within openings in the insulating layer and be positioned both within and without the die mounting area. A backside redistribution layer (RDL) can be formed over the temporary carrier before mounting a semiconductor die at the die mounting site. Conductive interconnects can be formed over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted face up to the insulating layer. The conductive interconnects, backside RDL, and semiconductor die can be encapsulated with a mold compound. A build-up interconnect structure can be formed and connected to the semiconductor die and the conductive interconnects. The temporary carrier can be removed and the conductive pads exposed in a grinding process.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: August 14, 2018
    Assignee: DECA Technologies Inc.
    Inventors: Christopher M. Scanlan, William Boyd Rogers, Craig Bishop
  • Patent number: 10049896
    Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sushumna Iruvanti, Shidong Li, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 10045435
    Abstract: A multilayer printed circuit board comprising: i) a plurality of circuit board layers disposed in parallel planes to one another; ii) an outer via forming an electrical connection between a conductor contact on a first circuit board layer and a conductor contact on a second circuit board layer, wherein the outer via has a hollow central core; and iii) an inner via formed within the hollow central core of the outer via. The inner via forms an electrical connection between a conductor contact on a third circuit board layer and a conductor contact on a fourth circuit board layer. The inner via and the outer via are substantially concentric cylinders.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: August 7, 2018
    Assignee: L-3 Communications Corporation
    Inventors: Dennis Jones, Christopher Anthony Gracia, Larry Brown, David Nail
  • Patent number: 10037897
    Abstract: A semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor element includes at least one conductive layer and at least one via layer. The insulating layer is positioned above the first semiconductor device and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one TIV has a conductive core including a copper-containing material. The second semiconductor element is positioned above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Patent number: 10026687
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: July 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sean Xuan Lin, Xunyuan Zhang, Shao Beng Law, James Jay McMahon
  • Patent number: 10015890
    Abstract: A method of manufacturing a conductive layer on a support body includes a first process of forming a precursor layer containing at least one of metal particles and metal oxide particles on the support body; a second process of forming a sintering layer by irradiating an electromagnetic wave pulse on the precursor layer; and a third process of compressing the sintering layer. The conductive layer is formed by repeating the first to third processes “N” times, where “N” denotes a natural number equal to or greater than 2, on the same location of the support body, and the third process performed in the first to (N?1)th operations includes forming a surface of the sintering layer in an uneven shape.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: July 3, 2018
    Assignee: FUJIKURA LTD.
    Inventors: Masahiro Kaizu, Masateru Ichikawa
  • Patent number: 10010001
    Abstract: A circuit board comprises a third conductive circuit layer, a third insulating layer, a first insulating layer, a first conductive circuit layer, a substrate, a second conductive circuit layer, a second insulating layer, a fourth insulating layer, and a fourth conductive circuit layer in that order from top to bottom. The circuit board defines at least one first conductive hole and at least one second conductive hole. Each one of the first conductive hole comprises a first conductive blind hole, and a third conductive blind hole aligned with and electrically connected to the first conductive blind hole. Each one of the second conductive hole comprises a second conductive blind hole, and a fourth conductive blind hole aligned with and electrically connected to the second conductive blind hole. A method for making the circuit board is also provided.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 26, 2018
    Assignees: Avago Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co
    Inventors: Meng-Lu Jia, Hai-Bo Qin
  • Patent number: 10010019
    Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component with contact terminals and conducting lines in a first wiring layer. There is also a dielectric between the component and the first wiring layer such that the component is embedded in the dielectric. Contact elements provide electrical connection between at least some of the contact terminals and at least some of the conducting lines. The electronic module also comprises a second wiring layer inside the dielectric. The second wiring layer comprises a conducting pattern that is at least partly located between the component and the first wiring layer and provides EMI protection between the component and the conducting lines.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: June 26, 2018
    Assignee: GE Embedded Electronics Oy
    Inventor: Risto Tuominen
  • Patent number: 10004144
    Abstract: A connector module includes a substrate including stacked magnetic layers, a first principal surface, and a second principal surface opposite to the first principal surface, a surface mount connector mounted on mounting electrodes on the first principal surface of the substrate, external mounting electrodes disposed on the second principal surface of the substrate, and inductors inside the substrate and each connected at a first end thereof to a corresponding one of the mounting electrodes and connected at a second end thereof to a corresponding one of the external mounting electrodes.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: June 19, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hirokazu Yazaki
  • Patent number: 9996653
    Abstract: The subject technology provides a method and apparatus for performing dual track routing. A pair of signal traces is routed in between two rows of contacts and at least one of the signal traces is modified to satisfy a routing restriction. The modification of the signal trace includes three trace segments that deviate the signal trace away from the source of the routing restriction.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: June 12, 2018
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Lin Shen, Yongming Xiong, Shahbaz Mahmood, Maurilio De Nicolo
  • Patent number: 9991195
    Abstract: The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 5, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hiromitsu Takeda