Feedthrough Patents (Class 174/262)
  • Patent number: 11363719
    Abstract: A wiring substrate includes a core substrate, and a build-up part laminated on the substrate and including resin insulating layers. The insulating layers include a first insulating layer, the build-up part includes a conductor layer on the first insulating layer, a second insulating layer on the first insulating layer and covering the conductor layer, and a recess penetrating through the second insulating layer and exposing portion of the conductor layer such that the conductor layer includes component mounting region that places an electronic component in the recess and a conductor pad forming bottom surface of the recess, the insulating layers include inorganic filler such that all insulating layers or all insulating layers other than the first insulating layer include the inorganic filler and that inorganic filler content rate of the first insulating layer is lower than inorganic filler content rate of the insulating layers other than the first insulating layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: June 14, 2022
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroyasu Noto, Kentaro Wada
  • Patent number: 11322301
    Abstract: A method for manufacturing an inductor built-in substrate includes forming openings in a core substrate including a resin substrate and a metal foil laminated on the resin substrate, filling a magnetic resin in the openings formed in the substrate, forming a shield layer including a first plating film on the substrate and on a surface of the magnetic resin such that the shielding layer is formed on the metal foil and on the surface of the magnetic resin, forming first through holes in the substrate, applying a desmear treatment in the first through holes, forming second through holes in the magnetic resin after the desmear treatment, and forming a second plating film on the substrate, on the magnetic resin, and in the first and second through holes such that the second plating film is formed on the shield layer, in the first through holes, and in the second through holes.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: May 3, 2022
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroaki Kodama, Kazuro Nishiwaki, Kazuhiko Kuranobu, Hiroaki Uno
  • Patent number: 11316120
    Abstract: The present invention provides a flexible substrate and a display panel. The flexible substrate comprises a substrate and a plurality of traces. The traces are disposed on the substrate. The substrate is further provided with a plurality of first via holes, and the first via holes are disposed along an extending direction of the traces.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 26, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Jian Ye
  • Patent number: 11315718
    Abstract: A coil component includes a body including a plurality of pattern layers and a via electrode layer connecting the respective conductive pattern layers to each other, and external electrodes disposed on an external surface of the body. A cross-sectional shape of the via electrode layer is divided into an upper region and a lower region, a side surface of the upper region has a tapered shape, and a lower surface of the lower region includes a curved portion.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Hye Won Jung
  • Patent number: 11317518
    Abstract: Systems and methods are provided to produce electromechanical interconnections within integrated circuits (ICs), printed circuit boards (PCBs) and between PCBs and other electronic components such as resistors, capacitors and integrated circuits. Elements include so-called “smart pins” or “neuro-pins” that facilitate electrical pathways in the dimension normal to the plane of a PCB. Smart pins or neuro-pins may be inserted using automated processes that do not require the high temperatures normally associated with soldering. Resultant circuits generally contain a large number of layers that are more compact and more readily constructed compared with conventional PCB-based circuitry.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: April 26, 2022
    Inventors: Lewis James Marggraff, Nelson G. Publicover, Blake Marggraff, Edward D. Krent, Marc M. Thomas
  • Patent number: 11315890
    Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 26, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chintan Buch, Roman Gouk, Steven Verhaverbeke
  • Patent number: 11308022
    Abstract: A motherboard may utilize a retimer device to condition signals used for high-speed USB data transfers. Motherboard embodiments include a common footprint for USB retiming capabilities. A motherboard that supports high-speed USB transfers, such as transfers of 10 Gbps or greater, utilizes a retimer in the footprint. A motherboard that supports lower-speed USB transfers, such as 5 Gbps, utilizes a passive bridge component in the footprint, where the bridge may be formed from a dielectric substrate. During manufacture of an IHS (Information Handling System) a common motherboard is selected that includes a retimer footprint, where the motherboard includes traces that couple the footprint to a USB connector and traces that couple the footprint to a USB controller. Based on the USB transfer speeds to be supported by the motherboard, a USB retimer or a passive bridge is installed in the retimer footprint.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: April 19, 2022
    Assignee: Dell Products, L.P.
    Inventor: Jonathan C. Giffen
  • Patent number: 11304311
    Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 12, 2022
    Assignee: SANMINA CORPORATION
    Inventors: Shinichi Iketani, Drew Doblar
  • Patent number: 11302846
    Abstract: A light emitting device package disclosed to an embodiment of the invention includes a body including an upper surface and a lower surface, the body including a first recess and a second recess concaved from the lower surface toward the upper surface; a light emitting device disposed on the body and including a first bonding portion and a second bonding portion; and first and second conductive portions respectively disposed in the first recess and the second recess, wherein the body includes a first through hole and a second through hole penetrating an upper surface of each of the first recess and the second recess and the upper surface of the body, and wherein each of the first and second conductive portions extends into the first and second through holes and is electrically connected to the first bonding portion and the second bonding portion, respectively.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: April 12, 2022
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Min Sik Kim, Won Jung Kim, Ki Seok Kim
  • Patent number: 11304298
    Abstract: A coaxial thru-via conductor and a method of fabricating the coaxial thru-via conductor can provide enhanced operations for semiconductor devices mounted on a substrate.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 12, 2022
    Inventor: Timothy Leigh LeClair
  • Patent number: 11284509
    Abstract: Disclosed is a stretchable substrate including: a via configured to provide an electrical connection between one surface and the other surface of the stretchable substrate; and a buffer shell positioned between the via and the stretchable substrate and having a Young's modulus value that is greater than a Young's modulus value of the stretchable substrate and smaller than a Young's modulus value of the via.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: March 22, 2022
    Assignee: Seoul National University R&DB Foundation
    Inventors: Yongtaek Hong, Eunho Oh, Junghwan Byun, Byeongmoon Lee
  • Patent number: 11282634
    Abstract: A coil electronic component includes a body and external electrodes disposed on an external surface of the body. The body includes a support member including a through-hole, upper and lower coils supported by the support member and including a plurality of coil patterns, a via connecting the upper and lower coils to each other, and an insulating wall supported by the support member and insulating adjacent coil patterns from each other. The via is formed on at least a portion of a interface of the through-hole.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Sun Kim, Kwang Il Park
  • Patent number: 11259418
    Abstract: A multilayer substrate includes a plurality of insulator layers laminated, a column conductor extending through two or more insulator layers among the plurality of insulator layers. The column conductor includes a first via conductor extending through a first insulator layer and a second via conductor extending through a second insulator layer adjacent to the first insulator layer. Each of the first via conductor and the second via conductor has a tapered shape in which a cross section decreases from one end portion to the other end portion in the lamination direction of the plurality of insulator layers. The first via conductor and the second via conductor are directly bonded to each other at large diameter portions that are end portions with a large cross section or small diameter portions that are end portions with a small cross section.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: February 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Saneaki Ariumi
  • Patent number: 11252824
    Abstract: Disclosed are a method for fabricating a printed circuit board wherein through-holes are formed in an organic substrate, followed by forming micro-circuit patterns through sputtering and plating, whereby the printed circuit board has low permittivity properties and enables high-speed processing, and a printed circuit board fabricated thereby. The disclosed method for fabricating a printed circuit board comprises the steps of: preparing a base substrate; forming a through-hole perforating the base substrate; forming a thin seed layer on the base substrate and in the through-hole; forming a thin plate layer on the thin seed layer; and etching the thin seed layer and the thin plate layer to form a micro-circuit pattern, wherein the base substrate is one selected from an organic substrate, FR-4, and Prepreg.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: February 15, 2022
    Assignee: AMOGREENTECH CO., LTD.
    Inventor: Sung-Baek Dan
  • Patent number: 11244966
    Abstract: A micro LED display panel and a method for fabricating the same are disclosed, and the micro LED display panel includes a TFT back panel, and a micro LED fixed on the TFT back panel, wherein the TFT back panel includes a substrate, and a first insulation layer and a second insulation layer stacked over the substrate in that order, wherein the first insulation layer includes a groove filled with the second insulation layer, and a normal projection of the groove onto the substrate does not overlap with a normal projection of a TFT area in the TFT back panel onto the substrate, wherein the rigidity of the second insulation layer is lower than the rigidity of the first insulation layer.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: February 8, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Haixu Li, Zhanfeng Cao, Ke Wang
  • Patent number: 11237666
    Abstract: A fabrication method of a panel, a panel and a display device are provided. The fabrication method of the panel includes: forming a first conductive layer on a base substrate by using a patterning process, the first conductive layer including a plurality of first conductive traces provided in a non-working region of the base substrate and a plurality of electrode patterns provided in a working region of the base substrate; forming a plurality of metal traces on the plurality of first conductive traces, wherein, each of the metal traces includes a connection end close to an edge of the working region of the base substrate.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: February 1, 2022
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Jun Chen, Ming Zhang, Zhanqi Xu, Cui Chen, Yang Li
  • Patent number: 11234326
    Abstract: Provided is a printed circuit board realizing selective inhibition of electromagnetic noise and enabling high-density arrangement of differential transmission lines without increasing cost. The printed circuit board includes a pair of strip conductors (first layer), a first resonance conductor plate, a ground conductive layer (together with a second layer) including an opening portion, a second resonance conductor plate (third layer), a third resonance conductor plate (fourth layer), first via holes connecting the first and second resonance conductor plates, a second via hole connecting the second and third resonance conductor plates, and third via holes connecting the third resonance conductor plate and the ground conductive layer, wherein a polygon obtained by sequentially connecting centers of the adjacent third via holes overlaps so as to include the first resonance conductor plate, and center-to-center distance between the adjacent third via holes is 0.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: January 25, 2022
    Assignee: Lumentum Japan, Inc.
    Inventor: Osamu Kagaya
  • Patent number: 11222835
    Abstract: An insulating circuit substrate includes an insulating layer; and a circuit layer formed on one surface of the insulating layer, in which the insulating layer has a core layer formed of an epoxy resin containing an inorganic filler, and a skin layer formed on the circuit layer side of the core layer and formed of a polyimide resin containing an inorganic filler, an amount of the inorganic filler in the epoxy resin forming the core layer is in a range of 80 vol % or more and 95 vol % or less, and an amount of the inorganic filler in the polyimide resin forming the skin layer is in a range of 10 vol % or more and 30 vol % or less.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: January 11, 2022
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Yoshiaki Sakaniwa, Toyo Ohashi
  • Patent number: 11215893
    Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display apparatus. The array substrate includes a plurality of pad structures located in a bonding region and a plurality of data leads located in a lead region. Each data lead corresponds to one pad structure. The pad structure includes at least two pad electrodes insulated from each other. In the pad structure, each pad electrode is electrically connected to the data lead corresponding to the pad structure, respectively, to form different signal writing paths.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 4, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yunze Li, Ni Yang, Zhijian Qi, Xiaoyuan Wang, Shaoru Li
  • Patent number: 11206737
    Abstract: A composite electronic component includes a composite body in which a multilayer ceramic capacitor and a ceramic chip are coupled to each other, the multilayer ceramic capacitor including a first ceramic body in which a plurality of dielectric layers and internal electrodes disposed to face each other with respective dielectric layers interposed therebetween are stacked, and first and second external electrodes disposed on both end portions of the first ceramic body, and the ceramic chip being disposed on a lower portion of the multilayer ceramic capacitor and formed of a ceramic material having substantially no piezoelectric property, wherein a ratio (T/L) of thickness (T) of the ceramic chip to length (L) of the multilayer ceramic capacitor is selected to minimize vibration of the ceramic chip.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: December 21, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Man Su Byun, Ho Yoon Kim, Kyung Hwa Yu, Dae Heon Jeong, Min Kyoung Cheon, Soo Hwan Son
  • Patent number: 11189500
    Abstract: A method of manufacturing a component carrier includes: i) forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, with at least one cavity formed in the stack, ii) forming a cluster by encapsulating a first electronic component and a second electronic component in a common encapsulant, and thereafter iii) placing the cluster in the common encapsulant at least partially into the cavity and v) embedding the cluster in the cavity.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 30, 2021
    Assignee: AT&S (Chongqing) Company Limited
    Inventor: Minwoo Lee
  • Patent number: 11178761
    Abstract: A printed circuit board includes a printed circuit board includes a substrate portion having a recess portion and including a first circuit layer, abridge disposed in the recess portion and including an insulating layer and a bridge circuit layer, an insulating material disposed in at least a portion of the recess portion and covering at least a portion of the bridge, a second circuit layer disposed on the insulating material, and a first via penetrating through the insulating material and a portion of the bridge and connecting the second circuit layer and the bridge circuit layer to each other.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jung Hyun Cho, Kyung Hwan Ko, Chi Won Hwang
  • Patent number: 11171078
    Abstract: A semiconductor device includes an insulated circuit board having conductor layers arranged away from each other and bonding materials each provided on the conductor layers; a wiring board having an opposing surface facing the conductor layers and through holes each corresponding to a position of each bonding material; hollow members each having a cylindrical portion and a flanged portion at one end of the cylindrical portion and having a cavity in common with the cylindrical portion, ok cylindrical portions press-fitted into the through holes, and other ends of the cylindrical portions bonded to the conductor layers by the bonding materials; and external connection terminals each inserted into the cavity of each hollow member and bonded to the conductor layers. Each cylindrical portion is inserted into each through hole such that each flanged portion contacts with an upper surface opposed to the opposing surface of the wiring board.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: November 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichiro Hinata, Tatsuo Nishizawa
  • Patent number: 11145602
    Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Ju Li, Jhih-Yuan Chen, Hsin-Jung Liu, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Fu-Chun Hsiao, Ji-Min Lin, Chun-Han Chen
  • Patent number: 11096270
    Abstract: A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 17, 2021
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 11088089
    Abstract: A package substrate includes a wiring substrate comprising an insulating layer, a first wiring layer, and a second wiring layer, wherein the first wiring layer comprises a first pad pattern, and the second wiring layer comprises a second pad pattern; a first passivation layer disposed on the insulating layer, and having a first opening portion passing through a region corresponding to at least a portion of the first pad pattern; a second passivation layer disposed on the insulating layer, and having a second opening portion passing through a region corresponding to at least a portion of the second pad pattern; and a reinforcing layer disposed on the second passivation layer, and having a through portion exposing the second opening portion. An upper surface of the first wiring layer is located in a position higher than a position of the lower surface of the insulating layer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yoong Oh, Sang Hoon Kim, Young Kuk Ko, Yong Soon Jang
  • Patent number: 11083091
    Abstract: Disclosed are a hole connecting layer manufacturing method, a circuit board manufacturing method and a circuit board. The hole connecting layer manufacturing method comprises: adhering a first insulating dielectric layer, used for laminating and filling, to a daughter board; laminating and solidifying the first insulating dielectric layer on the daughter board; adhering a second insulating dielectric layer, used for laminating and filling, to the first insulating dielectric layer which has been laminated and solidified; manufacturing a first receiving hole on the first insulating dielectric layer and a second receiving hole on the second insulating dielectric layer, wherein the first receiving hole and the second receiving hole are provided vertically opposite to each other; filling both the first receiving hole and the second receiving hole with a conductive medium to complete manufacturing of the hole connecting layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 3, 2021
    Assignees: GUANGZHOU FASTPRINT CIRCUIT TECH CO., LTD., SHENZHEN FASTPRINT CIRCUIT TECH CO., LTD., YIXING SILICON VALLEY ELECTRONICS TECH CO., LTD.
    Inventors: Zeyang Lian, Sen Wu, Yanguo Li, Bei Chen
  • Patent number: 11044805
    Abstract: The present disclosure provides a double-sided two-dimensional coding, includes a transparent medium layer on which a metal layer is plated, and a two-dimensional coding image is fused through the metal layer. The present disclosure also provides a flexible printed circuit and manufacturing method for a double-sided two-dimensional coding. By lasering the metal layer corresponding to the transparent medium layer, the metal layer is fused through to form a two-dimensional coding image, and the transparent medium layer is retained as a carrier of the two-dimensional coding image, and an effect of reading the two-dimensional coding on both sides can be achieved.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 22, 2021
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO.LTD.
    Inventor: Hao-Yang Xiao
  • Patent number: 11039535
    Abstract: A method includes providing an electrically conductive layer structure on top of an electrically insulating layer structure, forming a window in the electrically conductive layer structure and removing material of the electrically insulating layer structure below the window by a first laser beam, and subsequently removing further material of the electrically insulating layer structure below the window by a second laser beam having a smaller size than a size of the window.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 15, 2021
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Seok Kim Tay, Abderrazzaq Ifis, Haina Wu
  • Patent number: 11032917
    Abstract: A circuit carrier board includes a first substrate and a second substrate bonding to the first substrate. The first substrate includes a first circuit layer connecting to a plurality of conductive structure. The conductive structures connect to electronic elements. The second substrate contacts the first circuit layer. The second substrate includes a plurality of stacked dielectric layers, and a plurality of second circuit layers are disposed in the dielectric layers. The bottommost layer of the second circuit layers is exposed outside of the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first circuit layer. The conductive structure includes a pad and a conductive via. The pad electrically connects to the first circuit layer. A linewidth of the first circuit layer is smaller than a linewidth of the second circuit layer. A manufacturing method of the circuit carrier board is also provided.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: June 8, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Fu-Yang Chen
  • Patent number: 11031329
    Abstract: A method of fabricating a packaging substrate is provided, which includes: forming on a carrier a conductor layer having a plurality of openings; forming a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body disposed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with the conductive pad and less in width than the conductive pad; forming a plurality of conductive posts on the conductive pads; forming on the carrier a first insulating layer that encapsulates the conductive bumps and the conductive posts; removing the carrier; and removing the entire conductor layer to expose the post bodies from a first surface of the first insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 8, 2021
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chu-Chin Hu, Shih-Ping Hsu, Che-Wei Hsu, Chin-Ming Liu, Chih-Kuai Yang
  • Patent number: 11011551
    Abstract: An array substrate and display apparatus, the array substrate comprising a base substrate (10) and signal lines (VDD, VSS) provided on the base substrate (10), wherein at least one electrically conductive element (12) corresponding to the signal lines (VDD, VSS) is further provided on the base substrate (10), the signal lines (VDD, VSS) are connected in parallel with corresponding electrically conductive elements (12), and the electrically conductive elements (12) corresponding to different signal lines (VDD, VSS) are insulated from one another. Thus, resistance of the signal lines (VDD, VSS) can be reduced and the display effect can be improved.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 18, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiangdan Dong, Young Yik Ko, Jinsan Park
  • Patent number: 10999939
    Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Patent number: 10998258
    Abstract: A circuit carrier includes a substrate, a laminar circuit structure, a metal heat slug, a first fixing piece, and a second fixing piece. The laminar circuit structure is disposed over the substrate and includes a plurality of dielectric layers and circuits in the dielectric layers. The metal heat slug is disposed in the laminar circuit structure. The first fixing piece is disposed on the first side of the upper surface of the metal heat slug. The second fixing piece is disposed on the second side of the upper surface of the metal heat slug, wherein the first side is perpendicular to the second side. A method of manufacturing a circuit carrier is also provided herein.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Unimicron Technology Corp.
    Inventor: Tzu-Hsuan Wang
  • Patent number: 10993313
    Abstract: A component carrier including a stack with a plurality of electrically insulating layer structures and/or a plurality of electrically conductive layer structures, and a non-uniform magnetic foil integrated in the stack.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 27, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Gerald Weidinger, Jonathan Silvano de Sousa
  • Patent number: 10971914
    Abstract: The heat dissipation of a circuit assembly is improved. A circuit assembly includes: a relay that includes a terminal and generates heat when energized/as a result of energization/due to being energized; a base member to which the relay is attached and in which a through hole is formed; a heat dissipation member that is provided on a side of the base member opposite to a side on which the relay is attached; a first busbar that is connected to the terminal of the relay at a position spaced apart from the base member; and a heat transfer member that is inserted into the through hole so as to be movable in a direction along the axial direction of the through hole, and that comes into contact with the first busbar and the heat dissipation member.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: April 6, 2021
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD. <
    Inventors: Yuki Fujimura, Ryoya Okamoto, Hiroshi Shimizu
  • Patent number: 10966326
    Abstract: A wiring substrate includes a laminate having a through hole and including conductor layers and insulating layers interposed between the conductor layers, solder resist layers formed on the laminate and including a first solder resist layer covering first surface of the laminate and a second solder resist layer covering second surface of the laminate and that the first and second solder resist layers have openings exposing the through hole, and a resin film covering the laminate not covered by the solder resist layers such that the resin film is formed on the first and second surfaces of the laminate inside the openings of the first and second solder resist layers without overlapping with the solder resist layers on the first and second surfaces and that the resin film covers inner wall surface inside the through hole and at least part of the first and second surfaces exposed inside the openings.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: March 30, 2021
    Assignee: IBIDEN CO., LTD.
    Inventors: Kotaro Takagi, Yoji Mori
  • Patent number: 10932373
    Abstract: Provided is a circuit board for reducing a likelihood of so-called through-hole disconnection, and enhancing connection reliability on both sides of a substrate via a through-hole. The circuit board has a substrate with the through-hole, a first conductive part covering an opening of the through-hole on one surface of the substrate in a manner blocking the opening, having a portion inserted into the through-hole from the one surface, and a second conductive part covering a second opening of the through-hole on the other surface of the substrate in a manner blocking the second opening, having a portion inserted into the through-hole from the other surface. The portion of the first conductive part inserted in the through-hole has a columnar shape forming a columnar portion having a diameter smaller than the through-hole.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: February 23, 2021
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Akihiko Hanya
  • Patent number: 10930594
    Abstract: In a case of a multilayer wiring structure in which an insulating layer provided between wires is made of a material having high transmittance of light in a visible range containing ultraviolet rays, wires in the upper layer and those in a lower layer may be recognized together when defects of an upper layer are visually inspected. In this case, the lower layer may be noise for the inspection of the wires in the upper layer, lowering inspection accuracy. This lowered inspection accuracy has inhibited improvement in manufacturing yields and reliability. In order to solve this issue, a multilayer wiring substrate of the disclosure includes: a substrate; and a first wire and a second wire that are provided on the substrate with an insulating layer having a light transmitting property in between, and one or both of which are subjected to a surface treatment.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: February 23, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Toshihiko Watanabe
  • Patent number: 10930989
    Abstract: It has been difficult to suppress electromagnetic wave that propagates within a suspended substrate. The structure according to the present invention is provided with: a first conductor plane and a second conductor plane that are disposed parallel to each other; a dielectric plane that is disposed between the first and second conductor planes via a hollow region so as to be parallel to the first and second conductor planes; a first transmission line disposed on a surface that is of the dielectric plane and that opposes the first conductor plane; and a second transmission line disposed on a surface that is of the dielectric plane and that opposes the second conductor plane, wherein the first transmission line and the second transmission line are electrically connected to each other.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 23, 2021
    Assignee: NEC CORPORATION
    Inventors: Takahide Yoshida, Hiroshi Toyao, Eiji Hankui
  • Patent number: 10904998
    Abstract: A signal trace on a printed circuit board (PCB) includes a first trace segment on a first layer of the PCB, the first trace segment having a first end coupled to a transmitter, having a second end, and having a first characteristic impedance that is matched to the transmitter. The signal trace further includes a signal via passing from the first layer of the PCB to a second layer of the PCB, the signal via having a first contact connected to the second end of the first trace segment, having a second contact on the second layer, and having a second characteristic impedance different from the first characteristic impedance. The second characteristic impedance is determined based upon a first distance between the transmitter and the first via.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: January 26, 2021
    Assignee: Dell Products, L.P.
    Inventors: Mallikarjun Vasa, Bhyrav M. Mutnury
  • Patent number: 10905007
    Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 26, 2021
    Assignee: Qorvo US, Inc.
    Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
  • Patent number: 10905013
    Abstract: In a wiring base body of a printed wiring board, a conductive post including a wiring portion and a wiring are embedded in an insulating resin film. Therefore, even in a region in which a wiring portion is formed, the wiring base body is not increased in thickness. In addition, even in a region in which a wiring is formed, the wiring base body is not increased in thickness. Therefore, it is possible to obtain a printed wiring board having high flatness by stacking a plurality of wiring base bodies and constituting a printed wiring board.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 26, 2021
    Assignee: TDK CORPORATION
    Inventors: Takaaki Morita, Seiichi Tajima, Takashi Kariya
  • Patent number: 10887985
    Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 5, 2021
    Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
  • Patent number: 10887989
    Abstract: A printed wiring board of the present invention includes an insulating substrate layer; a first conductive layer laminated to one surface of the substrate layer; a second conductive layer laminated to another surface of the substrate layer; and a via hole formed along an inner surface of a connection hole that is provided, in a thickness direction, through the substrate layer and the first conductive layer, the via hole electrically coupling the first conductive layer and the second conductive layer. A cross-sectional shape of the connection hole along at least one surface of the substrate layer is an irregular shape.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: January 5, 2021
    Assignees: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tadahiro Kaibuki, Daisuke Sato, Haruna Oya, Yoshiaki Yanagimoto, Atsushi Kimura, Shigeki Shimada
  • Patent number: 10886211
    Abstract: A wiring board includes: a Cu pad; an insulating layer covering the Cu pad and having an opening portion; a first metallic layer formed on the Cu pad in the opening portion; and a connecting terminal formed on the first metallic layer to extend from the opening portion to above an upper surface of the insulating layer. The connecting terminal includes: a seed layer formed on the first metallic layer; and a second metallic layer formed on the seed layer. A stacked body is formed of the first metallic layer and the connecting terminal and includes a constricted portion. The constricted portion is located in a certain position of the first metallic layer in a thickness direction of the first metallic layer, and a sectional area of the stacked body is the smallest at the constricted portion.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 5, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yasuyuki Yamaguchi
  • Patent number: 10888001
    Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 5, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
  • Patent number: 10887980
    Abstract: A coupled via structure includes a plate via penetrating through an board body and having first and second plates spaced apart from each other by a first gap distance, a contact pad connected to the plate via on a surface of the board body and having first and second contacts connected to the first and second plates, respectively, and a connection line connected to the contact pad on the surface of the board body and having first and second lines connected to the first and second contacts, respectively, and spaced apart from the first line by a second gap distance. Accordingly, the deviation of the characteristic impedance is reduced (or, alternatively, minimized) between the coupled via structure and the coupled signal line.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: January 5, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNKYUNKWAN UNIVERSITY
    Inventors: Dong-Yoon Seo, Jea-Eun Lee, WanSoo Nah
  • Patent number: 10877534
    Abstract: Disclosed herein is a power supply apparatus that includes a bearing plate, insulation material and a plurality of pins. The insulation material is formed on two opposite surfaces of the bearing plate. The plurality of pins are electrically connected to the bearing plate and allocated along lateral sides of the insulation material.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 29, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Jian-Hong Zeng
  • Patent number: 10872878
    Abstract: Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chuei-Tang Wang, Monsen Liu, Chen-Hua Yu