Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.

Abstract: An integrated circuit package substrate. At least one insulating layer is formed between every two neighboring patterned wiring layers for isolation. At least a via is formed to penetrate through the insulating layers to electrically connect the patterned wiring layers. A capacitor is formed within at least one of the insulating layer. The capacitor has two electrodes insulated by a dielectric layer. One of the electrodes is connected to a power source, while the other is connected to ground.

Abstract: A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.

Abstract: Via holes are plated through the substrate of a surface mount package. The leads of an electronic device is inserted in the plated-through via holes. The bottom of the plated through metal is enlarged as pads to provide reliable soldering surfaces to a motherboard. Upon heating the leads are soldered to the walls of the plated through via holes. Alternatively, the leads can be folded before inserting into the plated-through via holes.

Abstract: A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.

Abstract: A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.

Abstract: A substrate is configured to electrically interconnect a semiconductor chip to an external device. The substrate preferably includes a ground plane that is electrically interconnected to a ground power of the semiconductor chip. An insulating layer is attached to the ground plane. A pattern layer is attached to the insulating layer. The pattern layer includes signal patterns that communicate electrical signals with the semiconductor chip and ground patterns that are electrically interconnected to the ground plane. The ground patterns can include bonding lands to provide electrical connection to the semiconductor chip. The bonding lands can be further provided with first via holes that electrically interconnect the ground patterns to the ground plane.

Abstract: A printed circuit board (PCB) is provided for mounting an electronic package thereon. The PCB includes a center pad centrally located in the PCB, a plurality of input/output (I/O) pins peripherally located in the PCB, and at least one slot formed in the center pad for providing escape areas into which contaminants can escape from solder joints associated with mounting of the electronic package onto the PCB.

Abstract: The invention concerns a PC board with laminates for electrical circuits, the PC board comprising at least one carrier (1) and at least one copper surface layer (7), intended to, after the removal of selected parts, e.g. by etching, function as conductors on the PC board. The new thing is that the carrier at least at some parts has a surface roughness of up to mainly the same size as the thickness of the copper layer and that at least at the above named rough parts is arranged a surface levelling layer (5a,b) between the carrier (1) and the copper layer (7). Further, the invention concerns a method for producing PC board laminate for electrical circuits as above, the laminate comprising a copper layer and a carrier that has a surface roughness of mainly the same size as the thickness of the copper layer.

Abstract: A semiconductor device package includes multiple build-up layers of metal sandwiching non-conductive layers. The metal layers include apertures, or degassing holes. A manual method and a computer-implemented method for designing the semiconductor device packages includes stepping polygons across a representation of a conductive layer. A signal routing layer that includes signal traces is then superimposed on the conductive layer. Signal traces overlap the polygons creating regions of intersection that can be enlarged. Regions of intersection are removed from the polygons and the remaining polygon area is designated as apertures in the conductive layer. A semiconductor device package and packaged integrated circuit includes apertures in a conductive layer such that the apertures generally form a radial pattern outward from a region on the package. Signal traces also traverse the package generally radially outward such that the traces and the apertures do not overlap.

Abstract: A stack including a micro-system having an electrical contact to connect the micro-system to the outside world, a substrate having a first layer formed on the substrate, a through hole extending in an axial direction of the substrate and configured to reveal a rear side of the first layer and to provide a passage to electrically connect to the electrical contact, and a cavity located at an end of the through hole close to the first layer, wherein the cavity has dimensions transverse to the axial direction larger than a diameter of the through hole and forms an overhanging edge around the through hole.

Abstract: An interconnection circuit and related techniques are described. The interconnection circuit includes a plated through hole having a plurality of electrically isolated segments with at least one of the plurality of electrically isolated segments coupled to a signal path and at least one of the electrically isolated segments coupled to ground. With this arrangement, the circuit provides a signal path between a first and a second different layers of a multilayer. By providing one segment as a signal segment and another segment as a ground segment the size and shape of the electrically isolated segments can be selected to provide the interconnection circuit having a predetermined impedance characteristic. The interconnection circuit can thus be impedance matched to circuit board circuits, devices and transmission lines, such as striplines, microstrips and co-planar waveguides.

Abstract: There is provided a printed wiring board in which control of a characteristic impedance of a signal transmission pattern is realized with a small space and at a low cost, its manufacture is easy, a delay is hard to cause, and a high frequency signal can be stably transmitted. The printed wiring board includes a flat plate base material, a signal transmission pattern provided on at least one surface of the base material, for transmitting a high frequency signal, an insulator layer formed to a constant thickness so as to cover the signal transmission pattern, and a control unit provided on the insulator layer so as to be opposite to the signal transmission pattern and to be grounded, for controlling a characteristic impedance of the signal transmission pattern.

Abstract: A multi-layer circuit board is provided that simultaneously optimizes impedance and interference within the multi-layer circuit board and a controlled impedance connector to which it is attached. The multi-layer circuit board includes at least one signal circuit layer, a plurality of signal contacts grouped in differential pairs and located on one signal circuit layer, and a plurality of ground contacts located on at least one ground circuit layer. The signal contacts are arranged in a pattern, or matrix, in which differential pairs of signal contacts are staggered in rows of the pattern. In accordance with an embodiment of the present invention, each differential pair of the multi-layer circuit board is more tightly coupled to a ground contact than to any other signal contact. The multi-layer circuit board, also includes a plurality of signal trace segments arranged in pairs. Both signal trace segments of a pair are equal in length and connect to signal contacts via linear routing channels.

Abstract: An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip.

Abstract: A printed circuit board is disclosed which has conductive pads located near an edge of a board main body on its upper and lower surfaces to reduce the width in the direction of contact sliding and to provide for a smoother connection between electrical contacts of an electrical connector and the conductive pads despite a powdered substance produced as a result of friction between the conductive pads and the electrical contacts. The printed circuit board (1) has conductive pads (14a, 14b) on upper and lower surfaces of the board main body (2) near the edge (3) of the main body (2). Electrical contacts (20) slide over the conductive pads (14a, 14b) from the edge (3) of the board main body (2). The conductive pads (14a, 14b) are connected together by via holes (15a) that are located in the paths of the contacts (20).

Abstract: A first wiring layer and metallized plated-through holes are formed in/on a substrate. A substrate layer is then applied to the top of the substrate by injection molding, during which an injected material passes through the plated-through holes, resulting in polymer studs being produced on an underside of the substrate. A second wiring layer, formed on the substrate layer, is electrically conductively connected to the first wiring layer by blind plated-through holes, and hence to external connections on the polymer studs by the plated-through holes.

Abstract: In manufacturing a double-layered or a multi-layered printed wiring board, a layer of metamorphic substance, which is created by transmuting a substrate material, is formed on an inner wall of a hole during a perforation process of the substrate utilizing radiation energy. The layer of metamorphic substance prevents conductive materials constituting electrical connection means formed on the inner wall of the hole from dispersing over a surface of the substrate or permeating into the substrate.

Abstract: A multi-layer printed circuit board that includes a first layer and a second layer that have first and second signal traces, respectively. The multi-layer printed circuit board includes a via that couples a signal transmitting component to the second signal trace and a throttling member, which is coupled to the first signal trace. The throttling member reduces the speed at which a first signal routed over the first signal trace travels when compared to the speed at which that signal would have traveled had the throttling member been absent.

Abstract: A mechanical-laser structure on a printed circuit board and a carrier. A method for fabricating the mechanical-laser structure includes the following steps. A substrate is provided. A first through hole is formed in the substrate by mechanical drilling. An epoxy plug is formed within the first through hole. A conductive layer is formed on the substrate by compression. The conductive layer is patterned to form conducting wires and exposes the epoxy plug. A micro via is formed within the epoxy plug by laser drilling.

Abstract: A printed wiring board comprises an insulating layer having first and second surfaces and the wiring layers. The insulating layer has a via electrically connected between the wiring layers. The via has one end opened on the first surface and the other end closed by the wiring layer on the second surface. The inner surface of the via is covered with a first plating layer. The first plating layer continuously covers the wiring layer exposed within the via and that portion of the wiring layer which is formed on the first surface and which faces one end of the via. A second plating layer is laminated on the first plating layer. The second plating layer electrically connects the wiring layers by cooperating with the first plating layer.

Abstract: A method is proposed for bonding a BGA (Ball Grid Array) package to a circuit board without causing the collapsing of the BGA package against the circuit board. The proposed method is characterized in the use of two groups of solder balls of different reflow collapse degrees, which are arranged in an interspersed manner among each other in the ball grid array. In one embodiment, the first group of solder balls are homogenously made of a solder material of a specific melting point; and the second group of solder balls each include an outer portion and a core portion, with the outer portion having substantially the same melting point as the first group of solder balls, and the core portion being greater in melting point than the outer portion. In another embodiment, the second group of solder balls are greater in melting point than the first group of solder balls.

Abstract: An electronic package and method of making the electronic package is provided. The package includes a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip.

Abstract: This invention discloses a wafer level packaging method and configuration. This improved wafer level package includes a processed wafer mounted on a first printed circuit board (PCB) carrier. The processed wafer mounted on the PCB carrier board includes a plurality of separated integrated circuit (IC) chips divided by scribe-line gaps wherein each of these scribe-line gaps is filled with flexible gap-filling insulation material. In another preferred embodiment, the wafer-level package further includes a second PCB carried board composed of same material as the first PCB carrier board mounted on top of the wafer. In another preferred embodiment, the wafer-level package, which having the first and the second PCB carrier boards further includes a plurality of connection via penetrating through the first and the second PCB carried board for forming electric connection to the IC chips separated by the scribe-line gaps.

Abstract: A printed wiring board includes a core substrate including a laminated capacitor. The laminated capacitor includes a plurality of composite dielectric layers and a plurality of metal layers stacked alternately. Three types through-hole conductors are provided which extend between the upper and lower surfaces of the core substrate. The first through-hole conductors are directly connected to first metal layers serving one electrode of the laminated capacitor, the second through-hole conductors are directly connected to second metal layers serving the other electrode of the laminated capacitor, and the third through-hole conductors are not connected to any of the first and second metal layers. The first and second through-hole conductors are used for establishing electrical connections between power supply and ground lines and an IC chip mounted on the printed wiring board. The third through-hole conductor is used as a signal line.

Abstract: A multilayer printed wiring board prevents unnecessary emission of electromagnetic waves. The board includes at least two signal wiring layers, at least one ground layer, at least one power source layer, and a ground plane. The board further includes ground wiring adjacent to signal wiring in a signal wiring layer farther apart from said ground layer, the ground wiring being in the signal wiring layer. The ground wiring serves as a return current path for a signal current flowing in the signal wiring. In this structure, the return current path is reserved adjacent to the signal current path and the signal wiring is lower in impedance than the ground plane. The current can be fed back through a shorter closed loop. It is therefore possible to form a small loop to pass a signal current returning to a ground point and flowing through each signal wiring arranged in the board and a return current of the signal current. This minimizes unnecessary emission of electromagnetic waves.

Abstract: Conductive materials that have low coefficients of thermal expansion (CTEs) and that are used for power and ground planes are disclosed. Fibrous materials (such as carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) with low CTEs are metallized to provide a resultant conductive material with a low CTE. Such fibers may be metallized in their individual state and then formed into a fabric, or these materials may be formed into a fabric and then metallized or a combination of both metallizations may be used. In addition, a graphite or carbon sheet may be metallized on one or both sides to provide a material that has a low CTE and high conductivity. These metallized, low CTE power and ground planes may be laminated with other planes/cores into a composite, or laminated into a core which is then laminated with other planes/cores into a composite. The resultant composite may be used for printed circuit boards (PCBs) or PCBs used as laminate chip carriers.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate.

Abstract: A multilayer resin wiring board includes a metal core substrate having a first main surface and a second main surface; a plurality of wiring layers located on the first and second main surfaces of the metal core substrate; a plurality of insulating resin layers, each intervening between the metal core substrate and the wiring layers and between the metal core substrate and the wiring layers and between the wiring layers; and a via formed on the wall of a through hole for connection to the metal core substrate extending through the insulating resin layers and the metal core substrate so as to establish electrical conductivity to the metal core substrate. The metal core substrate has a thin portion which is thinner than the remaining portion of the metal core substrate. The through hole for connection to the metal core substrate is formed through the thin portion by laser machining.

Abstract: A printed wiring board (1) having a cavity (20) for mounting electronic parts therein and a method for manufacturing thereof, comprising: an upper wiring substrate (1A) having flat surfaces on both sides; a lower plate body (1B) being fixed on a reverse side surface of the upper wiring substrate, and being formed with the cavity (20) in a part thereof, for receiving an electronic part (30) within an inside thereof; conductor layers (3) provided on both side surfaces of the upper wiring substrate for mounting electronic parts thereon, by forming plated through-holes (7) or flat through-holes (7′), in particular within a region of the cavity on the reverse side surface thereof; and external electrodes (5) formed on side-end surface or on a lower-end surface of the printed wiring board, wherein at least an electronic part, for example, hybrid IC, chip-like parts, functional parts, such as SAW filter, sensor parts, etc.

Abstract: Fine pitch area array packaging is achieved using a via-in-pad design within the area array attach portion of a printed circuit board (PCB). The limitation of the design is the wicking action, whereby solder applied to the capture pad contact surface is depleted by capillary action into the via hole when reflowed, causing insufficient solder to be present at the contact surface to effect reliable and repeatable electrical connections. In one implementation, an initial application of solder is applied to plug the via hole with a material having a higher final melting temperature than eutectic solder, thereby providing a stable plug. This plug is formed by the initial solder application that may be either a eutectic solder containing a third metal that forms intermetallic compounds, when reflowed, that elevate the liquidus temperature or a solder having a different formulation with an inherent higher melting temperature.

Abstract: The invention provides a printed-wiring board that is capable of preventing the lift-off phenomenon without changing the related process for fabricating related printed-wiring boards. A printed-wiring board of the present invention has the structure in which land portions are formed on both sides (front side and back side) of a board, a through hole is formed through the board, and an electrically conducting layer is formed on the inside peripheral surface of the through hole by means of plating to connect between the above-mentioned land portions of a wiring pattern, wherein the entire surface of the land part including the opening circumference of the through hole is covered with an insulating layer that covers the other part of the wiring pattern on the component side and on the other hand the land part is not covered with an insulating layer and remains exposed on the soldering side.

Abstract: A printed circuit board includes a plurality of dielectric substrates. Each of the dielectric substrates includes a first and a second surface and has a first conductive layer formed on the first surface of the respective dielectric substrate. A first pattern of lands is formed in the conductive layer of at least two of the dielectric substrates. The pattern of lands of each dielectric substrate is substantially the same. An opening is formed through each of the lands to expose the respective dielectric substrate. Each of the openings in a respective pattern of lands has a diameter different than at least a portion of the other openings in the same pattern. The plurality of dielectric substrates are laminated in stacked relationship.

Abstract: A conductive feed-through providing a conductive path through a dielectric body while maintaining differences in pressure between volumes separated by the dielectric body. A conductive feed-through of the present invention employs a hollow conductive tube created by first drilling a bore through the dielectric material. A first electrode is used to cover one end of the bore, and a vacuum-tight seal is formed around this first electrode. A second electrode is attached to the dielectric body at the other end of the bore. The inside surface of the bore is then coated with an electrically conductive material, and the coating provides a conductive path between the first electrode and the second electrode. In an alternative embodiment, the electrically conductive material coating is deposited such that it extends over the surface of the dielectric body so as to function as an electrode as well.

Abstract: An improved robber or solder thieving pad, parallelogram shaped, significantly reduces solder bridging in wave soldered multi leaded through hole or surface mounted components in a printed circuit board for different wave settings. The component leads are either parallel or perpendicular to the solder wave during the soldering process. In one embodiment, the parallelogram shaped solder thieving pad is disposed contiguous or adjacent to the through hole. In another embodiment, the parallelogram shaped solder thieving pad is spaced from a thin annular ring surrounding the through-hole. In still another embodiment, the pad may be linked to the ring by a thin connecting bridge. Dimensions of the solder thieving pad vary according to the component lead size, spacing, and number of rows.

Abstract: A chip carrier constituted of an organic laminate which incorporates structure compensating for thermal deformation of the carrier. Moreover, disclosed is a method of counteracting the thermal deformations encountered by chip carriers, especially during solder reflow, which is predicated on the uniformly, equidistant positioning of metal-plated through-holes (PTH) formed in the chip carrier relative to contact pads. A plurality of plated through-holes (PTH) are positioned equidistantly relative to contact (BGA) pads on a surface of a substrate which is constituted of an organic laminate material, so as to be able to control both in-plane and out-of-plane thermal deformations in the chip carrier material which may be occasioned in a solder reflow furnace or oven.

Abstract: A method of, and device (10) for, connecting a plurality of flexible printed circuits (12) each comprising a layer (14) of electrically insulating material and a layer (16) of electrically conducting material. The method including the steps of forming a hole (18) through each flexible printed circuit; positioning first and second substantially rigid plates (20,22) of electrically insulating material on either side of the flexible printed circuits with the holes in the flexible printed circuits aligned with a corresponding hole (26,28) in each plate; extending a rivet (24) of electrically conducting material through the aligned holes to electrically connect with the layers of electrically conducting material on the flexible printed circuits; and enlarging the ends (30,32) of the rivet to secure the flexible printed circuits between the plates. Provides an improved electrical and mechanical connection between FPCs.

Abstract: A method for laser drilling blind vias at multiple depths in a multilayer panel comprising forming a panel having a plurality of conductive layers and a plurality of dielectric layers interposed therebetween, a first relief in the first conductive layer, a second relief in a second conductive layer, and a blind pin in the third conductive layer, the first and second reliefs and blind pin being aligned. The panel is irradiated, laser energy passing through the first and second reliefs to remove material from the first and second dielectric layers and then plated, thereby forming a blind via from the first to third conductive layers through the second conductive layer.

Abstract: A routing technique for improving device reliability by selectively depopulating solder balls (12) (and their respective solder ball pads (34), vias (32) and traces or lines (30)) from a conventional foot print of a ball grid array (BGA) package, and a BGA package so modified. The routing technique uses the gap resulting from the depopulated solder balls as additional space for routing traces or lines from solder ball pads to an exterior surface of a substrate (14) upon which a semiconductor die (20) is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls on ever shrinking packages, thereby increasing device reliability.

Abstract: An electronic element is mounted on a resin wiring substrate and a cover member is bonded to the wiring substrate so as to cover the electronic element and constitute an encapsulation region. The encapsulation region houses the electronic element and has a cavity inside. A side electrode is formed of an electronically conductive through groove provided in a cover-member-bonding surface on the wiring substrate. A plating layer inside the electrically conductive through groove includes at least two metal layers including an Au plating layer and a Cu plating layer. The plating layer has conductors connected to circumferential peripheries of the electrically conductive through groove on upper and lower surfaces of the wiring substrate. Only the Cu plating layer is formed on the conductor on the upper surface of the wiring substrate to improve the reliability of bonding.

Abstract: A “Gatling gun” via to interconnect circuitry from a first side of a substrate or printed circuit board, to a second side of the substrate or board. The present via structure comprises a center conductor via surrounded by a plurality of ground vias. The plurality of ground vias shield the center conductor via, thus providing electrical isolation for the conductor via from the rest of the circuitry. In one embodiment, the conductor via is electrically connected to a conductive pattern on the substrate by a wire bond.

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact has a central axis normal to the surface and a peripheral portion adapted to expand radially outwardly from the central axis responsive to a force applied by a pad on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts expand radially and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by conductive bonding material carried on the contacts themselves.

Abstract: A semiconductor package is present along with an associated method. The package comprises a substrate with a top surface and a bottom surface, the substrate having a plurality of electrically conductive vias extending from the top surface of the substrate to the bottom surface of the substrate. A semiconductor device having an active surface, the active surface having a plurality of bonding pads, is attached to the substrate by an adhesive that bas holes that align with the vias. The vias are also aligned with the bonding pads. Solder serves to electrically and mechanically couple each of the bonding pads with a corresponding via. Each of the vias, in turn, is coupled to a solder ball formed on the bottom of the substrate.

Abstract: A mechanical-laser structure on a printed circuit board and a carrier. A method for fabricating the mechanical-laser structure includes the following steps. A substrate is provided. A first through hole is formed in the substrate by mechanical drilling An epoxy plug is formed within the first through hole. A conductive layer is formed on the substrate by compression. The conductive layer is patterned to form conducting wires and exposes the epoxy plug. A micro via is formed within the epoxy plug by laser drilling.

Abstract: A universal design of a multiple layer printed circuit board incorporates a series of routing vias interconnecting the various layers. The routing vias are connected to conductive traces in the internal trace layers by internal junctions. The internal junctions are located on the via so that internal junctions may be selectively severed by means of a laser or high pressure water cutting system or other fine line cutting tool or mechanism to customize the circuit design for a particular semiconductor device or integrated circuit.

Abstract: A chip-sized semiconductor device includes a semiconductor element having a plurality of electrodes and a plurality of connecting pads electrically connected to the respective electrodes. A connecting board includes a base substrate having a first surface and a second surface, a plurality of connecting holes extending from the first surface to the second surface, a plurality of lands formed on the first surface to close the respective connecting holes, the lands being arranged in conformity with positions of the connecting pads of the semiconductor element, each of the connecting pads having a surface area smaller than that of the land. The semiconductor element is mounted on the connecting board in such a manner that the connecting pads of the semiconductor element are electrically connected to the respective lands of the connecting board by means of a plurality of bumps, respectively.

Abstract: A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.

Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact has a central axis normal to the surface and a peripheral portion adapted to expand radially outwardly from the central axis responsive to a force applied by a pad on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts expand radially and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by conductive bonding material carried on the contacts themselves.

Abstract: A circuit design is logically partitioned into a plurality of blocks. As a first hierarchial assembly level, the blocks are fabricated as individual submodules each including at least one electronic component with component connection pads on a top surface, and a first interconnect structure including at least one interconnect layer bonded to the top surfaces, and interconnecting selected ones of the component connection pads. Submodule connection pads are provided on upper surfaces of the submodules. As a second hierarchial assembly level, a second interconnect structure is bonded to the upper surfaces and interconnects selected ones of the submodule connection pads.