Termination Post Patents (Class 174/267)
  • Patent number: 10818650
    Abstract: The semiconductor module includes a semiconductor chip and a semiconductor chip. The semiconductor chip includes an optical device such as an optical waveguide, an optical receiver, and a grating coupler, and a wiring formed over the optical device. The semiconductor chip includes a semiconductor element such as a MISFET formed in the semiconductor substrate, and a wiring formed over the semiconductor element. a top surface of the semiconductor chip is laminated to a top surface of the semiconductor chip such that the wirings are in direct contact with each other. In the semiconductor substrate, a through hole having a circular shape in plan view is formed, in the through hole, an insulating film is formed as a cladding layer, and the semiconductor substrate surrounded by the through hole constitutes an optical waveguide.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: October 27, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 10818586
    Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first redistribution structure, a first adhesive layer and a first connecting component. The substrate includes a first conductor on a first surface thereof. The first redistribution structure is disposed over the substrate. The first adhesive layer is disposed between the substrate and the first redistribution structure. The first connecting component is electrically connected with the first conductor, penetrates through the first adhesive layer into the first redistribution structure, and electrically connects the substrate to the first redistribution structure.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: October 27, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10813218
    Abstract: A resin multilayer board includes a substrate including a stack of resin layers, and a first metal pin including a first end portion exposed at a first main surface of the substrate and penetrating through at least one of the resin layers in a thickness direction, wherein a gap is provided at a portion of an interface between a lateral side of the first metal pin and the resin layer.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: October 20, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Kasuya, Yusuke Kamitsubo
  • Patent number: 10798828
    Abstract: A method of fabricating a circuit board structure is provided. The method includes providing a core substrate; forming an insulation layer on the core substrate; forming a patterned metal layer on the insulation layer, wherein the patterned metal layer includes a wiring layer and a pad; forming a first metal pillar on the pad, wherein the first metal pillar has a top surface; and forming a first solder resist layer on the patterned metal layer and the first metal pillar, wherein the first solder resist layer has a first opening exposing the first metal pillar, and the first opening has a bottom surface, wherein the top surface of the metal pillar is higher than or equal to the bottom surface of the first opening.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 6, 2020
    Assignee: NAN YA PRINTED CIRCUIT BORED CORPORATION
    Inventor: Hsien-Chieh Lin
  • Patent number: 10734345
    Abstract: A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien Ling Hwang, Yeong-Jyh Lin
  • Patent number: 10455699
    Abstract: A multilayer ceramic substrate includes: a plurality of ceramic layers 300a, 300b stacked together; a via hole 400a, 400b provided in each of the plurality of ceramic layers, the via holes of the plurality of ceramic layers being connected together in a layer stacking direction of the plurality of ceramic layers; a via wire 406a, 406b including an electrical conductor filled into each of the via holes; a first conductor 404a, 404b provided on an upper surface of at least one of the plurality of ceramic layers, the first conductor having an annular or partially annular shape surrounding the via wire; and a second conductor 403a, 403b including a first portion and a second portion, the first portion being located outside the first conductor on the upper surface of the at least one ceramic layer, the second portion overlying the first conductor, and an inner rim of the second portion being located outside an inner rim of the first conductor, wherein a thickness of the first conductor 404a, 404b is greater than a
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: October 22, 2019
    Assignee: HITACHI METALS, LTD.
    Inventor: Kenji Hayashi
  • Patent number: 10431920
    Abstract: An electronic device socket includes a barrel having a lumen extending therethrough. The barrel includes a proximal barrel portion having a first outer diameter; a tapering region extending distally from the proximal barrel portion, the tapering region extending both distally and radially inward towards a central axis of the barrel; a plurality of fingers extending distally from the tapering region, the plurality of fingers are all parallel to one another and the central axis; and a dimple contact area extending from each of the plurality of fingers extending radially inward and distally. The barrel is configured to make full contact with an electronic pin only at the dimple contact area.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 1, 2019
    Inventor: John O. Tate
  • Patent number: 10333235
    Abstract: This invention can be used as mini-micro-switching, up to macro switching. An electronic module having several input copper circuit traces, and several output copper traces, or wires, with some traces having disconnects, consisting of drilled holes, which can be bridged by conductive fasteners. This invention is also solving switching of differing functions both in the industry, and after that the product is in the market and the customer requests switching options. Selecting a switching options can be accomplished on a module, by first remove a conductive fastener from one position and attach the fastener in a second position on copper traces. Where the fastener is removed and not re-inserted, an open circuit trace occurs. Thereby accomplishing: selecting, reversing, or switching of one, or of a multiple of circuits.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: June 25, 2019
    Inventor: Sten R. Gerfast
  • Patent number: 10249967
    Abstract: An electronic device connected to a wire is provided, including a printed circuit board having a hole, a hollow tube, a plurality of blades separated from each other, and a solder, wherein the wire in inserted into the hollow tube and electrically connected to the printed circuit board. The hollow tube is extended through the hole. The solder is connected to the blades and the printed circuit board. The blades are connected to the hollow tube, and a reflex angle is formed between the inner wall of the hollow tube and each of the blades.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 2, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Shang-Yu Li, Hung-Chi Chen, Do Chen, Ching-Ho Chou
  • Patent number: 10224660
    Abstract: A circuit board disclosed herein includes a threaded receptor, one or more alignment holes, and one or more pads. The threaded receptor is configured to receive a component with a threaded screw. Each of the one or more alignment holes are configured to receive an alignment pin located on the component. Each of the one or more pads are configured to electrically connect to a pogo pin on the component.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: March 5, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Kanth Kurumaddali
  • Patent number: 10212810
    Abstract: An ink layer of an electrically conductive ink is formed on a sheet-like base and then the base is bent-deformed before the ink layer is cured, followed by curing the ink layer, thereby forming wiring. The ink layer is pliable during the bending deformation of the base, preventing breakage of the ink layer associated with the bending deformation of the base, and preventing damage to the wiring even when the wiring is finely formed.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: February 19, 2019
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Takanori Ohara, Kyoichi Yamamoto, Kentaro Kubota, Kenji Hayashi
  • Patent number: 10157753
    Abstract: A wiring board (1) includes an insulating substrate (11) having a cutout (12) opened in a main surface and a side surface of the insulating substrate (11), and an inner electrode (13) formed on an inner surface of the cutout (12). The inner electrode (13) includes a plurality of metal layers. The inner electrode (13) includes, as an intermediate layer, at least one metal layer (17b) selected from the group consisting of a nickel layer, a chromium layer, a platinum layer, and a titanium layer, and includes a gold layer as an outermost layer (17a). The metal layer (17b) is exposed at an outer edge portion of the inner electrode (13).
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 18, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Yukio Morita, Kenji Sugimoto
  • Patent number: 10111340
    Abstract: Provided are a conducting substrate and a method for preparing the same. The method for preparing the conducting substrate according to an embodiment of the present application includes a) providing a substrate comprising a conducting layer; b) forming a metal layer on the entire surface of the substrate comprising the conducting layer; c) forming an insulating layer pattern on the metal layer; d) forming a metal layer pattern by over-etching the metal layer by using the insulating layer pattern as a mask; and e) reforming the insulating layer pattern.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: October 23, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Minsoo Kang, Hyunsik Park, Young Kyun Moon
  • Patent number: 10091891
    Abstract: The present disclosure provides a novel apparatus and method for printing circuitry that can dispense conducting traces, insulating traces, solder paste, and other materials onto a substrate material in a manner that allows for convenient prototyping of printed circuit boards.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: October 2, 2018
    Assignee: Voltera Inc.
    Inventors: Katarina Ilic, Alroy Almeida, James Pickard, Jesus Zozaya, Matthew Ewertowski
  • Patent number: 10068889
    Abstract: An electronic system without using solder balls between electrical components, and without using interposer between chips and package substrate, without using a discrete system board for the chip package to mount. A chip is wrapped by molding material, a first redistribution circuitry is built on a bottom side of the molding material; a second redistribution circuitry is built on a bottom side of the first redistribution circuitry. A third redistribution circuitry is built on a bottom side of the second redistribution circuitry. Plated metal vias are configured between each two of the electrical components.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: September 4, 2018
    Inventor: Dyi-Chung Hu
  • Patent number: 10056345
    Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang
  • Patent number: 9841438
    Abstract: It is an object of the invention to provide a guide plate for a probe card with fine through holes at tight pitches and with increased strength. The guide plate 100 for a probe card includes a metal base 110; first insulation layers 120; and metal layers 130. The metal base 110 has a plurality of through holes 111 to receive probes therethrough, and inner walls of the through holes 111. The first insulation layers 120 are of tuboid shape and provided on the respective inner walls of the through holes 111 of the metal base 110. The metal layers 130 are provided on the first insulation layers 120.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: December 12, 2017
    Assignee: Japan Electronic Materials Corporation
    Inventors: Teppei Kimura, Liwen Fan
  • Patent number: 9837347
    Abstract: A coaxial copper pillar for signal transmission with signal shield is disclosed so that signal integrity for the signal passes transmission is maintained. One embodiment shows at least one coaxial copper pillar is made as a terminal connector for a chip package, the coaxial copper pillars are made adaptive for electrically coupling the chip package to a mother board.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 5, 2017
    Inventor: Dyi-Chung Hu
  • Patent number: 9673148
    Abstract: An electronic system without using solder balls between electrical components, and without using interposer between chips and package substrate, without using a discrete system board for the chip package to mount. A chip is wrapped by molding material, a first redistribution circuitry is built on a bottom side of the molding material; a second redistribution circuitry is built on a bottom side of the first redistribution circuitry. A third redistribution circuitry is built on a bottom side of the second redistribution circuitry. Plated metal vias are configured between each two of the electrical components.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: June 6, 2017
    Inventor: Dyi-Chung Hu
  • Patent number: 9502367
    Abstract: A semiconductor device according to an embodiment includes a semiconductor chip, a cap disposed to face the semiconductor chip, and having a through-hole electrode arranged in a through hole, and a bump electrode provided between the semiconductor chip and the cap, wherein the bump electrode is in a protruding shape connecting the semiconductor chip and the through-hole electrode, and wherein at least a portion of the bump electrode is included in the through-hole electrode, and electrically connected thereto, so that the adhesive performance between the cap and the bump electrode can be increased.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: November 22, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Onozuka, Hiroshi Yamada, Nobuto Managaki, Tadahiro Sasaki
  • Patent number: 9484487
    Abstract: A method for fabricating thin crystalline photovoltaic cells is disclosed. In one aspect, the method includes: forming a weakening layer in a surface portion of a semiconductor substrate; epitaxially growing a stack of semiconductor layers on the substrate for forming an active layer of the photovoltaic cell, the stack having a first thermal coefficient of expansion; providing on the stack patterned contact layer for forming electrical contacts of the photovoltaic cell, the patterned contact layer having a second thermal coefficient of expansion different from the first thermal coefficient of expansion. The process of providing a patterned contact layer simultaneously induces a tensile stress in the weakening layer, resulting in a lift-off from the substrate of a structure including the stack of semiconductor layers and the patterned contact layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 1, 2016
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventors: Alex Masolin, Maria Recaman Payo
  • Patent number: 9431719
    Abstract: The invention relates to a contact pin, comprising an angular end section, which is in particular designed for connecting to a wire or plug, wherein the angular end section has an angular cross-section. According to the invention, the contact pin has a round end section that is opposite the angular end section and that is designed for soldering to a circuit board. The round end section has a cross-section that is round at least in some sections of the circumference.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 30, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Joachim Braunger, Ulrich Becker, Richard Gueckel, Markus Kroeckel
  • Patent number: 9412805
    Abstract: An integrated circuit includes a substrate having a surface and an inductor disposed over the surface of the substrate. The inductor includes a first conductive line disposed over the surface and first conductive structures disposed over and electrically coupled with the first conductive line. The inductor includes second conductive structures disposed over and electrically coupled with the first conductive structures. The inductor includes a second conductive line disposed over and electrically coupled with the second conductive structures. The inductor includes third conductive structures disposed over and electrically coupled with the first conductive line and at least one fourth conductive structure disposed over and electrically coupled with the third conductive structures. The inductor includes a third conductive line disposed over and electrically coupled with the at least one fourth conductive structure, the third conductive line extending substantially parallel to the second conductive line.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsiu-Ying Cho
  • Patent number: 9386710
    Abstract: The invention relates to a method for producing populated or unpopulated circuit boards or individual circuits as individual panels (2) from a complete panel (1) having a circuit board base material (4), wherein the particular individual panel (2) is removed from the complete panel (1) using a laser, wherein the individual panel is fastened to the complete panel (1) by means of metal connections (3) before the individual panel (2) is removed, the circuit board base material (4) is removed except for the metal connections (3), and the individual panels (2) are separated from, in particular pressed out of, the complete panel (1) after the circuit board base material (4) has been removed.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: July 5, 2016
    Assignee: OTTO BOCK HEALTHCARE PRODUCTS GMBH
    Inventor: Marcus Eder
  • Patent number: 9362204
    Abstract: A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: June 7, 2016
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Hiroaki Sato
  • Patent number: 9297833
    Abstract: The present invention is a rhodium alloy suitable for wire for a probe pin, the rhodium alloy comprising 30 to 150 ppm of Fe, 80 to 350 ppm of Ir and 100 to 300 ppm of Pt as additive elements, and the balance being Rh. A probe pin composed of the material maintains processability of rhodium, has stable contact resistance even at a low contact pressure, and has excellent strength and antifouling properties, and therefore, can be used in a stable manner for a long period.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: March 29, 2016
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventor: Tomokazu Obata
  • Patent number: 9257369
    Abstract: The present invention is directed to a semiconductor device including a semiconductor substrate, a through hole penetrating the semiconductor substrate, a base film covering the through hole, a conductive layer disposed on the base film, an insulating film formed on the side wall of the through hole, and a conductive material embedded in the through hole via the insulating film, in which the base film has a stepped portion formed by an opening pattern that selectively exposes the conductive layer therethrough into the through hole, and in which the conductive material is connected electrically to the conductive layer through the opening pattern.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: February 9, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Toshiro Mitsuhashi
  • Patent number: 9111755
    Abstract: A semiconductor device comprises an integrated circuit including a wire bond pad and a passivation material, and a first gap between a first selected portion of the wire bond pad and the passivation material. The first gap is positioned to contain at least a first portion of a splash of the wire bond pad formed during a wire bond process.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: August 18, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tu-Anh N. Tran, David B. Clegg, Sohrab Safai
  • Patent number: 9103536
    Abstract: A printed circuit board (1), having a front side (2) for population with at least one semiconductor light source (4) and having at least one securing element (6) accessible via a rear side (3), wherein the at least one securing element (6) is embodied as an electrical through-conduction element for at least one of the semiconductor light sources.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: August 11, 2015
    Assignee: OSRAM GmbH
    Inventors: Peter Sachsenweger, Yuli Chen, Zhenjian Liang, Xuefeng Wang, Junhua Zeng
  • Patent number: 9105989
    Abstract: A connection structure includes a column electrode; a first connecting portion connected to one end of the column electrode; and a second connecting portion connected to another end of the column electrode via solder, wherein a height of the column electrode is a width of the first connecting portion or greater.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: August 11, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kei Murayama, Shinji Nakazawa, Miki Suzuki
  • Patent number: 9040844
    Abstract: A mounting board having a plurality of terminals. The ends of each of the plurality of terminals are inserted into and soldered to through-holes positioned in a printed board, and the terminals are mounted on the printed board. A plurality of pedestals are disposed on one side of the printed board. The pedestals support the terminals. The pedestals are integrally coupled to one another through deformable coupling portions. Mutual displacements among the pedestals are allowed by the coupling portions.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: May 26, 2015
    Assignee: SUMITOMO WIRING SYSTEMS, LTD.
    Inventor: Hideki Goto
  • Publication number: 20150136468
    Abstract: Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Inventors: Henry Meyer Daghighian, Steven C. Bird, YongShan Zhang
  • Publication number: 20150116955
    Abstract: An engine control unit including a substantially rectangular printed circuit board in which a microcontroller is mounted. The printed circuit board includes a connector portion in which connection terminals are provided to be arranged in one side edge portion along the longitudinal direction thereof. The connection terminals of the connector portion include connection terminals for input on one side in the longitudinal direction and connection terminals for output on the other side with respect to a setting position. A microcontroller is disposed at substantially the center portion of the printed circuit board in the longitudinal direction thereof. An electronic component as an input interface circuit is disposed on the one side in the longitudinal direction, and an electronic component as an output interface circuit is disposed on the other side.
    Type: Application
    Filed: November 26, 2014
    Publication date: April 30, 2015
    Applicant: MIKUNI CORPORATION
    Inventors: Ichiro TSUJI, Ryuichi YAMAZAKI, Yoshitaka KOGA
  • Publication number: 20150096798
    Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 9, 2015
    Applicant: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Publication number: 20150041208
    Abstract: Components and methods of making the same are disclosed herein. In one embodiment, a method of forming a component comprises forming metal anchoring elements at a first surface of a support element having first and second oppositely facing surfaces, the support element having a thickness extending in a first direction between the first and second surfaces, wherein each anchoring element has a downwardly facing overhang surface; and then forming posts having first ends proximate the first surface and second ends disposed above the respective first ends and above the first surface, wherein a laterally extending portion of each post contacts at least a first area of the overhang surface of the respective anchoring element and extends downwardly therefrom, and the overhang surface of the anchoring element resists axial and shear forces applied to the posts at positions above the anchoring elements.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Applicant: INVENSAS CORPORATION
    Inventors: Liang Wang, Ilyas Mohammed, Belgacem Haba
  • Patent number: 8952258
    Abstract: A method, and structures for implementing enhanced interconnects for high conductivity applications. An interconnect structure includes an electrically conductive interconnect member having a predefined shape with spaced apart end portions extending between a first plane and a second plane. A winded graphene ribbon is carried around the electrically conductive interconnect member, providing increased electrical current carrying capability and increased thermal conductivity.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark D. Plucinski, Arvind K. Sinha, Thomas S. Thompson
  • Patent number: 8952271
    Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Limited
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Seiki Sakuyama, Toshiya Akamatsu
  • Patent number: 8943684
    Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes simultaneously extruding a plurality of materials in the cross-sectional shape of the Z-directed component to form an extruded object with the plurality of materials arranged relative to each other in their operative positions for the Z-directed component. The extrusion of a first portion of at least one of the materials in the extruded object is staggered relative to the extrusion of a second portion of the at least one of the materials in the extruded object. At least a segment of the extruded object is fired. The fired segment forms the Z-directed component insertable into a mounting hole in a printed circuit board.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: February 3, 2015
    Assignee: Lexmark International, Inc.
    Inventor: Keith Bryan Hardin
  • Patent number: 8942002
    Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to a thin interposer disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can insulate the components from one another and also couple signals between the components on the first and second layers. In one embodiment, the components in the first and second layers are passive components.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: January 27, 2015
    Inventors: Shawn X. Arnold, Douglas P. Kidd, Sean A. Mayo, Scott P. Mullins, Dennis R. Pyper, Jeffrey M. Thoma, Kenyu Tojima
  • Patent number: 8927877
    Abstract: Disclosed herein is a system and method for mounting packages by forming one or more wire loop interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a first substrate. A first and second stud ball may each have at least one flat surface be disposed on a single mounting pad, and a wire having a bend region and forming a loop may be disposed between the stud balls. The stud balls may be formed from a deformed mouthing node formed on a wire. The loop may be mounted on a mounting pad on a first substrate and a second substrate may be mounted on the loop via a conductive material such as solder.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-An Shen, Yung Ching Chen, Ming-Chung Sung, Chih-Hang Tung, Chien-Hsun Lee, Da-Yuan Shih
  • Patent number: 8907354
    Abstract: The present disclosure relates to an optoelectronic device, in particular to an arrangement for contacting an optoelectronic device. The optoelectronic device (200) includes an elastic electrode (208). A method for forming the elastic electrode (208) is described.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andrew Ingle
  • Patent number: 8884167
    Abstract: A printed circuit board unit includes: a printed circuit board including a through hole including first and second inner surfaces opposite to each other; a terminal pin including an insertion portion inserted into the through hole; solder filled into the through hole, and joining the printed circuit board with the terminal pin, wherein the insertion portion includes a base portion abutting the first inner surface, and a protruding portion including: a projection surface projecting from the base portion to the second inner surface and abutting the second inner surface; and a recess surface located at a rear side of the projection surface and spaced apart from the first inner surface, and a length of the protruding portion in a thickness direction of the printed circuit board is greater than a thickness of the printed circuit board.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: November 11, 2014
    Assignee: Shinano Kenshi Co., Ltd.
    Inventors: Kazuya Miyasaka, Kouji Kobayashi, Akihito Fukuzawa
  • Patent number: 8878078
    Abstract: A printed wiring board including solder pads excellent in frequency characteristic is provided. To do so, each solder pad 73 is formed by providing a single tin layer 74 on a conductor circuit 158 or a via 160. Therefore, a signal propagation rate can be increased, as compared with a printed wiring board of the prior art on which two metal layers are formed. In addition, due to lack of nickel layers, manufacturing cost can be decreased and electric characteristics can be enhanced.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: November 4, 2014
    Assignee: Ibiden Co., Ltd.
    Inventor: Toru Nakai
  • Publication number: 20140318849
    Abstract: A portion of a flat conductor is exposed from an insulating layer covering at least one of surfaces of the flat conductor. A terminal includes a bottom plate on which the exposed portion of the flat conductor is provided, and crimp claws which are raised at two side edges of the bottom plate so that the exposed portion is disposed therebetween. The exposed portion is folded so as to define a bottom layer which faces the bottom plate and a top layer which faces opposite to the bottom plate. The top layer is configured to be plastically deformed so as to fill a gap between the top layer and inner surfaces of the crimp claws when the crimp claws are crimped onto the top layer, so that the bottom layer is in surface contact with the bottom plate.
    Type: Application
    Filed: July 9, 2014
    Publication date: October 30, 2014
    Inventor: Naoki Ito
  • Patent number: 8859077
    Abstract: A plurality of openings are formed in a resin insulation layer on a bottom surface side of a wiring laminate portion which constitutes a multilayer wiring substrate. A plurality of motherboard connection terminals are disposed to correspond to the openings. The motherboard connection terminals are primarily comprised of a copper layer, and peripheral portions of terminal outer surfaces thereof are covered by the outermost resin insulation layer. A dissimilar metal layer made of at least one metal which is lower in etching rate than copper is formed between an inner main surface of the outermost resin insulation layer and peripheral portions of the terminal outer surfaces.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: October 14, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Shinnosuke Maeda, Tetsuo Suzuki, Satoshi Hirano
  • Publication number: 20140262460
    Abstract: A packaged microelectronic element includes connection component incorporating a dielectric layer (22) carrying traces (58) remote from an outer surface (26), posts (48) extending from the traces and projecting beyond the outer surface of the dielectric, and pads (30) exposed at the outer surface of the dielectric layer, the pads being connected to the posts by the traces. The dielectric element overlies the front surface of a microelectronic element, and contacts (74) exposed on the front surface of the microelectronic element are connected to the pads by elongated leads (76) such as wire bonds. Methods of making the connection component are also disclosed.
    Type: Application
    Filed: December 10, 2013
    Publication date: September 18, 2014
    Applicant: Tessera, Inc.
    Inventors: YOICHI KUBOTA, Tec-Gyu Kang, Jae Park, Belgacem Haba
  • Publication number: 20140262470
    Abstract: A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad.
    Type: Application
    Filed: June 25, 2013
    Publication date: September 18, 2014
    Inventors: Yi-Li Hsiao, Su-Chun Yang, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Patent number: 8797760
    Abstract: A substrate includes: a base; and a plurality of bonding terminals arranged on at least one surface of the base, wherein the plurality of bonding terminals include a first bonding terminal and a second bonding terminal, the first bonding terminal and the second bonding terminal include, in plan view of the base, a circle contacting portion extending along the circumference of a circle tangent to the first bonding terminal and the second bonding terminal, all of the plurality of bonding terminals are arranged so as not to protrude from an area including the circle and the inside thereof, and the circle contacting portion includes at least a first circle contacting portion disposed in the first bonding terminal and a second circle contacting portion disposed in the second bonding terminal.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Kenji Sato
  • Patent number: 8796559
    Abstract: Disclosed herein are a lead pin for a printed circuit board and a printed circuit board using the same. The lead pin for a printed circuit board includes: a connection pin; and a pin head part formed at one end portion of the connection pin and including a protrusion, the diameter thereof being formed to be increasingly small based on a surface contacting the connection pin and the outer peripheral surface thereof being provided with a protrusion-shaped or depression-shaped band, whereby it forms a protrusion-shaped band or a depression-shaped band on the pin head part of the lead pin to increase a contacting area with the solder, thereby improving an adhesion between the lead pin and the printed circuit board.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Yong Ho Baek, Seok Hyun Park, Ki Taek Lee
  • Patent number: 8785789
    Abstract: Disclosed herein are a printed circuit board (PCB) and a method for manufacturing the same. The PCB includes a base substrate, a circuit layer formed on the base substrate and including a connection pad, a solder resist layer formed on an upper portion of the base substrate and having an opening exposing the connection pad, a metal post formed on upper portions of the connection pad and the solder resist layer and having a plurality of diameters, and a seed layer formed on the upper portion of the solder resist layer and inner walls of the opening along an interface of the metal post.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: July 22, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hueng Jae Oh, Boo Yang Jung, Dae Young Lee, Jin Won Choi