Termination Post Patents (Class 174/267)
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Patent number: 6115254Abstract: A high density vertical surface mount package and thermal carrier therefor including a heat sink.Type: GrantFiled: November 16, 1999Date of Patent: September 5, 2000Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Jerry M. Brooks, Walter L. Moden
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Patent number: 6054652Abstract: The thin-film multi-layer substrate includes an insulating substrate base plate, and a thin-film structure including a plurality of conducting layers and a plurality of insulating layers formed on the substrate base plate. A via structure is formed in the thin-film structure and connected to one of the conducting layers of the thin-layer structure. Pins are connected to the via structure, such that the bottom of the via structure is directly laminated on the substrate base plate, and the pins are secured onto the via structure.Type: GrantFiled: October 10, 1997Date of Patent: April 25, 2000Assignee: Fujitsu LimitedInventors: Kiyokazu Moriizumi, Shunichi Kikuchi, Kazuhiro Nitta, Naomi Fukunaga, Mitsuo Suehiro
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Patent number: 6049039Abstract: A printed circuit terminal includes a main terminal body and an integrally formed fixing portion that is coaxial with the terminal body for mounting the terminal to a printed circuit base member. A frusto-conical flange is integrally connected between the body and the fixing portion and has a peripheral surface located in radially outward relation to the body and the fixing portion. The flange includes two surface portions. The first surface portion is adapted to contact and extend from the base member for receiving solder deposited in electrical contact with the base member. A second surface portion is axially adjacent to the first portion and exposes a different surface material than the first portion in order to restrain solder adhesion to the second surface portion.Type: GrantFiled: November 24, 1997Date of Patent: April 11, 2000Assignee: Star Micronics Co., Ltd.Inventor: Isao Fushimi
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Patent number: 6018285Abstract: A wire-wound component to be mounted on a printed circuit board. The wire-wound component is formed by winding a wire on the body of the wire-wound component and by winding both end portions of the wire on terminals. The terminals and the body of the wire-wound component are formed as one unit by molding same from a heat-resistant resin material. The molded terminals, on which both end portions of the wire are wound, are inserted into the printed circuit board, and then connected to a circuit pattern on the printed circuit board by soldering.Type: GrantFiled: January 21, 1997Date of Patent: January 25, 2000Assignee: Funai Electric Co., Ltd.Inventor: Osamu Maeda
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Patent number: 6012223Abstract: A process for mounting a surface-mount component(12), such as a stick-leaded device, to a circuit board (10) having a pair of plated through-holes and at least one additional through-hole (20), each of which extends through the circuit board (10). The leads (16) of the component (12) are then inserted into the plated through-holes so as to position the component (12) on a first side of the circuit board (10), after which a material (14) is applied to the second (opposite) side of the circuit board (10) so that the material (14) flows through the second through-hole (20), contacts the component (12), and bonds the component (12) to the first side of the circuit board (10). For this purpose, the material (14) preferably contacts the entire surface (18) of the component (12) facing a near surface region of the circuit board (10) and bonds the component surface (18) to the surface region.Type: GrantFiled: July 31, 1998Date of Patent: January 11, 2000Assignee: Delco Electronics Corp.Inventor: Lee R. Hinze
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Patent number: 6010342Abstract: A compression connector for interconnecting microelectronic circuit and cable assemblies, providing shielding and characteristic impedance control, is readily configurable for high-density multi-connector arrays. A first embodiment includes a loop of insulated wire that resides in a magnetically permeable, electrically non-conductive or electrically conductive housing. This wire loop can be affixed to the housing or can be floating and be longitudinally driven. The loop of insulated wire can have a range of insulation removed, from only exposing the extreme end of the wire loop or have the majority of the insulation removed at the loop. A second embodiment includes two contiguous, parallel wire segments that are bonded or welded together, with the contiguous, parallel wire segments used in lieu of the bare-wire loop configuration; this configuration can also be affixed to the housing or be floating and driven.Type: GrantFiled: March 20, 1998Date of Patent: January 4, 2000Inventor: Troy M. Watson
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Patent number: 6011222Abstract: A substrate for mounting an electronic part and a method for producing the same, which allows a conductive pin to be inserted and secured in a through hole without exerting any damage thereto. The substrate for mounting an electronic part is formed of a through hole piercing an insulating substrate and a conductive pin with its head inserted into the through hole. The head of the conductive pin is provided with a plurality of projections to its side wall, each projecting radially in 4 or more directions. Those projections form a plurality of pairs, each of which is extending in an opposite direction from an axial center of the head. Those projection pairs include a primary projection pair having a largest length and a secondary projection pair having a second largest length. The length of the primary projection pair is equal to or more than an inside diameter of the through hole.Type: GrantFiled: December 13, 1996Date of Patent: January 4, 2000Assignee: IBIDEN Co., Ltd.Inventors: Masataka Sekiya, Tsunehisa Takahashi, Akihiro Demura, Takuji Asai
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Patent number: 5945637Abstract: A terminal attachment structure includes a circuit assembly and a terminal attached to the circuit assembly. The circuit assembly has an insulating substrate and a circuit printed on the insulating substrate. The terminal is composed of a circuit-contact part, a connecting part to be connected with a mating terminal and a cradle part arranged between the circuit-contact part and the connecting part. When a force directing the insulating substrate is applied on the connecting part, the cradle part operates to receive the force. Accordingly, the circuit-contact part does not rise from the insulating substrate, so that tottering of the terminal against the circuit assembly can be prevented.Type: GrantFiled: March 21, 1997Date of Patent: August 31, 1999Assignee: Yazaki CorporationInventors: Makoto Katsumata, Toshiyuki Mori, Hitoshi Ushijima
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Patent number: 5918153Abstract: High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing.Type: GrantFiled: September 18, 1996Date of Patent: June 29, 1999Assignee: Sandia CorporationInventor: William P. Morgan
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Patent number: 5915753Abstract: A method of producing a high-density wiring board for mounting comprises the steps of providing an electroconductive metallic film on the main surface thereof with a photosensitive resist layer, subjecting the photosensitive resist layer to selective exposure to light and development thereby forming holes for selectively exposing the surface of the electroconductive metallic foil in the photosensitive resist layer, depositing an electroconductive metal by plating on the exposed surface of the electroconductive metallic foil thereby forming electroconductive bumps thereon, peeling off the remainder of the photosensitive resist layer, superposing an insulating polymer sheet on the electroconductive bump forming surface, pressing the resultant superposed layers so that the electroconductive bumps to pierce the polymer sheet in the direction of thickness thereof and allowing the leading end parts of the electroconductive bumps to emerge from the polymer sheet and give rise to connecting terminal parts, and selectType: GrantFiled: January 16, 1998Date of Patent: June 29, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Motomura, Osamu Shimada, Yoshitaka Fukuoka
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Patent number: 5890284Abstract: In aspect, the present invention is directed to a method of modifying a circuit board having at least one Ball Grid Array (BGA). The method includes removing the via portion of the BGA pad from the circuit board to sever the connection between the via and the circuit, attaching the pad connector to the circuit board, and connecting the pad connector to the circuit of the circuit board.Type: GrantFiled: November 25, 1997Date of Patent: April 6, 1999Assignee: International Business Machines CorporationInventors: Richard L. Chartrand, Wai-Mon Ma, Roger A. Stinemire
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Patent number: 5825633Abstract: A multi-board electronic assembly (10) includes a first substrate (12) and a second substrate (14) electrically connected by a spacer (16). The spacer (16) includes a first end (26) that is received in a first receptacle (18) on the first substrate (12) and a second end (28) that is received in a second receptacle (22) in the second substrate (14). The spacer (16) is formed generally of a nonconductive body (15) and includes ridges (60) and longitudinal channels (30) defined between the ridges (60). The ridges (60) are formed generally of a nonconductive material, and the spacer (16) includes a metallic strip (32) disposed within the channel (30). The metallic strip (32) forms a conductive path to connect the first circuit trace (20) to the second circuit trace (24) to form an electrically connected microelectronic assembly (10).Type: GrantFiled: November 5, 1996Date of Patent: October 20, 1998Assignee: Motorola, Inc.Inventors: C. Gregory Bujalski, Jeffrey M. Petsinger, Daniel T. Rooney
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Patent number: 5787581Abstract: A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool, which has features adapted to control the position of the lead.Type: GrantFiled: August 17, 1995Date of Patent: August 4, 1998Assignee: Tessera, Inc.Inventors: Thomas H. DiStefano, Gary W. Grube, Igor Y. Khandros, Gaetan Mathiew
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Patent number: 5755596Abstract: A compression connector assembly for interconnecting microelectronic circuit and cable assemblies, which provides shielding and characteristic impedance control, and is configurable in high-density multi-connector arrays. In a first embodiment, the connector includes a bare-wire loop contact element rigidly maintained within a cylindrical sleeve closely received within a cylindrical receptacle of a conductive housing. In a second embodiment, the connector includes a bare-wire loop contact element closely received within a cylindrical receptacle of an insulating housing. In a third embodiment, the connector includes a contact element formed from two bare-wire segments bonded together and disposed within a cylindrical sleeve closely received within a cylindrical receptacle of a conductive housing. In a fourth embodiment, the connector includes a contact element formed from two bare-wire segments bonded together and closely received within a cylindrical receptacle of an insulating housing.Type: GrantFiled: November 19, 1996Date of Patent: May 26, 1998Inventor: Troy M. Watson
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Patent number: 5737833Abstract: A method of producing a high-density wiring board for mounting comprises the steps of providing an electroconductive metallic film on the main surface thereof with a photosensitive resist layer, subjecting the photosensitive resist layer to selective exposure to light and development thereby forming holes for selectively exposing the surface of the electroconductive metallic foil in the photosensitive resist layer, depositing an electroconductive metal by plating on the exposed surface of the electroconductive metallic foil thereby forming electroconductive bumps thereon, peeling off the remainder of the photosensitive resist layer, superposing an insulating polymer sheet on the electroconductive bump forming surface, pressing the resultant superposed layers so that the electroconductive bumps to pierce the polymer sheet in the direction of thickness thereof and allowing the leading end parts of the electroconductive bumps to emerge from the polymer sheet and give rise to connecting terminal parts, and selectType: GrantFiled: October 5, 1995Date of Patent: April 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Motomura, Osamu Shimada, Yoshitaka Fukuoka
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Patent number: 5671125Abstract: Two flat packages (110, 111) are arranged to achieve a mirrored footprint by employing guides (100), which are positioned within a mounting aperature a printed circuit board. The flat packages include leads (120, 121) which extend from an edge of the flat package. A semiconductor chip is encapsulated by the flat packages.Type: GrantFiled: August 21, 1995Date of Patent: September 23, 1997Assignee: Texas Instruments IncorporatedInventors: Ernest Russell, Daniel Baudouin, James S. Wallace
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Patent number: 5468920Abstract: A printed circuit board is installable into a slot of a cardedge connector such that contacts of the connector ride along electrically conductive, raised pads of the card. Each pad includes frontal edge segments which are inclined generally rearwardly toward a center axis of the pad so that if any of the contacts are laterally offset with respect to the center axis of its respective pad during installation, the offset contact will be re-directed toward the center axis in response to making engagement with one of the frontal edge segments.Type: GrantFiled: July 22, 1994Date of Patent: November 21, 1995Assignee: Apple Computer, Inc.Inventor: Mark P. August
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Patent number: 5455390Abstract: A component for mounting semiconductor chips or other microelectronic units includes a flexible top sheet with an array of terminals on it, and with flexible leads extending downwardly from the terminals. A compliant dielectric support layer surrounds the leads, holding the lead tips in precise locations. The leads are desirably formed from wire such as gold wire, and have eutectic bonding alloy on their tips. The component can be laminated to a chip or other unit under heat and pressure to form a complete subassembly with no need for individual bonding to the contacts of the chip. The subassembly can be tested readily and provides compensation for thermal expansion.Type: GrantFiled: February 1, 1994Date of Patent: October 3, 1995Assignee: Tessera, Inc.Inventors: Thomas H. DiStefano, John W. Smith, Jr.
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Patent number: 5453583Abstract: A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping the bond pads into a relatively small (compared to the total area of the die) sub-area within an interior area (generally away from the periphery) of the die. By keeping the bond pad layout small (tightly grouped, or oriented along a single row, or axis), differential thermally induced displacements between the bond pads are minimized, or are controlled in one dimension. Further, the bond pads may be disposed in a small area near the center of thermal expansion (centroid) of the die or near a heat-producing circuit element to minimize absolute thermal displacements of individual bond pads from the centroid or the circuit element. Overlapping sub-area patterns may be used, and grouped bond pads may be used in conjunction with (including overlapping of) traditional die-periphery located bond pads.Type: GrantFiled: May 5, 1993Date of Patent: September 26, 1995Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
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Patent number: 5453580Abstract: A printed circuit board includes vibration areas where vibration sensitive components of an electrical circuit design fabricated on the printed circuit board are mechanically isolated from supporting circuitry. The present invention provides a printed circuit board with areas having an increased natural resonant frequency of vibration for the circuit board area where the vibration sensitive circuit is located. The printed circuit board comprises a number of slots, holes or other openings around the vibration sensitive circuitry. In addition, one or more circuit board conductive paths are provided for maintaining electrical conductivity between the isolated circuit and the supporting circuits.Type: GrantFiled: November 23, 1993Date of Patent: September 26, 1995Assignee: E-Systems, Inc.Inventors: Earnest A. Franke, Judd O. Sheets, Steven R. Crose
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Patent number: 5448016Abstract: A member having a shank is selectively coated with a material such as a metal by loosely sliding a washer made of a material such as a thermoplastic or thermosetting polymer onto the shank, securing the washer such that the washer is in intimate contact with the shank, and immersing at least a portion of the member into at least one coating bath so that a portion of the member is coated and the portion of the shank in contact with the washer is not coated. The member can be an input/output pin for an electronic device and the coating can be applied by methods such as electroless plating or electrolytic plating.Type: GrantFiled: July 20, 1994Date of Patent: September 5, 1995Assignee: International Business Machines CorporationInventors: Nunzio DiPaolo, Balaram Ghosal, Kim H. Ruffing
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Patent number: 5446247Abstract: An electrical contact and method for making an electrical contact allows a flat contact (404) to be formed early in the process of making an electronic device. The flat contact (404) is level with the remainder of the substrate (116) in which it is formed. The flat contact (404) does not interfere with any required subsequent process steps. The flat contact can be reflowed to form a ball contact (302) which protrudes above the top of the substrate (120) to which it is attached.Type: GrantFiled: November 19, 1993Date of Patent: August 29, 1995Assignee: Motorola, Inc.Inventors: Lubomir Cergel, Barry C. Johnson, John W. Stafford
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Patent number: 5442142Abstract: A large-current circuit board having a plurality of fasteners positioned and secured beforehand to the circuit board, and a plurality of busbars for electrically connecting the plurality of fasteners. Each of the plurality of busbars has a strip-like planar plate shape. Various ones of the plurality of fasteners may have the same or different distances from the surface of the circuit board. Specifically, the portions of the fasteners that are connected with the busbars may be at different heights so that plural busbars connecting the fasteners can cross each other at plural levels. A variety of fasteners and busbar securing boards may be used for electrically connectibly holding and securing the plurality of busbars with the plurality of fasteners on the circuit board.Type: GrantFiled: September 30, 1993Date of Patent: August 15, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Satoru Hayashi
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Patent number: 5442145Abstract: A terminal for an electric circuit device, comprises a copper core, a gold (Au) layer provided over the copper core, and a nickel (Ni) layer having the thickness of 1.5 .mu.m or less, provided under the gold (Au) layer. In another embodiment, the core is made of an alloy containing (Ni) and covered by a metallized surface layer made of copper.Type: GrantFiled: October 12, 1993Date of Patent: August 15, 1995Assignee: NGK Spark Plug Co., Ltd.Inventors: Ryuji Imai, Toshikatsu Takada
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Patent number: 5426266Abstract: A connection for mounting an IC die directly to a substrate includes circuit runs deposited on the substrate with bond pad portions having metallization patterns forming ridges and cutout areas. Metal bumps made of gold or other highly conductive malleable material are placed atop the metallization patterns and are forced into the cutout areas between ridges as the dies are compressed onto the substrate. This locks the dies to the circuit run bond pads so as to resist thermal stress and high humidity.Type: GrantFiled: November 8, 1993Date of Patent: June 20, 1995Assignee: Planar Systems, Inc.Inventors: Candice H. Brown, Davar I. Roshanagh
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Patent number: 5414219Abstract: A circuit control device includes two intermating foil pads separated from one another by a narrow gap having a maximum dimension of 0.006 inches. A circuit path having one side connected to one of the pads and a second side connected to the other of the pads is selectively closed and opened by solder application and removal operations. Interdigitated, triangular fingers which are intermated to form the device ensure the formation of acutely angled junctures along the gap to ensure solder bridging of the gap. Emergency control elements are coupled to the circuit control device to permit control of an associated circuit path if the circuit control device itself fails. In that event, an emergency control device is coupled to the emergency control elements to control opening and closing of the circuit path.Type: GrantFiled: April 22, 1994Date of Patent: May 9, 1995Assignee: AT&T Corp.Inventors: Curtis L. Huetson, Rick D. Jussel
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Patent number: 5388328Abstract: A process for the fabrication of an interconnected multilayer board involves the steps of forming a metallic under-conductive layer on a base substrate, forming a windowed resist layer on the metallic under-conductive layer, filling windows of the resist layer with a conductor by plating thereby forming a conductor layer, forming another windowed resist layer on the conductor layer and filling windows of this resist layer with a conductor by plating, thereby forming a via-hole layer and to provide a two-level structure of the conductor layer and the via-hole layer. Thereafter, the resist layers and portions of the metallic under-conductor layer other than those in contact with a lower face of the conductor constituting the conductor layer are dissolved to form a two-level skeleton structure of conductor lines and spaces within the skeleton structure are filled with a varnish in a solventless form and the varnish is cured.Type: GrantFiled: January 28, 1994Date of Patent: February 14, 1995Assignee: Hitachi, Ltd.Inventors: Hitoshi Yokono, Hideo Arima, Takashi Inoue, Naoya Kitamura, Haruhiko Matsuyama, Hitoshi Oka, Fumio Kataoka, Fusaji Shoji, Hideyasu Murooka, Masayuki Kyooi
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Patent number: 5384435Abstract: An electronic device includes a flat flexible dielectric substrate which is less than 0.050 inch thick and has a generally round hole of a given diameter. A ductile conductive film is deposited on the substrate in an area at least about the hole. A generally round terminal pin is inserted into the hole in the substrate in contact with the conductive film. The pin has a given diameter greater than that of the hole. The difference between the diameter of the pin and the diameter of the hole is on the order of 5% to 50% of the diameter of the hole.Type: GrantFiled: January 28, 1994Date of Patent: January 24, 1995Assignee: Molex IncorporatedInventors: Robert M. Fuerst, Fred L. Krehbiel
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Patent number: 5373110Abstract: When an external connection I/O pin which is formed on a multilayer ceramic circuit board is broken off together with a part of a ceramic substrate, an electrically conductive adhesive is filled in the area where the I/O pin broke and was removed, and together with standing a new pin in this place and connecting it electrically, the new pin is bridged and secured to the surrounding I/O pins using a fixation plate. In so doing, it is possible to restore the broken I/O pin to have the same electrical and mechanical characteristics as before.Type: GrantFiled: October 9, 1992Date of Patent: December 13, 1994Assignee: NEC CorporationInventor: Jun Inasaka
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Patent number: 5369219Abstract: A multi-layer printed circuit board is disclosed as having more layers and greater accuracy in the conductive traces of those layers than has been previously possible. Using the disclosed multi-layer printed circuit boards can be built having a conductive path width of 0.5 mils (0.0127 mm) and spacing between such conductive traces of 0.5 mils (0.0127 mm). The method enables multi-layer boards to be created having more than eight layers, and still maintaining the desired 0.5 mil conductive path width and spacing. The enhanced accuracy and increased number of layers is made possible by use of adjustments to customer-supplied art work based upon evaluation of test pieces made early in the procedure. By use of the disclosed method, multi-layer printed circuit boards can he built having a high density of coaxial cable equivalents and tuned wave guide equivalents.Type: GrantFiled: February 10, 1993Date of Patent: November 29, 1994Assignee: Multimedia Design, Inc.Inventor: Robert Q. Kerns
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Patent number: 5357060Abstract: A pattern structure of a printed circuit board for mounting various kinds of electronic chip parts. The printed circuit board has a pad in each of a circuit connecting portion and a ground circuit portion thereof. A broad continuous ground pattern is formed with cuts to provide the pad in the ground circuit portion with substantially the same size or area as the pad in the circuit connecting portion. The pad in the ground circuit portion is connected to copper foil surrounding the cuts.Type: GrantFiled: September 2, 1992Date of Patent: October 18, 1994Assignee: NEC CorporationInventor: Koji Yamashita
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Patent number: 5349495Abstract: A system for securing and electrically connecting a semiconductor chip to a body of passive substrate. The semiconductor chip and the substrate are both provided with bonding pads or bonding areas. The bonding pads or areas are located so that when a chip is placed next to the substrate, at least some of the bonding pads on the chip are aligned with corresponding bonding areas on the substrate. Micro-pins in the shape of straight wires, stubs or loops are used to electrically connect some of the bonding pads on the chip to corresponding areas on the substrate thereby electrically connecting them and also securely bonding the chip to the substrate. In the preferred embodiment, epoxy is used to further strengthen the physical bonding between the chip and the substrate. The wicking action of the micro-pins reduces bridging of solder across adjacent micro-pins.Type: GrantFiled: October 4, 1990Date of Patent: September 20, 1994Assignee: VLSI Technology, Inc.Inventors: Thomas A. Visel, Jon M. Long
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Patent number: 5345040Abstract: A device including a conductor track foil with contact pins of an electrical component. The conductor track foil includes two insulating layers with an intervening conducting layer with lands in the upper layer for soldering the conductive layer to the contact pins of the electrical component. The conductor track foil is lowered, positionally correctly, onto the electrical component by use of a mounting device. The bottom insulating layer and the conducting layer of the soldering lands, which are free of an insulating layer on the top, are pierced by the contact pins extending at right angles to the conductor track foil. The conductor track foil is released by the mounting apparatus. A soldered connection is made between the lands and the contact pins. As a result, a device including an electrically reliably gap free conducting connection is attained even if the contact pins are eccentrically associated with the soldering lands.Type: GrantFiled: October 28, 1992Date of Patent: September 6, 1994Assignee: Robert Bosch GmbHInventors: Horst Stade, Helmut Deringer
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Patent number: 5334804Abstract: An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprises an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post.Type: GrantFiled: November 17, 1992Date of Patent: August 2, 1994Assignee: Fujitsu LimitedInventors: David G. Love, Larry L. Moresco, William T. Chou, David A. Horine, Connie M. Wong, Solomon I. Beilin
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Patent number: 5324892Abstract: Disclosed is a method of fabricating an electronic interconnection structure comprising at least one solder column Joined to an I/O pad of a substrate, the method including the steps of:(a) applying a quantity of solder to the solder column or I/O pad;(b) aligning the solder column with the I/O pad such that there is a quantity of solder between them;(c) heating the structure to cause the solder to melt and bond the column to the I/O pad; and(d) planarizing the solder column to a predetermined height.Also disclosed is the electronic interconnection structure made by the method according to the invention.Type: GrantFiled: August 7, 1992Date of Patent: June 28, 1994Assignee: International Business Machines CorporationInventors: Francois J. Granier, Jean-Jacques M. Rieu, Philippe Raout, Andre Sanchez
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Patent number: 5293502Abstract: The present integrated circuit package provides both a high density of conductor poles, and reduced crosstalk noises between the conductor poles. The conductor poles are received within holes in an insulating substrate. The insulating substrate has a laminated, multi-layer ceramic substrate structure comprising insulating plates having metallized layers thereon which constitute a portion of the walls of the holes. In addition, insulating layers for insulating the metallized layers from the conductor poles are formed within a selected number of the holes.Type: GrantFiled: April 15, 1992Date of Patent: March 8, 1994Assignee: NGK Spark Plug Co., Ltd.Inventors: Yukihiro Kimura, Nobuhiko Miyawaki, Masao Kuroda
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Patent number: 5290971Abstract: This invention relates to printed circuit boards and a method of fabricating same wherein the input/output terminals are integral with the wiring layer of the printed circuit board. This arrangement allows for a higher density of input/output connections than is possible with conventional printed circuit boards.Type: GrantFiled: December 2, 1991Date of Patent: March 1, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tsuneo Hamaguchi, Masanobu Kohara
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Patent number: 5281772Abstract: A method of forming solder stops on a thick film, comprising a conductive metal and an inorganic oxide, including the step of directing a laser beam onto the film to form a surface consisting essentially of fused inorganic oxides which acts as a solder stop.Type: GrantFiled: October 28, 1991Date of Patent: January 25, 1994Assignee: Delco Electronics CorporationInventors: Bruce A. Myers, John K. Isenberg, Christine R. Coapman, James A. Blanton
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Patent number: 5274197Abstract: An electronic-parts mounting board frame is formed by assembling a plurality of electronic-parts mounting boards into a single frame. The mounting boards may be electrically connected to the frame by separate inner and outer lead frames, the former being formed in the mounting boards and the latter being integral with the frame.Type: GrantFiled: November 25, 1991Date of Patent: December 28, 1993Assignee: Ibiden Co., Ltd.Inventors: Mitsuhiro Kondo, Atsushi Hiroi, Kinya Ohshima
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Patent number: 5266912Abstract: A multichip module (MCM) is formed with external connections on coaxial pins. This provides an impedance between a ground connection and a signal connection which is substantially equal per unit length. The module may be configured so that the impedances of the connections between the signal connections and integrated circuit may also be optimally impedance matched.Type: GrantFiled: August 19, 1992Date of Patent: November 30, 1993Assignee: Micron Technology, Inc.Inventor: Kenneth J. Kledzik
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Patent number: 5252784Abstract: An electronic-parts mounting board frame sheet includes a plurality of electronic-parts mounting board frames serially coupled into a single sheet. Each frame includes an electronic-parts mounting board with an insulating substrate, grouped leads protruding from the insulating substrate, an outer frame integrally formed with the grouped leads, and pilot holes, located in the outer frame, for indicating the positions of the grouped leads of the electronic-parts mounting board. Further, the grouped leads and the outer frame of each electronic-parts mounting board frame are integrally formed.Type: GrantFiled: May 27, 1992Date of Patent: October 12, 1993Assignee: Ibiden Co., Ltd.Inventors: Takuji Asai, Mitsuhiro Kondo, Atsushi Hiroi, Kinya Ohshima
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Patent number: 5250759Abstract: Pads for surface-mount components are formed in elongated rectangular openings in a circuit board directly from stripped portions of insulated hookup wire, thus eliminating additional interconnecting hardware parts and dependency on printed circuitry. For each pad, the wire is formed into a U shape by pressing the wire into the opening from a wiring side the circuit board with a press-driven mandrel shaped to place side portions of the loop at ends of the opening, and a solid, spring-loaded or adhesive filler inserted into the opening between the side wire portion to anchor the loop in place. The bridge portion of the loop, forming the pad, may be positioned so as to be recessed slightly below the circuit board surface so as to capture component leads in the depressed cavity with solder barriers between pads. Alternatively the pad may be located flush with the circuit board or slightly protruding, the location being determined by the travel of the press-driven mandrel.Type: GrantFiled: February 28, 1992Date of Patent: October 5, 1993Inventor: Troy M. Watson
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Patent number: 5239135Abstract: A press-in type fastener for mounting circuit board components or circuit boards to a chassis grips a through-hole in the circuit board by radial expansion of the shank. The fastener has a head and a shank with smooth parallel sides and a length substantially equivalent to, but greater than the thickness of the circuit board. The fastener includes a through-bore which is tapered in the area of the shank. After being loosely inserted into a pre-drilled circuit board mounting hole, the fastener is pressed between a punch and an opposing anvil which expands the fastener shank due to the axial compression of the fastener. The anvil has a substantially planar face which abuts the underside of the circuit board and, therefore, no part of the fastener protrudes through the opposite side of the board of the installation. The fastener may be headed and include teeth which extend axially from the underside of the fastener head for gripping the top side of the circuit board to provide torque resistance.Type: GrantFiled: February 14, 1992Date of Patent: August 24, 1993Assignee: Penn Engineering & Manufacturing Corp.Inventor: Ronald W. Phillips, II
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Patent number: 5235140Abstract: A large electrode bump is generated on a substrate such as a circuit board. A small electrode bump is then formed on the large bump. Preferably a barrier layer is deposited over the large bump prior to formation of the small bump. In this case the small bump is formed on the barrier layer over the large bump. In one embodiment, the small bump is formed by applying a sacrificial layer on the large bump. A window is created in the sacrificial layer. A spring may optionally be inserted in the window. The window is then filled with a conductive material. Finally, the sacrificial layer is removed to reveal the small bump. In another embodiment, a small bump is formed on a semiconductor die and a larger bump is formed on a substrate. The semiconductor die is mounted on the substrate such that the bump on the die contacts the larger bump.Type: GrantFiled: May 21, 1992Date of Patent: August 10, 1993Assignee: Eastman Kodak CompanyInventors: Samuel Reele, Thomas R. Pian
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Patent number: 5196251Abstract: Disclosed is a ceramic substrate having a protective coating on at least one surface thereof which includes:a ceramic substrate having at least one electrically conductive via extending to a surface of the substrate;an electrically conductive I/O pad electrically connected to at least one of the vias;an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet; anda protective layer of polymeric material fully encapsulating the I/O pad, wherein the layer of polymeric material protects the I/O pad from corrosion.Type: GrantFiled: April 30, 1991Date of Patent: March 23, 1993Assignee: International Business Machines CorporationInventors: Nanik Bakhru, Richard A. Bates, George Czornyj, Nunzio DiPaolo, Ananda H. Kumar, Suryanarayana Mukkavilli, Heinz O. Steimel, Rao R. Tummala
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Patent number: 5183698Abstract: An arrangement for protection of electrical equipment from electrical overstress pulses or transients using an electrical coupling to ground through a non-linear resistance having a high resistance at normal voltages and a very low resistance in response to an excessively high voltage pulse of transient, wherein the non-liner resistance is interposed between two contraposed faces of two electrodes, and at least one of said electrodes is a thin planar element whose said face is a thin edge of the planar element.Type: GrantFiled: March 7, 1991Date of Patent: February 2, 1993Assignee: G & H Technology, Inc.Inventors: Roger C. Stephenson, Hugh M. Hyatt
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Patent number: 5172472Abstract: A multi-layer rigid prototype printed circuit board is fabricated by applying a heat activated, rapid setting or tacking melt-remelt adhesive utilizing a moderate temperature heat laminating device onto appropriate surfaces of pre-etched and plated insulative film based, flexible film layers. A computer guided drill drills through-holes within an electrical insulative material planar substrate core using prescribed drill sizes for each through-hole pin size desired for a given hole location. The etched layers with the adhesive applied are positioned in proper sequence aligned to the drilled hole pattern and heat laminated thereto as a stacked array on the top and/or bottom surfaces of the substrate core. Computer guided drilling of the adhered films with prescribed smaller drill sizes at each through-hole location is effected to create film cantilever portions extending radially outwardly of the edge of the through-holes.Type: GrantFiled: August 15, 1991Date of Patent: December 22, 1992Assignee: Direct Imaging Inc.Inventors: Frederick H. Lindner, Paul A. Duncanson
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Patent number: 5118386Abstract: A printed circuit board having a plurality of bumps that serve for connection terminals, the bumps being formed by covering the printed circuit except portions where the bumps are to be formed, applying an electroplating onto the uncovered bump-forming portions on the printed circuit maintaining a thickness nearly equal to that of the covering, applying thereon a non-electrolytic plating and electroplating on the whole surface from the surfaces of the bump-forming portions to the surfaces of the covered portions, and removing the platings by etching from the surface except the bump portions.Type: GrantFiled: December 18, 1989Date of Patent: June 2, 1992Assignee: Mitsui Mining & Smelting Co., Ltd.Inventors: Tatsuo Kataoka, Yutaka Iguchi
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Patent number: 5092035Abstract: A first set of plated-through holes in the printed circuit board (PCB) are covered by a protective solder mask on the solder side of the PCB while a second set of plated-through holes are exposed. Electrical components are disposed on the component side with leads inserted in the second set of holes. Solder is prevented from flowing into the first set of holes during wave soldering by the mask covering. Conductive pins designed for press fitting into the first set of holes are inserted therethrough to define connecting pins on each side of the PCB following wave soldering. This permits both a wave soldering and press fit operation to be accommodated.Type: GrantFiled: September 10, 1990Date of Patent: March 3, 1992Assignee: Codex CorporationInventors: T. Blane McMichen, Kerry J. McMullen, John A. Sudanowicz, III
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Patent number: 5003131Abstract: A device for connecting a metal conductor on a surface of a first ceramic body to an outer terminal in which dispersion of copper metal into adjoining layers is prevented. An outer surface conductor made of Cu or Au is connected to the metal conductor on the surface of the ceramic body and extends through a throughhole in a second ceramic body. A lower conductive layer of Pd is formed over and in electrical connection with the outer end of the outer surface conductor, the lower layer having an area greater than the area of the outer end of the outer surface conductor. A dispersion-preventing layer is formed on a portion of the lower layer concentric with the outer end of the outer surface conductor, the dispersion-preventing layer having an area greater than the area of the outer end of the outer surface conductor but less than the area of the lower layer. The dispersion-preventing layer is made of a crystallized glass material.Type: GrantFiled: September 8, 1989Date of Patent: March 26, 1991Assignee: NKG Spark Plug Co., Ltd.Inventors: Asao Morikawa, Kazuo Kondo