Plural Layers Patents (Class 174/524)
  • Patent number: 10667419
    Abstract: There are provided an electronic component module in which an external terminal is disposed outwardly from a mold part by a plating process and a manufacturing method thereof. The electronic component module includes a substrate, at least one electronic component mounted on the substrate, a mold part sealing the electronic component, and at least one connection conductor having one end bonded to one surface of the substrate and formed in the mold part so as to penetrate through the mold part. The connection conductor is formed to have a form in which horizontal cross-sectional areas of the connection conductor are gradually reduced toward the substrate and includes at least one step.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 26, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Do Jae Yoo, Eun Jung Jo, Jae Hyun Lim
  • Patent number: 10645796
    Abstract: An electrical node includes a substrate for accommodating a functional element. The substrate includes a first side and an opposite second side, and hosting a number of connecting elements. The functional element includes an electronic component and conductive traces. The electrical node also includes a first material layer defining a protective covering. The first material layer defining at least a portion of the exterior surface of the nod arranged to reduce at least thermal expansion and/or mechanical deformation related stresses between one or more elements included in the node, adjacent the node and/or at least at a proximity thereto.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: May 5, 2020
    Assignee: TACTOTEK OY
    Inventors: Antti Keränen, Tomi Simula, Mikko Heikkinen, Jarmo Sääski, Pasi Raappana, Minna Pirkonen
  • Patent number: 10580743
    Abstract: A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric reactant; and a sealant layer arranged on a surface of the self-destructive layer, on sidewalls of the self-destructive layer, and on the chip substrate such that the sealant layer forms a package seal on the semiconductor chip; wherein the pyrophoric reactant ignites spontaneously upon exposure to air.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 10529637
    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu
  • Patent number: 10030463
    Abstract: An apparatus for use subsea includes a container having at least one aperture; a lid securable to the container to cover the at least one aperture, suitable to isolate the inside of the container from the outside of the container when fluid pressure outside the container is at least 5000 kPa. The lid has one or more electrical connections providing electrical communication from a first side of the lid to a second side of the lid. The apparatus further includes one or more wires for providing electrical communication between one or more electrical components in the container and the one or more electrical connections in the lid.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: July 24, 2018
    Assignee: AKER SOLUTIONS LIMITED
    Inventors: Kenneth Hood, Stuart Reid, Daniel Ahrens
  • Patent number: 10026701
    Abstract: The various technologies presented herein relate to isolating an integrated circuit from electromagnetic radiation/interference. The integrated circuit can be encapsulated in a coating (e.g., a conformal coating). A conductive layer can be formed over the coating, where the conductive layer is deposited to connect with an electromagnetic shielding layer included in a substrate upon which the integrated circuit is located thereby forming a Faraday cage around the integrated circuit. Hollow spheres can be included in the coating to improve the dielectric constant of the coating. The conductive layer can be formed from at least one of metallic material or a polymer coating which includes conductive material. The integrated circuit can be utilized in conjunction with a heat sink and further, the integrated circuit can be of a flip chip configuration.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: July 17, 2018
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Christopher T. Rodenbeck, Kenneth A. Peterson
  • Patent number: 9882304
    Abstract: A connection arrangement is for an electrical connection from an interior room of a sealed housing to an outside of the sealed housing. The connection arrangement includes a first connection line, a second connection line, and an interconnecting element. The first connection line is adapted to be electrically coupled to an electric source arranged outside the housing. The second connection line is adapted to be electrically coupled to an electric element arranged in the interior room. The first connection line is configured for being guided through an opening in a wall of the housing into the interior room. An end section of the first connection line and an end section of the second connection line are both electrically and/or mechanically connected to the interconnecting element to establish an electrical connection from the interior room to the outside of the sealed housing.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: January 30, 2018
    Assignee: TORQUE AND MORE (TAM) GMBH
    Inventor: Lutz May
  • Patent number: 9853001
    Abstract: A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric reactant; and a sealant layer arranged on a surface of the self-destructive layer, on sidewalls of the self-destructive layer, and on the chip substrate such that the sealant layer forms a package seal on the semiconductor chip; wherein the pyrophoric reactant ignites spontaneously upon exposure to air.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9806234
    Abstract: A method of manufacturing a light emitting device includes a first step of mounting a light emitting element on a substrate having a conductor wiring and electrically connecting the light emitting element with the conductor wiring, a second step of disposing a light reflecting resin which reflects light from the light emitting element to surround the light emitting element, and a third step of disposing a sealing member after hardening the light reflecting resin to cover the light emitting element.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 31, 2017
    Assignee: Nichia Corporation
    Inventors: Motokazu Yamada, Mototaka Inobe, Kunihiro Izuno
  • Patent number: 9786632
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: October 10, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Patent number: 9730326
    Abstract: Electrical contact arrangement for an electric motor and method for producing same. The present invention relates to an electrical contact arrangement for an electric motor, in particular for an EC drive of a motor vehicle fan, comprising an elongate contact which runs perpendicular to a planar basic conductor, wherein the basic conductor is in the form of a leadframe, and a conductive cohesive and/or form-fitting and/or force-fitting connection is provided between the leadframe and the contact. The present invention also relates to a method for the production of said electrical contact arrangement.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: August 8, 2017
    Assignee: BROSE FAHRZEUGTEILE GMBH & CO. KG, WÜRZBURG
    Inventors: Steffen Ehrmann, Katharina Gerlach, Artur Schmidt, Karl-Heinz Fleischmann
  • Patent number: 9674952
    Abstract: An electrical interconnect includes a copper pillar and solder cap. The copper pillar and solder cap are formed onto a contact pad or an under bump metallurgy (UBM). In some applications, the contact pad or UBM is part of an electronic component, such as a semiconductor chip. In other cases, the contact pad is part of laminated substrate, such as a printed circuit board (PCB), or a ceramic substrate. The copper pillar and the solder cap are printed using an ink printer, such as an aerosol ink jet printer. A post heat treatment solidifies the interconnection between the contact pad or UBM, the copper pillar and the solder cap.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 6, 2017
    Assignee: Flextronics AP, LLC
    Inventors: Weifeng Liu, Anwar Mohammed, Zhen Feng
  • Patent number: 9607769
    Abstract: A multilayer ceramic capacitor and a board having the same are provided. The multilayer ceramic capacitor includes a ceramic body including internal electrodes and having lead-out portions exposed to end surfaces thereof, and external electrodes disposed on portions of the end surfaces of the ceramic body to be connected to the lead-out portions of the internal electrodes, terminal electrodes coupled to both end portions of the ceramic body and including horizontal portions disposed below the ceramic body and vertical portions spaced apart from the end surfaces of the ceramic body and connected to the external electrodes.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: March 28, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Sang Soo Park
  • Patent number: 9462709
    Abstract: An element housing package includes a substrate, a frame body, and an input-output terminal. The input-output terminal has a wiring conductor formed in a stacked body consisting of dielectric layers and ground layers which are alternately laminated, to extend through an inside of the stacked body, and a lead terminal connected to the wiring conductor. A non-formation region is provided in the ground layers around the wiring conductor, which passes through the inside of the input-output terminal in a vertical direction of the stacked body. The non-formation region has, in order from an upper side toward a lower side, a first non-formation section, a second non-formation section having an area smaller than that of the first non-formation section, and a third non-formation section having an area larger than that of the second non-formation section.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 4, 2016
    Assignee: KYOCERA CORPORATION
    Inventor: Yoshiki Kawazu
  • Patent number: 9442658
    Abstract: Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a single-rank memory module by providing separate chip select signals to separately select a first memory device and a second memory device. A method may further include, subsequent to sensing that the initializing is completed, for example, providing a single chip select signal to simultaneously select the first memory device and the second memory device.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 13, 2016
    Assignee: Micron Technology, Inc.
    Inventor: William A. Lendvay
  • Patent number: 9362187
    Abstract: A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip and a second group of terminal pads of the chip package is electrically connected to the integrated circuit chip. The first and second groups of terminal pads are arranged on a common terminal surface of the chip package. A pad size of a terminal pad of the first group of terminal pads is greater than a pad size of a terminal pad of the second group of terminal pads.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies AG
    Inventor: Peter Ossimitz
  • Patent number: 8946566
    Abstract: An improved method for producing a PCB assembly requiring at least two different encapsulants is disclosed. The PCB assembly may have two or more separate regions in which electronic devices are attached. In each region, a unique encapsulant with different mechanical, electrical, physical and or chemical properties is used according to the particular requirements of the electronic devices in that region.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: February 3, 2015
    Assignee: Apple Inc.
    Inventor: John J. Baker
  • Patent number: 8922986
    Abstract: An electronic data recorder including an electronic data storage device disposed within an enclosure having a main housing and a cover adapted to engage a base region of the housing. The main housing forms a cavity housing the electronic data storage device. A mounting wall extending from the main housing and including an attachment foot for attachment to a vehicle wherein an impact during a vehicle crash preferentially fractures one or both the mounting wall and attachment foot as opposed to the main housing.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 30, 2014
    Assignee: Honda Motor Co., Ltd.
    Inventor: Darin S. Garrett
  • Patent number: 8879273
    Abstract: A mobile terminal including a first casing, and a second casing connected to the first casing. An electrically conductive plate is disposed inside either of the first casing and the second casing or between the first casing and the second casing. A flexible printed circuit board connects the first casing and the second casing. An electrically conductive reinforcement member is connected to a surface of a portion of the flexible printed circuit board. An electrically conductive connecting member conducts electricity between the electrically conductive reinforcement member and the electrically conductive plate.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: November 4, 2014
    Assignees: Sony Corporation, Sony Mobile Communications Inc.
    Inventor: Kotaro Fujimori
  • Patent number: 8785792
    Abstract: Disclosed herein is a case structure of an electronic product to which a film-type electronic circuit is adhered. The case structure may include a case of an electronic product and a first film adhered to the case. The case structure may further include a second film adhered to the first film such that one surface of the second film contacts the first film, and an electronic circuit layer adhered to the first film. The electronic circuit layer may be arranged between the first film and the second film, wherein the first film is thermally adhered to the case. The first film may have a melting at a melting point that is lower than a heat-resistant temperature of the case.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ja Myeong Koo, Soon Min Hong, Tae Sang Park, Young Jun Moon, Gyun Heo, Sun Gu Yi
  • Patent number: 8748756
    Abstract: An electric device includes a support substrate 12, an electric circuit 14 provided in a sealing region set on the support substrate 12, an electric wiring provided on the support substrate 12 for electrically connecting an external electrical signal input/output source with the electric circuit 14, a sealing member 16 provided on the support substrate 12 to surround the sealing region, and a sealing substrate 17 bonded to the support substrate 12 with the sealing member 16 interposed therebetween. the electric circuit 14 includes an electronic element 24 having an organic layer, and a width of the sealing member 16 differs between an intersection region in which the electric wiring 15 and the sealing member 16 intersect each other and a non-intersection region excluding the intersection region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: June 10, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kenji Kasahara, Masaya Shimizu, Tomoki Kurata
  • Patent number: 8723057
    Abstract: Systems and methods for protecting a flight recorder are provided. In certain embodiments, a crash survivable memory unit, comprises a memory device that records flight data; a flexible insulation layer that inhibits thermal energy from conducting from an external side of the flexible insulation layer to an internal side of the flexible insulation layer, wherein the internal side faces the memory device; a microlattice layer abutting the internal side and enclosing the memory device, the microlattice layer configured to distribute thermal energy that passes through the flexible insulation layer substantially throughout the microlattice layer; and a heat absorbing material that impregnates the microlattice layer, the heat absorbing material configured to absorb the thermal energy in the microlattice layer; and an impact resistant layer encircling the flexible insulation layer, wherein the impact resistant layer absorbs shocks that result from other objects contacting the impact resistant layer.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: May 13, 2014
    Assignee: Honeywell International Inc.
    Inventors: David Lowell Miller, Gary Kersten, Wendell A. Frost
  • Patent number: 8653383
    Abstract: An electric device includes a support substrate 12, an electric circuit 14 provided in a sealing region set on the support substrate 12, an electric wiring provided on the support substrate 12 for electrically connecting an external electrical signal input/output source with the electric circuit 14, a sealing member 16 provided on the support substrate 12 to surround the sealing region, and a sealing substrate 17 bonded to the support substrate 12 with the sealing member 16 interposed therebetween. the electric circuit 14 includes an electronic element 24 having an organic layer, and a width of the sealing member 16 differs between an intersection region in which the electric wiring 15 and the sealing member 16 intersect each other and a non-intersection region excluding the intersection region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 18, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kenji Kasahara, Masaya Shimizu, Tomoki Kurata
  • Patent number: 8624111
    Abstract: A mobile device case including a housing sized to receive a mobile device; at least a portion of the housing including a first layer, a second layer, and a third layer of material, the second layer of material being disposed between the first and third layers of material and having a material with a higher durometer than the first and third layers of material.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: January 7, 2014
    Assignee: A.G. Findings & Mfg. Co.
    Inventors: Fernando Tages, Daniel Acero
  • Patent number: 8559186
    Abstract: An inductor with patterned ground plane is described. In one design, the inductor includes a conductor formed on a first layer and a patterned ground plane formed on a second layer under the conductor. The patterned ground plane has an open center area and a shape matching the shape of the conductor. The patterned ground plane includes multiple shields, e.g., eight shields for eight sides of an octagonal shape conductor. Each shield has multiple slots formed perpendicular to the conductor. Partitioning the patterned ground plane into separate shields and forming slots on each shield help prevent the flow of eddy current on the patterned ground plane, which may improve the Q of the inductor. Multiple interconnects couple the multiple shields to circuit ground, which may be located at the center of the conductor.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: October 15, 2013
    Assignee: QUALCOMM, Incorporated
    Inventor: Zhang Jin
  • Patent number: 8547701
    Abstract: This publication discloses an electronics module and a method for manufacturing it. The electronic module includes at least one first embedded component (6), the contact terminals (7) of which face essentially towards the first surface of the insulating-material layer (1) and which is connected electrically by its contact terminals (7) to the conductor structures contained in the electronic module. According to the invention, a second embedded component (6?), the contact terminals (7?) of which face essentially towards the second surface of the insulating-material layer and which is connected electrically by its contact terminals (7?) to the conductor structures contained in the electronic module, is attached by means of glue or two-sided tape to the first component (6), and the contact terminals (7, 7?) are connected to the conductor structures with the aid of a conductive material, which is arranged in the insulating-material layer in holes (17) at the locations of the contact terminals (7, 7?).
    Type: Grant
    Filed: November 24, 2005
    Date of Patent: October 1, 2013
    Assignee: Imbera Electronics Oy
    Inventors: Risto Tuominen, Antti Iihola
  • Patent number: 8481861
    Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: July 9, 2013
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Robert C. Cooney, Joseph M. Wilkinson
  • Patent number: 8440924
    Abstract: A switch unit includes a switch cover having an opening; a knob for operating a switch, the knob being provided within the opening in such a manner as to oscillate or rotate; and a parting line is set on a circumferential edge portion of the opening of the switch cover. The switch cover includes a first resin layer which is molded of a resin material having a property in which a plate layer does not adhere thereto, in which the opening is formed and which defines a rear side of the switch cover; a second resin layer which is molded of a resin material having a property in which a plated layer can adhere thereto and which is provided on a surface side of the first resin layer in such a manner as to be integral with the first resin layer; and a plated layer which is provided to cover a surface of the second resin layer.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: May 14, 2013
    Assignee: Kabushiki Kaisha Tokia Rika Denki Seisakusho
    Inventor: Toshimitsu Ukai
  • Patent number: 8328584
    Abstract: This invention is directed to systems and methods for providing a port in an electronic device housing that is electrically isolated from a conductive portion of a connector inserted in the port without the use of a nonconductive trim in the port. In some embodiments, the connector may include a non-conductive flange or ring operative to contact the housing and the portions of the housing within the port. In some embodiments, a thin layer of non-conductive material may be applied to the portions of the housing within the port to prevent conductive portions of the connector from coming into contact with the housing (e.g., and grounding the conductive portion. This invention may be of particular interest when the conductive portion that may come into contact with the housing is not used to ground the connector.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: December 11, 2012
    Assignee: Apple Inc.
    Inventors: Stephen Brian Lynch, Emery Sanford, Cameron Frazier
  • Patent number: 8203849
    Abstract: A joint board is arranged between an upper package and a lower package. The arrangement of the joint board makes it possible to reduce the size of solder balls and to arrange them with narrower pitch. The joint board has slightly greater dimensions those of the upper package and the lower package. This makes it possible to prevent underfill from leaking and spreading.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: June 19, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Masanori Shibamoto
  • Patent number: 8129627
    Abstract: A circuit board includes a semiconductor chip having an upper surface and side surfaces connected to the upper surface. A bonding pad is disposed on the upper surface of the semiconductor chip. A bump is disposed on the bonding pad and projects from the bonding pad by a predetermined height. A circuit board body has a recess part, and the semiconductor chip is positioned in the recess part so that the circuit board body covers the upper surface and the side surfaces of the semiconductor chip while exposing an end of the bump. A wiring line is disposed on the circuit board body and part of the wiring line is positioned over the bump. An opening is formed in a portion of the part of the wiring line over the bump to expose the bump. A reinforcing member physically and electrically connects the exposed bump and the wiring line.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Woong Sun Lee, Qwan Ho Chung, Ki Young Kim
  • Patent number: 8093512
    Abstract: A package of an environmentally sensitive electronic device including a first substrate, a second substrate, an environmentally sensitive electronic device, a plurality of barrier structures, and a fill is provided. The second substrate is disposed above the first substrate. The environmentally sensitive electronic device is disposed on the first substrate and located between the first substrate and the second substrate. The barrier structures are disposed between the first substrate and the second substrate, wherein the barrier structures surround the environmental sensitive electronic device, and the water vapor transmission rate of the barrier structures is less than 10?1 g/m2/day. The fill is disposed between the first substrate and the second substrate and covers the environmentally sensitive electronic device and the barrier structures.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: January 10, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Kuang-Jung Chen, Jia-Chong Ho, Jing-Yi Yan, Shu-Tang Yeh
  • Publication number: 20110303457
    Abstract: An electronic device includes a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the functional structural body disposed therein, wherein the covering structure is provided with a side wall provided on the substrate and comprising an interlayer insulating layer surrounding the cavity part and a wiring layer; a first covering layer covering an upper portion of the cavity part and having an opening penetrating through the cavity part and composed of a laminated structure including a corrosion-resistant layer; and a second covering layer for closing the opening.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 15, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shogo INABA, Akira SATO
  • Patent number: 7897881
    Abstract: Disclosed is a method for producing a package. According to said method, a substrate is provided, on a surface of which one or several components are disposed, and a hermetically sealing protective layer is formed on the one or several components and on the surface of the substrate. The hermetically sealing protective layer is impermeable to gas, liquid, and electromagnetic waves, temperature-resistant, electrically insulating, and process-resistant.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: March 1, 2011
    Assignee: Siemens Aktiengesellschaft
    Inventors: Michael Kaspar, Herbert Schwarzbauer, Karl Weidner
  • Patent number: 7892392
    Abstract: A method for manufacturing an over-current protection device comprises a step of providing at least one current sensitive device and a step of pressing. The current sensitive device comprises a first electrode foil, a second electrode foil and a PTC conductive layer physically laminated between the first and second electrode foils. The pressing step is to press the current sensitive device at a predetermined temperature, thereby generating at least one overflow portion at sides of the PTC conductive layer to form the over-current protection device. The predetermined temperature is higher than the softening temperature of the PTC conductive layer. The over-current protection devices manufactured according to the present invention have superior resistance distribution.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: February 22, 2011
    Assignee: Polytronics Technology Corporation
    Inventors: David Shau Chew Wang, Jyh Ming Yu
  • Patent number: 7812265
    Abstract: Provided are a semiconductor package and a method for forming the same, and a PCB (printed circuit board). The semiconductor package comprises: a PCB including a slit at a substantially central portion thereof, the PCB including an upper surface and a lower surface; a semiconductor chip mounted on the upper surface of the PCB; an upper molding layer disposed on the upper surface and covering the semiconductor chip; and a lower molding layer filling the slit and covering a portion of the lower surface of the PCB, wherein the PCB comprises a connecting recess at a side surface thereof, and the upper molding layer and the lower molding layer are in contact with each other at the connecting recess.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: October 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Seob Shin, Byung-Seo Kim, Min-Young Son, Min-Keun Kwak
  • Patent number: 7714236
    Abstract: An electric component includes a substrate, a function element provided on the substrate, a first sealing body provided on the substrate to cover the function element at a certain distance, the first sealing body including multiple apertures communicating with an internal space formed between the first sealing body and the substrate, and a second sealing body provided on the first sealing body and configured to occlude the multiple apertures. Here, a boundary between the first sealing body and the substrate is curved in a direction to narrow the internal space.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: May 11, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michinobu Inoue, Susumu Obata
  • Patent number: 7683269
    Abstract: A terminal electrode body on a substrate is exposed relative to a resin layer, protruding out beyond the side of the resin layer. That is, the terminal electrode body is not covered by the resin layer. The electronic element is covered by an insulating layer and the terminal electrode body and the electronic element are electrically connected. Hence, an electric signal applied to the terminal electrode body can be transmitted to the electronic element. A cover layer covers the terminal electrode body and the boundary between the terminal electrode body and the resin layer.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: March 23, 2010
    Assignee: TDK Corporation
    Inventors: Toshiyuki Yoshizawa, Masaomi Ishikura, Masahiro Miyazaki, Akira Furuya, Nobuyuki Okuzawa
  • Patent number: 7683268
    Abstract: A semiconductor element and a passive element are embedded in an insulating resin film by thermocompression bonding. After formation of a interconnection, a layered film which contains a film insulating between elements and is provided with a recess or penetrated portion is pressure-bonded followed by formation of a member with a high resistance or a high dielectric constant by embedding a material of a member constituting an element such as a resistor and a capacitor in the recess. Furthermore, after formation of the upper layer insulating resin film, a photoimageable solder resist layer containing the cardo type polymer is formed, and interconnection formation and solder electrode formation are performed.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: March 23, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Takeshi Nakamura, Atsuhiro Nishida
  • Patent number: 7672098
    Abstract: A power plug includes a base, an upper cover attached to the base, a base-side cover adjacent the base and removeably attached to the upper cover, an output cord, a leakage current detection and protection circuit for detecting a leakage current in the output cord, and an electrical connection mechanism for electrically connecting and disconnecting an input side and an output of the power plug. The leakage current detection and protection circuit and the electrical connection mechanism are attached to the base and disposed substantially within a space enclosed by the base and the upper cover. A plurality of connecting ends of the circuit extend from the space enclosed by the base and the upper cover into a space enclosed by the base-side cover and the upper cover. Wires of the output cord are connected to the connecting ends, respectively.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: March 2, 2010
    Assignee: Shanghai ELE Manufacturing Corp.
    Inventors: Long Zhang, Chengli Li
  • Publication number: 20100033885
    Abstract: A potted electrical circuit is enclosed within a housing and has a first and second fiberglass layer that is laid upon a top surface of the potted electrical circuit. A lid of the housing seals the electrical circuit there within and an opening formed in a side wall allows circuitry wiring to extend there from out. The first fiberglass layer is a woven layer while the second fiberglass layer is a padding-like layer. Circuitry wiring pushes through the woven first fiberglass layer before extending out through the opening in the housing. The first fiberglass layer is tucked in and around the electrical circuit and adheres to the inside of the housing by attaching to the potting material while it hardens. In a preferred embodiment, the electrical circuit in combination with the insulation material is used within a transient voltage surge suppression device.
    Type: Application
    Filed: August 8, 2008
    Publication date: February 11, 2010
    Applicant: SURGE SUPPRESSION, INCORPORATED
    Inventors: Ronald Hotchkiss, Richard Hotchkiss, Jr., Ricky Fussell, Andrea Haa
  • Patent number: 7552532
    Abstract: A method is provided to produce a hermetic encapsulation for an electronic component, which may be an optical and at least partially light-permeable component or a surface wave component, comprises attaching and electrically contacting a component based on a chip to a carrier comprising electrical connection surfaces, such that a front of the chip bearing component structures facing the carrier is arranged to clear it, covering a back of the chip with a film made of synthetic material, such that edges of the film overlap the chip; tightly bonding the film and carrier in an entire edge region around the chip; structuring the film such that the film is removed around the edge region in a continuous strip parallel to the edge region; and applying a hermetically sealing layer over the film, such that this layer hermetically terminates with the carrier in a contact region outside of the edge region.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: June 30, 2009
    Assignee: EPCOS AG
    Inventors: Alois Stelzl, Hans Krueger, Gregor Feiertag, Ernst Christl
  • Patent number: 7525803
    Abstract: A power converter including a printed circuit board (PCB) having a plurality of heat conductive layers configured to sink heat generated by the power converter electronics. Each of these heat conductive layers are comprised of thermally conductive material configured as planar sheets, each of these heat conductive layers being coupled to at least one wire to sink heat therefrom, such as via a wire of an input cable and/or output cable. Advantageously, a more compact power converter is realized having improved power output while operating within safety guidelines.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: April 28, 2009
    Assignee: iGo, Inc.
    Inventors: Jason Walter Swanson, Bryan Wayne McCoy, Arthur Kenneth Dewyer
  • Publication number: 20090025976
    Abstract: An electric component includes a substrate, a function element provided on the substrate, a first sealing body provided on the substrate to cover the function element at a certain distance, the first sealing body including multiple apertures communicating with an internal space formed between the first sealing body and the substrate, and a second sealing body provided on the first sealing body and configured to occlude the multiple apertures. Here, a boundary between the first sealing body and the substrate is curved in a direction to narrow the internal space.
    Type: Application
    Filed: July 22, 2008
    Publication date: January 29, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Michinobu INOUE, Susumu Obata
  • Patent number: 7352602
    Abstract: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 1, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Jeffery W. Janzen
  • Patent number: 7183491
    Abstract: To provide a printed wiring board where the impedance between pads through which differential signals pass has been set to a predetermined standard value. The printed wiring board includes a first conductor layer extending over an area excluding a hole formed for each pad group and filled with a dielectric, and a second conductor layer extending over an area containing areas facing the hole. The hole encompasses a plurality of areas facing predetermined respective pads which are adjacent to each other and which form the pad group from among the plurality of pads.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: February 27, 2007
    Assignee: Fujitsu Limited
    Inventor: Kiyoshi Ishikawa
  • Patent number: 7174631
    Abstract: An electrical connection terminal of an embedded chip and a method for fabricating the same are disclosed. An insulating layer is provided on a circuit board integrated with a chip and has a plurality of first openings for exposing a conductive pad of the chip. A first metal layer is formed on the conductive pad, and a conductive layer if formed on surfaces of the first metal layer, the insulating layer and the first openings. A patterned resist layer is formed on the conductive layer and has a plurality of second openings for exposing a part of the conductive layer corresponding to the condictive pad of the chip. A second metal layer is formed on the exposed part of the conductive layer by an electroplating process. Thus, the fabrication of conductive structure of the conductive pad of the ship and build-up of conductive circuits on the circuit board are integrated simultaneously.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: February 13, 2007
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Shih-Ping Hsu, Kun-Chen Tsai
  • Patent number: 7161092
    Abstract: The present invention provides in one embodiment, a system for encapsulating a substrate on a vehicle structure. The system includes the substrate, the vehicle structure and a package substrate. The substrate has a top portion and a bottom portion. The vehicle structure is operatively connected to the bottom portion of the substrate. The package substrate has a plurality of layers, where the package substrate is operatively connected to the top portion of the substrate. The package substrate conforms to a periphery area of the top portion of the substrate.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: January 9, 2007
    Assignee: Visteon Global Technologies, Inc.
    Inventor: Andrew Glovatsky
  • Patent number: 7049510
    Abstract: A sensor with a carrier board which is arranged in a housing is at least partly produced by an injection molding process and fitted with electronic, optical, electromechanical and/or opto-electronic components. A region of the carrier board and at least some of the components disposed thereon are arranged in a hollow space formed inside the at least partly injection molded housing.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: May 23, 2006
    Assignee: Sick AG
    Inventor: Torsten Neuhaeuser
  • Patent number: 6894220
    Abstract: A grounding member support forms an interference or friction fit with an opening defined by a circuit board. A compliant, electrically conductive grounding member couples to the grounding member support. The grounding member electrically couples a grounding layer of the circuit board with a support mount coupled to the circuit board. During assembly, insertion of the grounding member support within the opening defined by the circuit board creates an expansive or lateral force on the opening. Furthermore, during assembly, the support mount compresses the compliant, electrically conductive grounding member against the circuit board. The interference fit between the grounding member support and the opening along with compression of the grounding member between the circuit board and the support mount limits the amount of stress received by a surface of the circuit board.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: May 17, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Frederic Michael Kozak, Lester Creekmore