Abstract: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.

Abstract: To provide a printed wiring board where the impedance between pads through which differential signals pass has been set to a predetermined standard value. The printed wiring board includes a first conductor layer extending over an area excluding a hole formed for each pad group and filled with a dielectric, and a second conductor layer extending over an area containing areas facing the hole. The hole encompasses a plurality of areas facing predetermined respective pads which are adjacent to each other and which form the pad group from among the plurality of pads.

Abstract: An electrical connection terminal of an embedded chip and a method for fabricating the same are disclosed. An insulating layer is provided on a circuit board integrated with a chip and has a plurality of first openings for exposing a conductive pad of the chip. A first metal layer is formed on the conductive pad, and a conductive layer if formed on surfaces of the first metal layer, the insulating layer and the first openings. A patterned resist layer is formed on the conductive layer and has a plurality of second openings for exposing a part of the conductive layer corresponding to the condictive pad of the chip. A second metal layer is formed on the exposed part of the conductive layer by an electroplating process. Thus, the fabrication of conductive structure of the conductive pad of the ship and build-up of conductive circuits on the circuit board are integrated simultaneously.

Abstract: The present invention provides in one embodiment, a system for encapsulating a substrate on a vehicle structure. The system includes the substrate, the vehicle structure and a package substrate. The substrate has a top portion and a bottom portion. The vehicle structure is operatively connected to the bottom portion of the substrate. The package substrate has a plurality of layers, where the package substrate is operatively connected to the top portion of the substrate. The package substrate conforms to a periphery area of the top portion of the substrate.

Abstract: A sensor with a carrier board which is arranged in a housing is at least partly produced by an injection molding process and fitted with electronic, optical, electromechanical and/or opto-electronic components. A region of the carrier board and at least some of the components disposed thereon are arranged in a hollow space formed inside the at least partly injection molded housing.

Abstract: A grounding member support forms an interference or friction fit with an opening defined by a circuit board. A compliant, electrically conductive grounding member couples to the grounding member support. The grounding member electrically couples a grounding layer of the circuit board with a support mount coupled to the circuit board. During assembly, insertion of the grounding member support within the opening defined by the circuit board creates an expansive or lateral force on the opening. Furthermore, during assembly, the support mount compresses the compliant, electrically conductive grounding member against the circuit board. The interference fit between the grounding member support and the opening along with compression of the grounding member between the circuit board and the support mount limits the amount of stress received by a surface of the circuit board.

Abstract: A sensor with a carrier board which is arranged in a housing is at least partly produced by an injection molding process and fitted with electronic, optical electromechanical and/or opto-electronic components. A region of the carrier board and at least some of the components disposed thereon are arranged in a hollow space formed inside the at least partly injection molded housing.

Abstract: The present invention is to provide a manufacturing process of an integrated circuit module comprising the following steps: (a) providing a circuit board, which has at least one module circuit pattern thereon, said circuit pattern having at least one chip assembly area and an electronic element assembly area; (b) mounting at least one substrate on said at least one chip assembly area; said substrate is provided thereon with at least one connecting circuit pattern which is electrically connected to the at least one module circuit pattern of said circuit board; (c) mounting at least one IC chip on said at least one substrate such that said IC chip is electrically connected to said connecting circuit pattern of the substrate.

Abstract: A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

Abstract: A semiconductor device exhibiting a lower incidence of burrs forming on its contacts during the singulation process. The semiconductor device includes a die which is electrically connected to a set of contacts wherein each contact has a contact surface and a non-contact surface. Each contact surface of the contacts contains a recessed region filled with a first deposit of molding material. The die and the non-contact surfaces of the contacts are encapsulated with a second deposit of molding material. The semiconductor device is singulated from a molded lead frame by guiding a saw blade through recessed regions formed on the contact surface of the contacts. The molding material in the recessed regions creates a “buffer zone” which separates the path of the saw blade from the contact surface of the contacts.

Abstract: A method and apparatus is provided to identify defective laminate objects or package substrates having mounting sites for integrated circuit dies during the package substrate fabrication process. A hole is drilled or punched within the boundary of an individual package substrate contained within a larger laminate substrate and covered with a material layer coating composed of an opaque material such as a resist. The coating may then be selectively applied or removed at a later point during the fabrication process dependent upon whether the package substrate has been classified as defective or non-defective. After specific package substrates have been marked as defective, a light source and light collector are supplied to the fabrication process on opposite sides of the wafer. By shining the light source on the laminate substrate, defective package substrates can be identified by the passage of light through the hole which is no longer covered with resist.

Abstract: The present invention provides a circuit substrate containing a conductive circuit on an insulating base, an electrode for connection to an IC and an electrode for connection to a mother board substrate, which eliminates the step of bonding the film-like insulating base and the conductive circuit to simplify the manufacturing process.

Abstract: An electronic control unit having a housing, a substrate, particularly a hybrid, arranged in the housing and having an electronic control circuit. The electronic control unit also includes at least one device plug secured to the housing having contact elements that are electrically conductively connected to the control circuit of the substrate. A second substrate is arranged in the housing, spatially separated from the first substrate. At least one power component disposed in the housing and, electrically connected to the control circuit on the first substrate. One connecting printed circuit trace disposed in housing and conductively connected to the power component. The connecting printed circuit trace are conductively connected to a contact element, conducting power currents, of the device plug. Using the arrangement, in the event of a large number of contact elements in a device plug, the electrical connecting of the contact elements to the substrate can be simplified.

Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.

Abstract: A terminal mounting structure for a printed circuit board according to the present invention comprises a printed circuit board having a wiring pattern and a slit formed in an end face of the board and a terminal connected to the wiring pattern on the board, the terminal being provided with a holding portion having first and second clamp pieces and a connection piece for connection between both clamp pieces, the connection piece being inserted into the slit formed in the printed circuit board to position the terminal with respect to the printed circuit board, and the first and second clamp pieces being connected to the wiring pattern.

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant.A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Abstract: An electrically grounded semiconductor structure is embedded in a non-conductive packaging material, without employing any electrical leads of the semiconductor structure as an electrical path and without damaging the semiconductor structure. The desired grounding connection is obtained by physically removing a portion of the non-conductive packaging material from a rear portion of the semiconductor structure, replacing the removed non-conductive material by a conformable electrically conductive material, and then electrically contacting this conformable electrically conductive material to a grounding element. In another aspect of the invention, a portion of the non-conductive packaging material is removed from a rear portion of the semiconductor structure and a metallic element such as a pin or a spring is disposed to make contact between the exposed portion of the semiconductor structure and the grounding element.

Abstract: A modular miniature circuit built entirely within the case of the module without a primary printed circuit board conventionally used as a bottom support for the circuit component. The circuit components are mounted on the inside of the case and the leads of the components are attached directly to the module's terminals, greatly reducing lead inductance. The elimination of the primary PC board results in a substantial reduction in cost and physical size and the reduction in lead lengths results in a significant enhancement of high frequency performance. The "flip chip" construction provides a flat surface for pick up by automatic assembly equipment without the added cost of a cover.

Abstract: A package for mounting an integrated circuit chip to a circuit board or the like is provided. The package includes a chip carrier which has a metal substrate including first and second opposed faces. A dielectric coating is provided on at least one of the faces, which preferably is less than about 20 microns in thickness, and preferably has a dielectric constant from about 3.5 to about 4.0. Electrical circuitry is disposed on the dielectric coating, said circuitry including chip mounting pads, connection pads and circuit traces connecting the chip mounting pads to the connection pads. An IC chip is mounted by flip chip or wire bonding or adhesive connection on the face of the metal substrate which has the dielectric coating thereon. In any case, the IC chip is electrically connected to the chip mounting pads either by the solder ball or wire bond connections.

Abstract: A solder ball array package has a mould gate tape that is attached on top of a portion of the top surface of a leadless circuit carrying insulating substrate and on top of a portion of the top metallization pattern. The mould gate tape, which is optionally removable after completion of the moulding process, is such that it does not interfere with the design of the top side metallization pattern.

Abstract: A multilayer wiring system for preventing the generation of fixing failure due to an organic residue, eliminating an increase in the number of processes and reducing an area necessary for bonding of the cap and its fabrication method. The multilayer wiring board includes at least one wiring layer made of a conductor, at least one insulating layer made of an organic matter and a board. The wiring layer and the insulating layer are alternately laminated on the board and a cap is provided for covering the insulating layer and the wiring layer. The wiring layer has a wiring pattern for forming a wiring and a frame pattern for surrounding the wiring pattern. This frame pattern includes vent holes. The insulating layer has a shield structure made of an inorganic matter around the outer peripheral portion thereof and/or in the interior thereof. The shield structure is formed of the frame patterns continuously connected to each other and the cap is joined to an uppermost layer of the shield structure.

Abstract: A power module with leads extending upwardly. The circuit components and connections of the power module are arranged upon a substrate having interface leads attached thereto extending away from the undersurface of the substrate. The interface leads extend through openings in a form fitting molded case. The case has an open center region to facilitate performance of final assembly steps upon the module and is subsequently covered with a rugged lid and is encapsulated with a suitable potting material. The interior of the module is filled with a gel to provide moisture-proof protection.

Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.

Abstract: An electronic assembly (1) having at least one semiconductor die (2) with external electrodes (3) has a foldable electrically insulating substrate (4) supporting a plurality of conductive leads (5) connected and mounted to respective ones of the electrodes (3). A plurality of external connectors (11) supported by the substrate (4) are electrically coupled to respective ones of the leads (5). The substrate (4) is folded at least once into a folded position to form at least two opposite facing surfaces (8, 9) with an adhesive and the die (2) at least partially sandwiched therebetween. The adhesive bonding the substrate (4) to the die (2) maintains the substrate (4) in the folded position.

Abstract: A leadless ceramic chip carrier useful in surface mounting of SAW devices includes electrically conductive vias and metalization between input and output bond pads for improved crosstalk suppression between input and output device connections. A protrusion extending from a top layer of a multilayer ceramic carrier provides additional electrical contact to a package seal brazed thereto. The vias are positioned between input and output bond pads and connect the metalized protrusion to package ground pads through contact with multiple metalized layers of the package for enhancing the electrical connection between the package Kovar seal ring and customer accessed ground pads. For further suppression of crosstalk, bond pads within the package for connection to the SAW device are spaced at a greater distance from each other than their corresponding pads on the package bottom surface thus maintaining an optimum spacing for package connection to printed circuit board pads for minimizing thermal mismatch effects.

Abstract: A flip chip on chip method for forming a flip chip assembly including a first flip chip; a second flip chip directly connected to the top of the first flip chip; and electrically conductive epoxy means disposed between the second flip chip and the top of the first flip chip to form an electrical connection between the first flip chip and the second flip chip. In another preferred embodiment, a method for forming a flip chip assembly including a plurality of semiconductor chips where the plurality of chips are vertically interconnected on top of one another to form an electrically interconnected stack of chips; a flip chip directly connected to the top chip of the stack of chips; and electrically conductive epoxy means disposed between said flip chip and said top chip to form an electrical connection between the flip chip and the top chip.

Abstract: A leadframe for semiconductor devices is characterized in that the edge of the paddle has the shape of inclined plane which facilitate the silver epoxy to fill up the gap near the edge of the epoxy. The inclined plane on the paddle can also prevent the excessive silver epoxy from leaking to the bottom side of the paddle, which may cause delamination due to the poor adhesion between silver epoxy and plastic resin. Therefore the leadframe of the present utility can prevent moisture from accumulating within the package and the problem of pop corn.

Abstract: The radio frequency module of the present invention includes an insulating substrate having a first metal film on a first principal surface thereof and a second metal film on a second principal surface thereof opposed to the first principal surface and a semiconductor device. The semiconductor device is thermally and electrically coupled to the second metal film, and a thickness of the second metal film is larger than that of the first metal film.

Abstract: A mounting socket for a semiconductor package has socket leads that contact the semiconductor package's external leads. The semiconductor package has a package body surrounding a semiconductor chip, as well as internal and external leads. The external leads are formed in an ingot shape and project outwardly from the package body, and are adapted to connect with the socket leads or external terminals. The external leads contact external walls of the package body, thereby preventing undesired bending or breaking of the leads when the package is handled. Fixing and reworking of the package in the socket is easy, since the semiconductor package is inserted into grooves in the socket. It is possible to stack-mount or side-by-side-mount the package, depending on the socket shape, thus improving socket density and making the arrangement suitable for miniaturization.

Abstract: A lead frame structure and semiconductor package using the same and fabrication method thereof is provided that decreases noise by providing prescribed impedances for leads of a lead frame. The lead frame structure for the semiconductor package includes a paddle, a plurality of leads regularly aligned outside the paddle, and upper and lower dielectric adhesive layers sandwiching the plurality of leads. Upper and lower dielectric layers are attached on an upper surface of the upper dielectric adhesive layer and a lower surface of the lower dielectric adhesive layer. Upper and lower metallic polar plates formed on an upper surface of the upper dielectric layer and a lower surface of the lower dielectric layer.

Abstract: A carrier element for a semiconductor chip, in particular to be built into smart cards. The carrier element has a substrate that carries the chip and a stiffening sheet which also carries the chip and has a recess for receiving the chip and its connection leads therein. An edge of the recess is provided with a frame formed integrally from the sheet.

Abstract: A chip scale package for packaging an IC chip includes a package frame displaced from the side and bottom surfaces of the IC chip by a predetermined gap and a pair of leads symmetrically extending in opposite directions. Each lead has an inner lead portion coupled to a bonding point on the top surface of the IC chip, and an outer lead portion bent and contoured in such a way that to follow the shape of the outside surface of the package frame. The lead further includes a connecting segment extending between the inner lead portion and the outer lead portion. Under heat induced stress, an angle between the connecting segment and the wall of the package frame changes causing displacement of the IC chip from its original position, and the gap between the surfaces of the IC chip and the package frame absorbs deviations in position of the IC chip, to cushion the stress effect.

Abstract: A micro-dimensional coupling conductor with a shape that is customized for a particular electronic device. A fabrication method is used in which the physical dimensions of the conductor are precisely controlled with photolithographic techniques, resulting in a conductor that is more precisely tuned to the operating frequency of the device. The conductor is fabricated on an SiO.sub.2 substrate using vacuum deposition techniques. After fabrication, the conductor is separated from the SiO.sub.2 substrate by dissolving the SiO.sub.2. Alternatively, the conductor may be fabricated on a Teflon.TM. substrate. The use of a Teflon substrate allows a user to remove the conductor from the substrate by applying a small mechanical force to the conductor.

Abstract: Procedure for producing a transponder unit (55) provided with at least one chip (16) and one coil (18), and in particular a chip card/chip-mounting board (17) wherein the chip and the coil are mounted on one common substrate (15) and the coil is formed by installing a coil wire (21) and connecting the coil-wire ends (19, 23) to the contact surfaces (20, 24) of the chip on the substrate.

Abstract: A semiconductor package is disclosed, including: (a) two semiconductor chips having a plurality of bonding pads; (b) an insulating circuit film having (i) an insulating base film with a plurality of through holes, (ii) a plurality of first metal lines formed on upper and lower faces of the base film, (iii) a plurality of protruding, conductive inner pads which are respectively formed on the first metal lines, being respectively connected to said bonding pads of each semiconductor chip, (iv) a plurality of protruding, conductive outer pads which are formed on the first metal line at a predetermined interval from the plurality of inner pads, and (v) a plurality of second metal lines formed along wall surface of the plurality of through holes to connect to the inner pads of each semiconductor chip, for electrically connecting inner pads each other which are positioned at the upper and lower surfaces of the base film, (c) a lead frame including an inner lead for connecting the outer pads of the insulating circuit

Abstract: A semiconductor chip package includes a semiconductor chip having surfaces and contacts, a layer of a moisture-permeable material bonded to one surface of the chip and a moisture-impermeable encapsulant overlying the moisture-permeable material and at least partially surrounding the chip. The package has exposed exterior surfaces and terminals on at least one of the exposed exterior surfaces which are electrically connected to the contacts. The moisture-permeable material extends to at least one of the exposed exterior surfaces so that moisture may be vented through the moisture-permeable material and out of the package. In certain embodiments, the moisture-permeable material includes a compliant layer having silicone and the moisture-impermeable material includes an epoxy.

Abstract: An electronic module or package is disclosed for providing high reliability and high performance operation. The package comprises a hermetically sealed enclosure having a metallic baseplate and a ceramic cover, and containing one or more circuits or devices therein which typically are power rectifiers, bridges or power control circuitry. One or more power terminals are disposed on a terminal block compliantly supported on or above the baseplate, the terminals extending through the cover in hermetically sealed manner. Signal or control terminals may also be disposed on a terminal block compliantly supported on or above the baseplate, these terminals also extending through the cover in hermetically sealed manner. An adapter plate may be mounted on the cover and containing a plurality of terminals connected to the module terminals. The terminals of the adapter plate can be in any configuration to suit user requirements without requiring a change in the terminal configuration of the module itself.

Abstract: In a method for manufacturing an electronic apparatus, an electronic component is mounted on an organic substrate within its cavity. The electronic component is sealed by a concave molded resin enveloper filled into the cavity.

Abstract: A power distribution assembly (100) that comprises at least two direct current power supplies (106, 107), at least three signal splitter modules (102-104), wherein each signal splitter modules comprises a signal splitter and a radio frequency amplifier, a centerplane board (110) coupled to the at least three signal splitter modules (102-104) and to the at least two direct current power supply modules(106, 107), wherein the centerplane board (110) provides a plurality of electrical paths among a plurality of modules contained in the power distribution assembly (100), and a chassis (101) to which the modules (102-104, 106, 107) and the centerplane board (110) are mounted, and has an overall volume of at most 0.009 cubic meters.

Abstract: A consolidation point enclosure employing a two piece design in which a cover subassembly is removably mounted to a mounting plate. The cover subassembly includes notches that allow cable to enter the consolidation point enclosure. When the cover subassembly is removed, cables can be routed to the consolidation point enclosure without pulling the cables through restrictive openings. The cover subassembly is then mounted to the mounting plate with the notches straddling the cables. The invention also includes a patch panel mounting assembly that is hingedly mounted to the mounting plate. A pair of spring loaded pins secure the patch panel mounting assembly in an open position which facilitates access to the devices mounted in the patch panel mounting assembly. In alternative embodiments, the mounting plate includes additional support plates for mounting 110 type or 66 type cabling products.

Abstract: A plastic housing assembly is constructed with a non-plateable plastic wall portion (101), and a plateable plastic wall portion (107) positioned abutting (109) the non-plateable plastic wall portion (101). The plateable plastic wall portion (107) has a via (115) disposed therethrough for thermally coupling an outer surface (111) to an inner surface (113). A heat-generating component (119) is disposed coupled to the second inner surface (113). The via (115) is preferably plated with metal so that heat produced from the heat-generating component (119) is conducted away from the inner surface (113) to the outer surface (111).

Abstract: A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semiconductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the substrate, and the thin-film semiconductor chip and the substrate are wired to each other by printing.

Abstract: A stacked circuit assembly is provided for mounting memory modules in close proximity to an integrated circuit. The assembly includes an integrated circuit mounted on a printed circuit board and at least one stacked printed circuit board mounted in substantially parallel arrangement with respect to the printed circuit board on which the integrated circuit is mounted. A memory module is mounted for electrical connection on a surface of the stacked printed circuit board and an interface connector is mounted on facing surfaces of the printed circuit board and the stacked printed circuit board, thereby providing means for both mechanical and electrical connection between the boards. The integrated circuit and the memory module are mounted in parallel relationship with respect to one another for electrical interconnection through the boards and the interface connectors, thereby reducing the physical distance between the integrated circuit and the memory module.

Abstract: An electronic assembly which includes a heat sink. The assembly includes first and second integrated circuit packages that are mounted to a substrate. The heat sink may be in direct thermal contact with the first integrated circuit package and include a channel that is located adjacent to the second integrated circuit package. The channel allows air to flow across the second integrated circuit package and remove heat generated within the package.

Abstract: A bottom lead package is capable of increasing a memory capacity for a mounting position on a mother board by stacking several semiconductor packages such that exposed surfaces of leads on upper and lower surfaces of the package are aligned. The package includes a semiconductor chip, a plurality of lower leads attached to the lower side of the chip by an adhesive, a plurality of upper leads attached to the upper side of the chip by an adhesive and to the upper surfaces of the lower leads, wherein metal wires electrically connect the upper leads with a plurality of chip pads formed on the chip, and wherein a molding section packages the chip, the metal wires and the upper and lower leads, such that the upper and lower surfaces of the upper and lower leads, respectively, are externally exposed.

Abstract: A flip chip and a flip chip package are shielded from alpha particles emitted by lead in the solder bumps used to form the electrical connection between the flip chip and a substrate. This is accomplished by coating the solder bumps with a layer of alpha particle absorbing material or by providing a suitable amount of alpha particle absorbing material in the underfill material between the flip chip and the substrate. Methods of forming the coating the solder bumps include electroless coating, as well as a method involving a) the deposition of a layer of thick resist in a pattern suitable for the formation of solder bumps; b) the deposition of a layer of alpha particle absorbing material; c) the deposition of a layer of solder; d) removal of excess solder and alpha particle absorbing material; and e) the removal of the thick resist layer.

Abstract: A microelectronic assembly (10) includes an integrated circuit die (12) that is mounted to a printed circuit board (14). The integrated circuit die (12) overlies the printed circuit board (14) and includes an active face (26) that faces the printed circuit board (14) and is spaced apart therefrom by a gap (30). A plurality of solder bump interconnections (32) extend across the gap (30) and connect a plurality of board bond pads (22) with a plurality of die bond pads (28). A polymeric precursor (13) is dispensed onto the printed circuit board (14) about the integrated circuit die (12) and is curable to form a polymeric encapsulant (16). The polymeric precursor (13) is drawn into the gap (30) and forms a fillet (34) overlying the printed circuit board (14). A frame (18) is embedded in the fillet (34), not in direct contact with the board (14), and the polymeric precursor (13) is heated to cure the polymeric precursor (13) to form a polymeric encapsulant (16).

Abstract: A semiconductor device has a multi-layered wiring structure having a conductor layer to be electrically connected to a packaging substrate, the structure being provided on a circuit formation surface of a semiconductor chip; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein the multi-layered wiring structure includes a buffer layer for relieving a thermal stress produced between the semiconductor chip and the packaging substrate, after packaging thereof, and multiple wiring layers.

Abstract: A multi-chip memory module comprises multiple standard, surface-mount-type memory chips stacked on top of each other, and a pair of printed circuit boards mounted on opposite sides of the memory chips to electrically interconnect the memory chips. Each printed circuit board has vias that are positioned to form multiple rows, with each row of vias used to connect the printed circuit board to a respective memory chip. The vias falling along the bottom-most row of each printed circuit board are also exposed and are used to surface mount the multi-chip module to pads of a memory board.