Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

Abstract: A display device includes: a display panel; a circuit board disposed on a lower surface of the display panel; and an adhesive layer disposed between the circuit board and the lower surface of the display panel. An area of the circuit board that has a roughness higher than a predetermined reference roughness does not overlap the adhesive layer.

Abstract: The present invention relates to a production of electro-conductive traces on the surface of polymeric articles using laser excitation for the areas to be metallised, followed by activation of the laser-treated areas with a metal salt solution, the article is later rinsed in distilled water, and the activated areas are metallised in the chemical plating bath. The aims of the invention are to produce cost-effective conductive traces of the circuits for the application in 3D moulded interconnect devices, to increase the quality of the circuit traces improving the selective metallization process. An irradiation dose and scanning parameters for the surface excitation are chosen experimentally, provided that a negative static charge appears on the surface of the laser-irradiated areas. The chosen parameters ensure that any surface degradation of the polymer is avoided.

Abstract: A copper clad laminate and a method to manufacture the same are provided. In one general aspect, a copper clad laminate include a first copper clad layer on a first surface of an insulating layer, and a second copper clad layer on a second surface of the insulating layer. The second copper clad layer includes polymer resin layer, a second copper layer, and a carrier foil layer.

Abstract: A substrate (1, 10) for electrical circuits, comprising at least one metal layer (2,3, 14) and a paper ceramic layer (11), which is joined face to face with the at least one metal layer (2,3, 14) and has a top side and bottom side (11a, 11b), wherein the paper ceramic layer (11) has a large number of cavities in the form of pores. Especially advantageously, the at least one metal layer (2, 3, 14) is connected to the paper ceramic layer (11) by means of at least one glue layer (6, 6a, 6b), which is produced by applying at least one glue (6a?, 6a?, 6b?, 6b?) to the metal layer (2,3, 14) and/or to the paper ceramic layer (11), wherein the cavities in the form of pores in the paper ceramic layer (11) are filled at least at the surface by means of the applied glue (6a?, 6a?, 6b?,6b?).

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

Abstract: An electrochemical biosensor includes a substrate, a plurality of layered active metal parts, a plurality of layered electrodes, a reaction confinement layer, an electrochemical reactive layer and a cover piece. The substrate is formed with through holes each of which is defined by an interior wall surface and penetrates top and bottom surfaces. Each of the layered active metal parts is formed at least upon a respective one of the interior wall surfaces. The layered electrodes are formed on the layered active metal parts. The reaction confinement layer confines a reactor space over a region where the through holes are formed. The electrochemical reactive layer is disposed in the reactor space and is electrically coupled to the layered electrodes.

Abstract: A length- and width-deformable printed circuit board includes a first conductive circuit layer, an elastic film, and a plurality of conductive via holes. The first conductive circuit layer includes a plurality of first conductive circuits. The plurality of first conductive circuits is embedded in the elastic film. The first conductive circuit layer have a plurality of first honeycomb hole. Each of the plurality of conductive via holes corresponds to one of the first honeycomb holes.

Abstract: A package substrate includes a dielectric layer, a first circuit layer, a second circuit layer and at least one electrically conductive pole. The dielectric layer includes a first side and a second side opposite to the first side. The first circuit layer is located at the first side of the dielectric layer, and includes a plurality of spaced first circuit patterns embedded into the dielectric layer. The second circuit layer is located at the second side of the dielectric layer, and includes a plurality of spaced second circuit patterns located on the second side the dielectric layer. The electrically conductive pole electrically couples the first circuit layer to the second circuit layer. Each of the first circuit patterns has an extension direction from the first side toward the second side, and has widths gradually decreasing along the extension direction.

Abstract: The present invention relates to a new method of light induced photopolymerization under mild irradiation conditions, copper initiator complexes to be used in such method and a polymers obtained by such method.

Abstract: A motor wiring structure of the present invention relates to motor wiring for supplying electric power to coils which are respectively wound around split cores provided in a stator. The motor wiring structure includes a power supply-side terminal disposed on a power supply side, multiple coil connection-side terminals configured to be connected respectively to winding wire terminals of the coils, and multiple conductor wires each independently connecting the power supply-side terminal and one of the multiple coil connection-side terminals to each other. Moreover, the motor wiring structure includes a positioning and heat-dissipating protrusion which is provided to the coil connection-side terminal, and which is configured to position the coil connection-side terminal with respect to the stator and dissipate heat during thermal crimping with the coil.

Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.

Abstract: A method of manufacturing an inductor, includes: forming a coil pattern on a substrate by forming a conductive pattern on the substrate then growing the conductive pattern by plating; removing, if a plating residue is adhering to the coil pattern, the plating residue from the coil pattern; and outputting a cleaning request alarm that requests a plating bath to be cleaned if a number of times the plating residue has been removed or an amount of plating residue that has been removed exceeds a first threshold.

Abstract: Electroless copper plating baths include alternative reducing agents to the conventional reducing agents currently used in the electroless plating industry. The electroless copper baths are stable and deposit a salmon bright copper deposit on substrates. Exclusion of many environmentally unfriendly conventional reducing agents enables environmentally friendly electroless copper plating baths.

Abstract: Liquid compositions useful for the cleaning of residue and contaminants from a III-V microelectronic device material, such as InGaAs, without substantially removing the III-V material. The liquid compositions are improvements of the SC1 and SC2 formulations.

Abstract: A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion. The bottom portion is surrounded by a molding compound and the top portion is not surrounded by a molding compound. The method includes depositing and forming a liquid molding compound around an intermediate solder joint using release film, and then etching the molding compound to a reduced height. The resulting solder joint has no waist at the interface of the molding compound and the solder joint. The molding compound has a greater roughness after the etch, greater than about 3 microns, than the molding compound as formed.

Abstract: Provided is a printed circuit board, including: a circuit pattern or a base pattern formed on an insulating layer; and a plurality of metal layers formed on the circuit pattern or the base pattern, wherein the metal layers includes: a silver metal layer formed of a metal material including silver; a first palladium metal layer formed at a lower part of the silver metal layer; and a second palladium metal layer formed at an upper part of the silver metal layer.

Abstract: The present invention relates to a polyimide resin surface modifier which modifies the surface of a polyimide resin to permit easy absorption of metal ions, and a surface-modifying method for polyimide resins using the same. The surface modifier contains an alkali component, an organic solvent having hydroxy groups and a boiling point of 120° C. or higher, and a water content of 0-10% by weight. The surface-modifying method includes a printing process wherein a predetermined pattern is printed on the surface of a polyimide resin substrate using the polyimide resin surface modifier, an organic solvent-removing process wherein an organic solvent in the polyimide resin surface modifier pattern-printed on the surface of said polyimide resin substrate is removed and a water-treatment process wherein said polyimide resin surface modifier after removing the organic solvent is brought into contact with water.

Abstract: An electronic component that includes a resistive element. A Ni concentration of a resistive thin film of the resistive element at a side where there is a connection interface with a connection electrode is higher than the concentration of Ni at the side opposite to the interface.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.

Abstract: A semiconductor device has semiconductor die mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. A channel is formed in a back surface of the die, either while in wafer form or after mounting to the carrier. The channel corresponds to a specific heat generating area of the die. The channel can be straight or curved or crossing pattern. The carrier is removed. An interconnect structure is formed over the encapsulant and die. The semiconductor die are singulated through the encapsulant. A TIM and heat sink are formed over the channel and encapsulant. Alternatively, a conformal plating layer can be formed over the channel and encapsulant. A conductive via can be formed through the encapsulant, and TSV formed through the die. The die with channels can be mounted over a second semiconductor die which is mounted to the interconnect structure.

Abstract: Methods are provided for fabricating three-dimensional electrically conductive structures. Three-dimensional electrically conductive microstructures are also provided. The method may include providing a mold having at least one microdepression which defines a three-dimensional structure; filling the microdepression of the mold with at least one substrate material; molding the at least one substrate material to form a substrate; and depositing and patterning of at least one electrically conductive layer either during the molding process or subsequent to the molding process to form an electrically conductive structure. In one embodiment, the three-dimensional electrically conductive microstructure comprises an electrically functional microneedle array comprising two or more microneedles, each including a high aspect ratio, polymeric three dimensional substrate structure which is at least substantially coated by an electrically conductive layer.

Abstract: Systems and methods for reducing overhang on electroplated surfaces of printed circuit boards are described. One such method includes applying a first resist layer on a substrate having a first copper layer, applying a first image to the first resist layer, developing the first resist layer in accordance with the first image, applying a second copper layer on the first copper layer, electroplating a first metallic layer on the second copper layer, removing the first resist layer, etching a portion of the first copper layer, removing the first metallic layer, depositing a third copper layer on a surface of the assembly, applying a second resist layer on the third copper layer, applying a second image to the second resist layer, developing the second resist layer in accordance with the second image, electroplating a preselected metal layer on the third copper layer, removing the second resist layer, and etching a portion of the third copper layer.

Abstract: The present invention relates to a method for manufacture of fine line circuitry in the manufacture of printed circuit boards, IC substrates and the like. The method utilizes a first conductive layer on the smooth surface of a build-up layer and a second conductive layer selected from electrically conductive polymers, colloidal noble metals and electrically conductive carbon particles on the roughened walls of at least one opening which are formed after depositing the first conductive layer.

Abstract: A method of making a metal-electrodeposited insulator substrate includes: forming first and second continuous conductor parts of a patterned conductive base layer on a pattern-forming surface of an insulator substrate; subjecting an assembly of the patterned conductive base layer and the insulator substrate to electroplating so as to simultaneously form first and second electroplating parts of a patterned electroplating layer on the patterned conductive base layer; and removing a sacrificial portion of the first continuous conductor part and a sacrificial portion of the first electroplating part from the insulator substrate.

Abstract: A printed circuit board includes a first seed layer, a second seed layer, and a metal layer. The first and second seed layers are disposed on a base substrate and spaced apart from each other. The metal layer covers the first and second seed layers except a first side of the first seed layer and a second side of the second seed layer. The first side of the first seed layer faces the second side of the second seed layer.

Abstract: A system and method for “pixelating” a three-dimensional circuit structure into a three-dimensional matrix of cubes that are located with respect to a coordinate system. The design step is typically performed on a conventional computer using computer aided design software that pixelates the proposed circuit structure into an array of uniformly sized cube. The fabrication process involves adding and subtracting bulk materials from the individual cubic positions within the pixelated representation of the circuit structure. Various existing and new techniques can be used to add or subtract bulk materials as the cubic positions within the matrix to construct the circuit structure.

Abstract: A method for fabricating a conductive trace structure includes the steps: forming a first metal layer on a non-conductive substrate; removing a part of the first metal layer to expose the non-conductive substrate so as to form the first metal layer into a plating region and a non-plating region, the plating region being divided into at least two trace-forming portions and at least one bridge portion; forming a second metal layer on the plating region by electroplating the plating region using one of the trace-forming portions and the bridge portion as an electrode; and removing the bridge portion and the second metal layer formed on the bridge portion.

Abstract: Stable tin-free palladium catalysts are used to metalize through-holes of printed circuit boards. A stabilizer is included in the catalyst formulation which prevents precipitation and agglomeration of the palladium.

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board according to a preferred embodiment of the present invention includes a base substrate; a through via formed to penetrate through the base substrate; and circuit patterns formed on one side and the other side of the base substrate and formed to be thinner than an inner wall of the through via.

Abstract: A method of forming a metal pattern includes forming a precursor layer including a metal precursor on a substrate, irradiating a light on the precursor layer to form a metal seed layer having a predetermined pattern, and electroless-plating the metal seed layer to form a metal pattern layer.

Abstract: A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes a) providing a blank printed wiring member comprising a copper foil laminated to a dielectric substrate; b) masking the blank printed wiring member to protect regions of the copper foil; c) removing copper in unprotected regions of the blank printed wiring member to form a patterned printed wiring member including contact pads and connector pads; d) depositing a nickel coating on the patterned printed wiring member; e) electrolytically depositing a hard gold layer on the nickel coating; and f) depositing palladium on a surface of the hard gold layer to improve bondability of the contact pads while preserving wear resistance of the connector pads.

Abstract: A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction.

Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Abstract: Disclosed herein are a printed circuit board and a manufacturing method thereof. In the manufacturing method of the printed circuit board according to the exemplary embodiment of the present invention, primary copper plating layers are first formed on each of upper and lower surface portions of a core layer in a symmetrical structure, an insulating layer is formed on the primary copper plating layer of the upper surface side, and a secondary copper plating layer is continuously formed on the primary copper plating layer of only the lower surface side. Therefore plating thicknesses required for the front side and the rear side in an asymmetric structure may be uniform to have no plating deviation and non-peeling of an insulating layer (a dry film) for a circuit protection is prevented to have no short defect, thereby making it possible to form a fine circuit pattern.

Abstract: An apparatus and system for stirring liquid inside a flow cell. In one implementation, the apparatus includes a rotatable disc configured to receive liquid at a top side of the disc and distribute the liquid substantially evenly around a periphery of the flow cell. The disc has a triangular cross sectional area. The apparatus may further include a set of fins attached to a bottom side of the disc, wherein the set of fins is configured to draw the liquid from the periphery of the flow cell into the center of the flow cell.

Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

Abstract: A method for manufacturing a sensing electrical device includes the following steps; (a) forming a conductive trace on an insulating substrate; (b) placing the insulating substrate with the conductive trace in a mold cavity of a mold; (c) injecting an insulating material into the mold cavity to encapsulate the conductive trace to form an injection product; and (d) removing the injection product from the mold cavity.

Abstract: A method for forming electrical traces on a substrate includes the steps of: providing a substrate; printing an ink pattern using an ink on the substrate, the ink including a aqueous medium containing silver ions and a heat sensitive reducing agent; heating the ink pattern to reduce silver ions into silver particles thereby forming an semi-finished traces; and forming a metal overcoat on the semi-finished traces by electroless plating thereby obtaining patterned electrical traces.

Abstract: The present invention relates to a pattern-forming composition used to form a conductive circuit pattern. The pattern-forming composition comprises Cu powders, a solder for electrically coupling the Cu powders, a polymer resin, a curing agent and a reductant. According to the present invention, a circuit pattern having superior conductivity can be formed at low cost.

Abstract: The invention relates to a prepreg, obtained by impregnating a base material with an epoxy resin composition containing an epoxy resin (A), a curing agent (B), an accelerator (C), a phenoxy resin (D), and an inorganic filler (E) and semi-hardening the impregnated material, wherein the inorganic filler (E) has an average particle diameter of 3 ?m or less. When a circuit with a narrow wire distance is formed on a surface of a insulator substrate composed of such a prepreg by using a method of forming the circuit by plating process, an amount of the plating remaining on the insulator substrate surface at the circuit contour periphery can be reduced. As a result, it leads to stabilization of inter-circuit insulation resistance and increase in a yield during production of printed wiring boards.

Abstract: A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

Abstract: An apparatus and system for stirring liquid inside a flow cell. In one implementation, the apparatus includes a rotatable disc configured to receive liquid at a top side of the disc and distribute the liquid substantially evenly around a periphery of the flow cell. The disc has a triangular cross sectional area. The apparatus may further include a set of fins attached to a bottom side of the disc, wherein the set of fins is configured to draw the liquid from the periphery of the flow cell into the center of the flow cell.

Abstract: A copper electroplating bath that includes an aqueous solution that comprises a copper salt and at least one acid and a container that comprises a copper salt in solid form, is disclosed. The container supplies copper ions to the aqueous solution to maintain the copper ion concentration of the aqueous solution at saturation levels while retaining the copper salt in solid form within the container.

Abstract: A method for producing a layer on a molded article. The method includes providing a formable film. Galvanically catalytically active nuclei are anchored to at least one region of the formable film provided for the layer. The formable film is shaped so as to form the molded article. A galvanic deposition is performed on a surface of the molded article so as to bond the nuclei to form the layer.

Abstract: A method for manufacturing a multilayer printed circuit board including providing a core substrate having a penetrating-hole, forming an electroless plated film on a surface of the substrate and an inner wall surface of the penetrating-hole, electrolytically plating the substrate while moving with respect to the surface of the substrate an insulating member in contact with the surface of the substrate such that an electrolytic plated film is formed on the electroless plated film, an opening space inside the penetrating-hole is filled with an electrolytic material, and a through-hole conductor structure is formed in the penetrating-hole, forming an etching resist having an opening pattern on the electrolytic plated film, and removing an exposed pattern of the electrolytic plated film exposed by the opening pattern and a pattern of the electroless plated film under the exposed pattern such that a conductor circuit is formed on the surface of the substrate.

Abstract: The invention provides a method of forming a metallic pattern including: (a) forming, in a pattern form on a substrate, a polymer layer which contains a polymer that has a functional group that interacts with an electroless plating catalyst or a precursor thereof; (b) imparting the electroless plating catalyst or precursor thereof onto the polymer layer; and (c) forming a metallic film in the pattern form by subjecting the substrate having the polymer layer to electroless plating using an electroless plating solution, wherein the substrate is treated using a solution comprising a surface charge modifier or 1×10?10 to 1×10?4 mmol/l of a plating catalyst poison before or during the (c) forming of the metallic film. The invention further provides a metallic pattern obtained thereby. Furthermore, the invention provides a printed wiring board and a TFT wiring board, each of which uses the metallic pattern as a conductive layer.

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract: In order to be able to produce high density circuits on a dielectric substrate wherein the conductor lines of said circuit have a good adhesion to the dielectric substrate surface, a method is provided which comprises the following method steps: a) providing an auxiliary substrate having two sides, at least one of said sides having an electrically conductive surface; b) treating at least one of the at least one electrically conductive surface with at least one release layer forming compound, the at least one release layer forming compound being a heterocyclic compound having at least one thiol group, c) forming a patterned resist coating on at least one of said at least one electrically conductive surface which has been treated with said at least one release layer forming compound, the patterned resist coating having at least one resist opening thereby exposing the electrically conductive surface; d) forming an electrically conductive pattern in the at least one resist opening by electrodepositing a metal on

Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.