Coating Predominantly Semiconductor Substrate (e.g., Silicon, Compound Semiconductor, Etc.) Patents (Class 205/157)
  • Patent number: 10475742
    Abstract: A method of forming a semiconductor device structure includes: forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and wherein the forming the first conductive structure includes manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density and such that the first conductive structure has a resistance which is substantially the same as the second conductive structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Patent number: 10438849
    Abstract: An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 8, 2019
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Jie Zhou, Guannan Chen, Michael W. Stowell, Bencherki Mebarki, Mehul Naik, Srinivas D. Nemani, Nikolaos Bekiaris, Zhiyuan Wu
  • Patent number: 10388804
    Abstract: Disclosed is a method of manufacturing a solar cell, the method including forming a tunneling layer over one surface of a semiconductor substrate, forming a semiconductor layer over the tunneling layer, forming a conductive area including a first conductive area of a first conductive type and a second conductive area of a second conductive type in the semiconductor layer, and forming an electrode including a first electrode connected to the first conductive area and a second electrode connected to the second conductive area. The forming of the conductive area includes forming a mask layer over the semiconductor layer, forming a doping opening corresponding to at least one of the first conductive area and the second conductive area in the mask layer using a laser, and performing doping using the doping opening.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 20, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Indo Chung, Juhong Yang, Eunjoo Lee, Mihee Heo
  • Patent number: 10283450
    Abstract: A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries. The forming the conductive structure includes: manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of an atomic migration ratio corresponding to values of the density of the twin boundaries.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Patent number: 10077505
    Abstract: A metal-film forming apparatus includes: an anode; a resin substrate having a surface on which a conductor pattern layer that serves as a cathode is formed; a solid electrolyte membrane that contains metal ions and is between the anode and the resin substrate, the solid electrolyte membrane contacting a surface of the conductor pattern layer when a metal film is formed; a power supply; and a conductive member that is arranged contacting the conductor pattern layer when the metal film is formed, such that a negative electrode of the power supply is electrically connected to the conductor pattern layer, the conductive member being detachable from the conductor pattern layer, wherein the metal ions are reduced to deposit metal that forms the metal film on the surface of the conductor pattern layer when the voltage is applied.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 18, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Motoki Hiraoka, Hiroshi Yanagimoto, Yuki Sato
  • Patent number: 9919526
    Abstract: A method for manufacturing a liquid discharge head includes a transferring step of transferring a dry film supported by a supporting member to a substrate having a hole, and a peeling step of peeling the supporting member off the dry film on the substrate. In the peeling step, the dry film is in contact with a wall surface defining the hole in the substrate.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: March 20, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuhiro Asai, Kenji Fujii, Keiji Matsumoto, Koji Sasaki, Kunihito Uohashi, Jun Yamamuro, Seiichiro Yaginuma, Masahisa Watanabe, Ryotaro Murakami
  • Patent number: 9911645
    Abstract: A method includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The method includes an adhesion layer formed in the dielectric layer and over the first metal layer, and the adhesion layer is a discontinuous layer. The method includes a second metal layer formed in the dielectric layer, and the adhesion layer is formed between the second metal layer and the dielectric layer. The second metal layer includes a via portion and a trench portion over the via portion, and the trench portion is wider than the via portion.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9899274
    Abstract: A method of forming an SOI fin using a porous semiconductor. The method may include forming a stack of semiconductor layers on a substrate, the stack includes a second semiconductor layer on a first semiconductor layer in a layered region; forming fins in the second semiconductor layer by etching a trench through an exposed portion of the of the second semiconductor layer; converting the first semiconductor layer into a porous semiconductor layer using a porousification process; and converting the porous semiconductor layer into an oxide layer.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Joel P. de Souza, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis
  • Patent number: 9881888
    Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Ming-Da Cheng, Chih-Hang Tung, Chung-Shi Liu
  • Patent number: 9816194
    Abstract: The uniformity of electroplating a metal (e.g., copper) on a semiconductor wafer is improved by using an electroplating apparatus having a flow-shaping element positioned in the proximity of the semiconductor wafer, wherein the flow-shaping element is made of a resistive material and has two types of non-communicating channels made through the resistive material, such that the electrolyte is transported towards the substrate through both types of channels. The first type of channels is not perpendicular to the plane defined by a plating face of the substrate. The second type of channels is perpendicular to the plane defined by the plating face of the substrate. The channels of the first and second type are substantially spatially segregated. In one embodiment a plurality of channels of the first type are located in the central portion of the flow-shaping element and are surrounded by a plurality of channels of the second type.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: November 14, 2017
    Assignee: Lam Research Corporation
    Inventors: Zhian He, Jian Zhou, Jingbin Feng, Jonathan D. Reid, Shantinath Ghongadi
  • Patent number: 9812344
    Abstract: A wafer processing system has a ring maintenance module for loading wafers into a chuck assembly, and for cleaning and inspecting the chuck assembly used in electroplating processors of the system. A shaft is attached to a rotor plate. A rotation motor rotates the shaft and a rotor plate on the shaft. A chuck clamp on an upper end of the shaft holds the chuck assembly onto the rotor plate. A lift motor raises and lowers the rotor plate and the shaft, to move open the chuck assembly for wafer loading and unloading, and to move the chuck assembly into different process positions. A swing arm having spray nozzles may be provided for cleaning the chuck assembly.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 7, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Jason Rye, Mario David Silvetti, Randy A. Harris, Bryan Puch, Vincent Steffan Francischetti, Satish Sundar
  • Patent number: 9773582
    Abstract: The present invention relates to a conductive composition containing a conductive metal powder and an epoxy resin component in which the conductive metal powder contains a metal flake and the epoxy resin component contains a polyfunctional epoxy resin having three or more epoxy groups.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: September 26, 2017
    Assignee: MITSUBOSHI BELTING LTD.
    Inventors: Taisuke Iseda, Masahiro Iwamoto
  • Patent number: 9761523
    Abstract: A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 ?m?1 to about 250 ?m?1.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Patent number: 9644288
    Abstract: Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten suspension mixture (e.g., including KOH (or KOH eutectic) and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: May 9, 2017
    Assignee: University of South Carolina
    Inventors: Tangali S. Sudarshan, Haizheng Song, Tawhid Rana
  • Patent number: 9644287
    Abstract: Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten mixture (e.g., including KOH and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: May 9, 2017
    Assignee: University of South Carolina
    Inventors: Tangali S. Sudarshan, Haizheng Song, Tawhid Rana
  • Patent number: 9418937
    Abstract: An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 ?m and a ratio of average grain size to thickness of less than 0.7.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Patent number: 9337514
    Abstract: Methods for reductively polymerizing vinylic based monomers from a solution thereof onto the surface of an electrode material, resulting in thin, electrically insulating solid-polymer electrolyte coatings strongly bound to the surface of the electrode material, are described. The strong bond permits a second electrode to be coated directly onto the solid-polymer electrolyte, thereby incorporating the required components for a Li-ion battery cell. At least one initiator species, which is readily reduced by accepting an electron from the electrode material, is included in electropolymerization deposition solution for permitting the polymerization of vinylic species that would otherwise not electrochemically polymerize without damage to either the electrode material or to the solvents employed.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: May 10, 2016
    Assignees: Colorado State University Research Foundation, Prieto Battery, Inc.
    Inventors: Derek C. Johnson, Amy L. Prieto, Matthew Rawls, Daniel J. Bates, C. Michael Elliott
  • Patent number: 9028666
    Abstract: Methods described herein manage wafer entry into an electrolyte so that air entrapment due to initial impact of the wafer and/or wafer holder with the electrolyte is reduced and the wafer is moved in such a way that an electrolyte wetting wave front is maintained throughout immersion of the wafer also minimizing air entrapment.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: May 12, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Manish Ranjan, Shantinath Ghongadi, Frederick Dean Wilmot, Douglas Hill, Bryan L. Buckalew
  • Patent number: 8991042
    Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Manabu Sakamoto, Tetsuya Shirasu, Naoki Idani
  • Patent number: 8992746
    Abstract: An apparatus for anodizing substrates immersed in an electrolyte solution. A substrate holder mounted in a storage tank includes a first support unit having first support elements for supporting, in a liquid-tight condition, only lower circumferential portions of the substrates, and a second support unit attachable to and detachable from the first support unit and having second support elements for supporting, in a liquid-tight condition, remaining circumferential portions of the substrates. A drive mechanism separates the first support unit and the second support unit when loading and unloading the substrates, and for connecting the first support unit and the second support unit after the substrates are placed in the substrate holder.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: March 31, 2015
    Assignees: Dainippon Screen Mfg. Co., Ltd., Solexel, Inc.
    Inventors: Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara, Takao Yonehara, Karl-Josef Kramer, Subramanian Tamilmani
  • Publication number: 20150068911
    Abstract: A copper plating apparatus according to an embodiment includes a plating tank configured to have a copper member and a plating member being disposed in an interior of the plating tank, a blocking film configured to partition the interior of the plating tank into an anode chamber where the copper member is to be disposed and a cathode chamber where the plating member is to be disposed, the blocking film being configured to transmit copper ions and not transmit an additive agent, a supply unit configured to supply the additive agent to the anode chamber, and a power supply configured to apply a voltage between the copper member and the plating member.
    Type: Application
    Filed: December 6, 2013
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Fumitoshi IKEGAYA, Toshiyuki MORITA
  • Patent number: 8968531
    Abstract: In an electro processor for plating semiconductor wafers and similar substrates, a contact ring has a plurality of spaced apart contact fingers. A shield at least partially overlies the contact fingers. The shield changes the electric field around the outer edge of the workpiece and the contact fingers, which reduces or eliminates the negative aspects of using high thief electrode currents and seed layer deplating. The shield may be provided in the form of an annular ring substantially completely overlying and covering, and optionally touching the contact fingers.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: March 3, 2015
    Assignee: APPLIED Materials, Inc.
    Inventors: Gregory J. Wilson, Paul R. McHugh
  • Patent number: 8968532
    Abstract: A substrate plating processor has a vessel on a support structure and a head support fixed in place relative to the support structure. A head having a rotor is attached to the head support. A lifter associated with the head support moves the head into and out of engagement with the vessel. An alignment assembly attachable to the rotor has at least one sensor adapted to detect a position of an inside surface of the vessel when the head is engaged with the vessel. The sensor may be a physical contact sensor positioned to contact the inside surface of the vessel.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: March 3, 2015
    Assignee: APPLIED Materials, Inc.
    Inventor: Bryan Puch
  • Patent number: 8968533
    Abstract: An electroplating processor includes an electrode plate having a continuous flow path formed in a channel. The flow path may optionally be a coiled flow path. One or more electrodes are positioned in the channel. A membrane plate is attached to the electrode plate with a membrane in between them. Electrolyte moves through the flow path at a high velocity, preventing bubbles from sticking to the bottom surface of membrane. Any bubbles in the flow path are entrained in the fast moving electrolyte and carried away from the membrane. The electroplating processor may alternatively have a wire electrode extending through a tubular membrane formed into a coil or other shape, optionally including shapes having straight segments.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: March 3, 2015
    Assignee: APPLIED Materials, Inc
    Inventors: Randy A. Harris, Daniel J. Woodruff, Jeffrey I. Turner, Gregory J. Wilson, Paul R. McHugh
  • Patent number: 8961771
    Abstract: Processes and systems for electrolytically processing a microfeature workpiece with a first processing fluid and an anode are described. Microfeature workpieces are electrolytically processed using a first processing fluid, an anode, a second processing fluid, and a cation permeable barrier layer. The cation permeable barrier layer separates the first processing fluid from the second processing fluid while allowing certain cationic species to transfer between the two fluids. The described processes produce deposits over repeated plating cycles that exhibit deposit properties (e.g., resistivity) within desired ranges.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: February 24, 2015
    Assignee: APPLIED Materials, Inc.
    Inventors: Rajesh Baskaran, Robert W. Batz, Jr., Bioh Kim, Tom L. Ritzdorf, John L. Klocke, Kyle M. Hanson
  • Patent number: 8920616
    Abstract: An electroplating method is disclosed that selectively deposits a greater thickness of a metal or alloy layer on a region of wafer that has a higher thickness loss during a subsequent chemical mechanical polish process. A paddle assembly has three rectangular sides joined at their edges to form a triangle shape from an end view, and a notch in a bottom side that faces a wafer during the plating process. The notch extends along second and third paddle sides to a height up to about 50% of the paddle thickness. The thickness in a K-block region that has two sides formed parallel to the wafer flat is selectively increased by aligning a first side of the paddle notch side directly over one K-block side and aligning a second notch side directly over a second K-block side during a paddle movement cycle. The notch may be rectangular shaped or tapered.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: December 30, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Chao-Peng Chen, Jaswant Chudasama, Pradeep Mishra, Chen-Li Lin, David Wagner
  • Publication number: 20140374266
    Abstract: A method and apparatus for controlling and changing the composition of a cadmium zinc telluride (CZT) transition layer as it is formed over a partially completed photovoltaic device using electrochemical deposition (ECD) where plating variables are systematically changed while the CZT transition layer is formed to change the composition of the plated CZT transition layer.
    Type: Application
    Filed: December 20, 2013
    Publication date: December 25, 2014
    Applicant: First Solar, Inc.
    Inventors: Markus Gloeckler, Long Cheng
  • Publication number: 20140370313
    Abstract: A method is provided for metallization of substrates providing a high adhesion of the deposited metal to the substrate material and thereby forming a durable bond. The method applies novel adhesion promoting agents comprising nanometer-sized particles prior to metallization. The particles have at least one attachment group bearing a functional chemical group suitable for binding to the substrate.
    Type: Application
    Filed: December 5, 2012
    Publication date: December 18, 2014
    Inventors: Thomas Thomas, Lutz Brandt, Lutz Stamp, Hans-Jürgen Schreier
  • Patent number: 8911609
    Abstract: Embodiments of the invention are directed to methods of electroplating copper onto at least one surface of a substrate in which more uniform electrical double layers are formed adjacent to the at least one surface being electroplated (i.e., the cathode) and an anode of an electrochemical cell, respectively. In one embodiment, the electroplated copper may be substantially-free of dendrites, exhibit a high-degree of (111) crystallographic texture, and/or be electroplated at a high-deposition rate (e.g., about 6 ?m per minute or more) by electroplating the copper under conditions in which a ratio of a cathode current density at the at least one surface to an anode current density at an anode is at least about 20. In another embodiment, a porous anodic film may be formed on a consumable copper anode using a long conditioning process that promotes forming a more uniform electrical double layer adjacent to the anode.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: December 16, 2014
    Assignee: Moses Lake Industries, Inc.
    Inventors: Valery M. Dubin, Xingling Xu, Yingxiang Tao, James D. Blanchard
  • Patent number: 8906218
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: December 9, 2014
    Assignee: Solexel, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 8895425
    Abstract: A method of forming a channel layer of an electric device according to an embodiment is provided. First, a conductive substrate including an insulating layer on the substrate is provided. The conductive substrate and a metal to be plated are used as respective electrodes to carry out electroplating within an electrolyte solution. In this case, electrons provided by a tunneling current passing through the insulating layer from the conductive substrate are bonded with ions of the metal within the electrolyte solution to form a metal channel layer on the insulating layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 25, 2014
    Assignee: SNU R&DB Foundation
    Inventors: Young June Park, Seok Ha Lee, Jun Ho Chun, Yeonkyu Choi
  • Patent number: 8888984
    Abstract: Tin-silver alloy electroplating baths having certain amine-oxide surfactants and methods of electrodepositing a tin-silver-containing layer using these baths are disclosed. Such electroplating baths are useful to provide tin-silver solder deposits having reduced void formation and improved within-die uniformity.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: November 18, 2014
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Inho Lee, Elissei Iagodkine, Yi Qin, Yu Luo
  • Publication number: 20140318977
    Abstract: In a processing system for electroplating semiconductor wafers and similar substrates, the contact ring of the electroplating processor is removed from the rotor of the processor and replaced with a previously deplated contact ring. This allows the contact ring to be deplated in ring service module of the system, while the processor continues to operate. Wafer throughput is improved. The contact ring may be attached to a chuck for moving the contact ring between the processors and the ring service module, with the chuck quickly attachable and releasable to the rotor.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 30, 2014
    Inventors: Robert B. Moore, David Silvetti, Paul Wirth, Randy Harris
  • Patent number: 8871076
    Abstract: Solar cells are produced using a method for producing solar cells, wherein silicon containing vitreous substrates is provided, wherein each substrate is provided with an electrically conductive material on at least one side thereof. In the method, at least a portion of each substrate is successively transported through an electrolytic solution that is present in an electrolytic bath, and the electrically conductive material as the cathode is connected during the transport of the substrates through the electrolytic bath for the purpose of electrodepositing material from the electrolytic solution onto the electrically conductive material during said transport, wherein the substrates are suspended from a conveyor element during transport and extend in the transport direction.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: October 28, 2014
    Assignee: Meco Equipment Engineers B.V.
    Inventors: Ronald Langereis, Gregorius Johannes Bertens
  • Patent number: 8858774
    Abstract: Methods of electroplating metal on a substrate while controlling azimuthal uniformity, include, in one aspect, providing the substrate to the electroplating apparatus configured for rotating the substrate during electroplating, and electroplating the metal on the substrate while rotating the substrate relative to a shield such that a selected portion of the substrate at a selected azimuthal position dwells in a shielded area for a different amount of time than a second portion of the substrate having the same average arc length and the same average radial position and residing at a different angular (azimuthal) position. For example, a semiconductor wafer substrate can be rotated during electroplating slower or faster, when the selected portion of the substrate passes through the shielded area.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: October 14, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter, Bryan L. Buckalew, Robert Rash
  • Patent number: 8852417
    Abstract: Processes and systems for electrolytically processing a microfeature workpiece with a first processing fluid and a counter electrode are described. Microfeature workpieces are electrolytically processed using a first processing fluid, a counter electrode, a second processing fluid, and an anion permeable barrier layer. The anion permeable barrier layer separates the first processing fluid from the second processing fluid while allowing certain anionic species to transfer between the two fluids. Some of the described processes produce deposits over repeated plating cycles that exhibit resistivity values within desired ranges.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: October 7, 2014
    Assignee: APPLIED Materials, Inc.
    Inventors: Rajesh Baskaran, Robert W. Batz, Jr., Bioh Kim, Tom L. Ritzdorf, John Lee Klocke, Kyle M. Hanson
  • Publication number: 20140262804
    Abstract: In electroplating a wafer, the front and/or back side of the wafer is heated or cooled during processing. The wafer may be in contact with a backing plate of an electroplating processor. The backing plate may be heated via electrical heaters, by radiant heaters, or via a heated liquid or gas. The backing plate may alternatively be cooled using electric coolers or cooled liquid or gas. The heated or cooled backing plate then heats or cools the back side of the wafer largely via conduction.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: APPLIED Materials, Inc.
    Inventor: Sam K. Lee
  • Publication number: 20140251817
    Abstract: A method of forming an oxide layer on an exposed surface of a semiconductor device which contains a p-n junction is disclosed, the method comprising: immersing the exposed surface of the semiconductor device in an electrolyte; producing an electric field in the semiconductor device such that the p-n junction is forward-biased and the exposed surface is anodic; and electrochemically oxidising the exposed surface to form an oxide layer.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: NewSouth Innovations Pty Limited
    Inventors: Valantis Vais, Alison Joan Lennon, Stuart Ross Wenham, Jing Jia Ji, Alison Maree Wenham, Jingnan Tong, Xi Wang
  • Publication number: 20140251435
    Abstract: The present invention describes a method of producing a p-type light-absorbing semiconductor copper zinc tin selenide/sulfide (Cu2(ZnxSn2-x)(SySe1-y)4) (abbreviated CZTS) with electrochemical deposition. It can be used in the production of solar cell when combined with an n-type inorganic or an organic semiconductor layer. The present method comprises a one-step or a sequence of depositions using electroplating to fabricate a low-cost and large-area CZTS solar cell, without using expensive and complicated deposition techniques or highly toxic and flammable chemicals in the production process. The present method significantly reduces the cost and energy requirement for production of solar cell.
    Type: Application
    Filed: February 12, 2014
    Publication date: September 11, 2014
    Applicant: Nano and Advanced Materials Institute Limited
    Inventors: Kam Piu HO, Paul Kwok Keung HO, Man Wah LIU, Ranshi WANG, Wai Chun LUK, Wing Ho CHOI, Fulin ZHENG, Kwong Chau KWOK, Mei Mei HSU, Ivan Ka Yu LAU
  • Publication number: 20140242374
    Abstract: Various methods, apparatuses and devices relate to porous metal layers on a substrate which are three-dimensionally coated. In one embodiment, a porous metal layer is deposited over a substrate. The porous metal layer can be three-dimensionally coated with a coating material.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Johann Strasser, Thomas Kunstmann, Manfred Frank, Werner Robl, Maximilian Krug, Simon Faiss, Matthias Mueller
  • Patent number: 8795502
    Abstract: A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Harold J. Hovel, Devendra K. Sadana, Xiaoyan Shao, Steven Erik Steen
  • Patent number: 8795505
    Abstract: A copper electroplating method including dipping a substrate in a copper electroplating solution, the substrate including a seed layer; and forming a copper electroplating layer on the seed layer, wherein the copper electroplating solution includes water, a copper supply source, an electrolytic material, and a first additive, the first additive includes a compound represented by Formula 1, below:
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: August 5, 2014
    Assignees: Samsung Electronics Co., Ltd., Adeka Corporation
    Inventors: Myung-Beom Park, Jung-Sik Choi, Ki-Hyeon Kim, Yuji Morishima, Shin-ichi Tanaka, Takashi Yamada, Takehiro Zushi
  • Patent number: 8795503
    Abstract: The invention concerns a device to conduct an electrochemical reaction on the surface of a semiconductor substrate (S), characterized in that the device comprises: a container (10) intended to contain an electrolyte (E), a support (20) arranged in the container, said support being adapted for attachment of the semiconductor substrate (S) on said support (20), a counter-electrode (30) arranged in the container (10), illumination means (50) comprising a source (51) emitting light rays and means (52) to homogenize the light rays on all of said surface of the semiconductor substrate (S), so as to activate the surface of the semiconductor substrate (S), and an electric supply (40) comprising connection means for connection to the semiconductor substrate and to the counter-electrode in order to polarize said surface of said semiconductor substrate (S) at an electric potential permitting the electrochemical reaction.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: August 5, 2014
    Assignee: Alchimer
    Inventors: Said Zahraoui, Francis Descours, Frederic Raynal
  • Patent number: 8784636
    Abstract: A method can form a conductive structure, which is useful for three-dimensional packaging with via plugs, in a shorter time by shortening the conventional long plating time that is an impediment to the practical use of electroplating. The method includes forming a conductive film on an entire surface, including interior surfaces of via holes, of a substrate having the via holes formed in the surface; forming a resist pattern at a predetermined position on the conductive film; carrying out first electroplating under first plating conditions, using the conductive film as a feeding layer, thereby filling a first plated film into the via holes; and carrying out second electroplating under second plating conditions, using the conductive film and the first plated film as a feeding layer, thereby allowing a second plated film to grow on the conductive film and the first plated film, both exposed in the resist openings of the resist pattern.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: July 22, 2014
    Assignee: Ebara Corporation
    Inventors: Mizuki Nagai, Nobutoshi Saito, Fumio Kuriyama, Akira Fukunaga
  • Patent number: 8778165
    Abstract: The invention relates to a process for forming a polymeric organic film on an electrically conductive or semiconductive surface by application of an electric potential between a gel, in contact with said surface, and said surface, the gel comprising (i) a protic solvent, (ii) compounds having colloidal properties, (iii) an adhesion primer, optionally (iv) a monomer and the potential applied being at least equal to the reduction potential of the adhesion primer. The invention also relates to said gel, to its use and to a kit for forming an organic film.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: July 15, 2014
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Serge Palacin, Brigitte Mouanda
  • Patent number: 8771495
    Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: July 8, 2014
    Assignee: Enthone Inc.
    Inventors: Vincent Paneccasio, Jr., Xuan Lin, Richard Hurtubise, Qingyun Chen
  • Publication number: 20140183051
    Abstract: A system and method generate atomic hydrogen (H) for deposition of a pure metal in a three-dimensional (3D) structure. The method includes forming a monolayer of a compound that includes the pure metal. The method also includes depositing the monolayer on the 3D structure and immersing the 3D structure with the monolayer in an electrochemical cell chamber including an electrolyte. Applying a negative bias voltage to the 3D structure with the monolayer and a positive bias voltage to a counter electrode generates atomic hydrogen from the electrolyte and deposits the pure metal from the monolayer in the 3D structure.
    Type: Application
    Filed: January 2, 2013
    Publication date: July 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Chudzik, Min Dai, Rishikesh Krishnan, Joseph F. Shepard, JR.
  • Patent number: 8741113
    Abstract: The present invention concerns an electrochemical pattern replication method, ECPR, and a construction of a conductive electrode for production of applications involving micro and nano structures. An etching or plating pattern, which is defined by a conductive electrode, a master electrode, is replicated on an electrically conductive material, a substrate. The master electrode is put in close contact with the substrate and the etching/plating pattern is directly transferred onto the substrate by using a contact etching/plating process. The contact etching/plating process is performed in local etching/plating cells, that are formed in closed or open cavities between the master electrode and the substrate.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: June 3, 2014
    Assignee: Centre de Recherche Public—Gabriel Lippmann
    Inventors: Patrik Möller, Mikael Fredenberg, Peter Wiwen-Nilsson
  • Patent number: 8728939
    Abstract: A single-crystal substrate is placed on a supporting table while maintaining crystalline orientation of the single-crystal substrate. The single-crystal substrate has contacting regions on a periphery of an upper surface of the single-crystal substrate. Linear contacting surfaces of contacting pins are placed in contact with the contacting regions of the single-crystal substrate placed on the supporting table. Longitudinal directions on the contacting surfaces of all the contacting pins are not parallel to intersecting lines of the upper surface of the single-crystal substrate and cleaved surfaces of the single-crystal substrate.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 20, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Maeda, Koichiro Nishizawa
  • Publication number: 20140110265
    Abstract: An electrode for forming an electrochemical cell with a substrate and a method of forming said electrode. The electrode comprises a carrier provided with an insulating layer which is patterned at a front side. Conducting material in an electrode layer is applied in the cavities of the patterned insulating layer and in contact with the carrier. A connection layer is applied at the backside of the carrier and in contact with the carrier. The periphery of the electrode is covered by the insulating material.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 24, 2014
    Applicant: CENTRE DE RECHERCHE PUBLIC - GABRIEL LIPPMANN
    Inventors: Mikael Fredenberg, Patrik Möller, Peter Wiwen-N ilsson, Cecilia Aronsson, Matteo Dainese