Coating Predominantly Semiconductor Substrate (e.g., Silicon, Compound Semiconductor, Etc.) Patents (Class 205/157)
  • Patent number: 7704367
    Abstract: First and second electrodes are disposed at first and second locations, respectively, proximate to a periphery of a wafer support, wherein the first and second location are substantially opposed to each other relative to the wafer support. Each of the first and second electrodes can be moved to electrically connect with and disconnect from a wafer held by the wafer support. An anode is disposed over and proximate to the wafer such that a meniscus of electroplating solution is maintained between the anode and the wafer. As the anode moves over the wafer from the first location to the second location, an electric current is applied through the meniscus between the anode and the wafer. Also, as the anode is moved over the wafer, the first and second electrodes are controlled to connect with the wafer while ensuring that the anode does not pass over an electrode that is connected.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 27, 2010
    Assignee: Lam Research Corporation
    Inventors: Yezdi Dordi, Bob Maraschin, John Boyd, Fred C. Redeker, Carl Woods
  • Publication number: 20100096271
    Abstract: Provided is a copper anode or a phosphorous-containing copper anode for use in performing electroplating copper on a semiconductor wafer, wherein purity of the copper anode or the phosphorous-containing copper anode excluding phosphorous is 99.99 wt % or higher, and silicon as an impurity is 10 wtppm or less. Additionally provided is an electroplating copper method capable of effectively preventing the adhesion of particles on a plating object, particularly onto a semiconductor wafer during electroplating copper, a phosphorous-containing copper anode for use in such electroplating copper, and a semiconductor wafer comprising a copper layer with low particle adhesion formed by the foregoing copper electroplating.
    Type: Application
    Filed: October 6, 2008
    Publication date: April 22, 2010
    Applicant: NIPPON MINING & METALS CO., LTD.
    Inventors: Akihiro Aiba, Hirofumi Takahashi
  • Patent number: 7691324
    Abstract: In a reaction chamber, which constitutes a component of a process installation for obtaining foodstuffs or foodstuff components, biological products in harvested form that are whole or in pieces are subjected to pulsed electric fields as they pass through said reaction chamber, said electric fields forming pores in the cell walls so as to irreversibly open the latter, thus making the content of the cells more easily accessible. This is achieved by electrode groups, which can be energized to a high voltage and are located in the wall of a longitudinal passage of the reactor through which the process material is moved past grounded electrodes located in an opposing longitudinal wall area. Each electrode group is connected to an electric energy accumulator such as for example, a Marx generator, by means of a switch, in order to rapidly establish electric fields of multiple directions between the charged and the grounded electrodes.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: April 6, 2010
    Assignees: Südzucker AG, Forschungszentrum Karlsruhe GmbH
    Inventor: Christoph Schultheiss
  • Publication number: 20100032303
    Abstract: An apparatus for electroplating a layer of metal on the surface of a wafer includes a second cathode located remotely with respect to the wafer. The remotely positioned second cathode allows modulation of current density at the wafer surface during an entire electroplating process. The second cathode diverts a portion of current flow from the near-edge region of the wafer and improves the uniformity of plated layers. The remote position of second cathode allows the insulating shields disposed in the plating bath to shape the current profile experienced by the wafer, and therefore act as a “virtual second cathode”. The second cathode may be positioned outside of the plating vessel and separated from it by a membrane.
    Type: Application
    Filed: August 16, 2006
    Publication date: February 11, 2010
    Inventors: Jonathan Reid, Seshasayee Varadarajan, Bryan Buckalew, Patrick Breiling, Glenn Ibarreta
  • Patent number: 7648621
    Abstract: The present invention pertains to an electrolytic copper plating method characterized in employing pure copper as the anode upon performing electrolytic copper plating, and performing electrolytic copper plating with the pure copper anode having a crystal grain diameter of 10 ?m or less or 60 ?m or more or a non-recrystallized anode. Provided are an electrolytic copper plating method and a pure copper anode for electrolytic copper plating used in such electrolytic copper plating method capable of suppressing the generation of particles such as sludge produced on the anode side within the plating bath upon performing electrolytic copper plating, and capable of preventing the adhesion to a semiconductor wafer, as well as a semiconductor wafer plated with the foregoing method and anode having low particle adhesion.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: January 19, 2010
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Akihiro Aiba, Takeo Okabe, Junnosuke Sekiguchi
  • Publication number: 20100000871
    Abstract: The present invention pertains to an electrolytic copper plating method characterized in employing pure copper as the anode upon performing electrolytic copper plating, and performing electrolytic copper plating with the pure copper anode having a crystal grain diameter of 10 ?m or less or 60 ?m or more. Provided are an electrolytic copper plating method and a pure copper anode for electrolytic copper plating used in such electrolytic copper plating method capable of suppressing the generation of particles such as sludge produced on the anode side within the plating bath upon performing electrolytic copper plating, and capable of preventing the adhesion of particles to a semiconductor wafer, as well as a semiconductor wafer plated with the foregoing method and anode having low particle adhesion.
    Type: Application
    Filed: September 11, 2009
    Publication date: January 7, 2010
    Applicant: NIPPON MINING & METALS CO., LTD.
    Inventors: Akihiro Aiba, Takeo Okabe, Junnosuke Sekiguchi
  • Patent number: 7641776
    Abstract: A system and method increase yield from semiconductor wafer electroplating. The aspects include a semiconductor wafer, the semiconductor wafer comprising a plurality of die areas. A plating ring for holding the semiconductor wafer in position during electroplating is also included, the plating ring substantially surrounding a circumference of the semiconductor wafer and having a width that varies in order to avoid overlap near edge die areas of the semiconductor wafer.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: January 5, 2010
    Assignee: LSI Corporation
    Inventors: Mohan Nagar, Shirish Shah
  • Publication number: 20090301770
    Abstract: A method for forming a film on a conductive substrate, comprising immersing a substrate having a conductive portion in a solution comprising a metal ion ceramic precursor for the film and a peroxide; applying a voltage potential to the conductive portion with respect to a counter electrode in the solution, sufficient to protect the conductive portion from corrosion by the solution, and drive formation of a film on the substrate, controlling a pH of the solution while limiting a production of hydrogen by electrolysis of the solution proximate to the conductive portion; and maintaining the voltage potential for a sufficient duration to produce a film on the conductive portion. An electrode may be formed over the film to produce an electrical device. The film may be, for example, insulating, dielectric, resistive, semiconductive, magnetic, or ferromagnetic.
    Type: Application
    Filed: June 10, 2009
    Publication date: December 10, 2009
    Inventors: Junghyun Cho, Bahgat Sammakia, Mark D. Poliks, Roy Magnuson, Biplab Kumar Roy
  • Publication number: 20090294293
    Abstract: The present invention relates to an electrodeposition composition intended particularly for coating a semiconductor substrate in order to fabricate structures of the “through via” type for the production of interconnects in integrated circuits. According to the invention, the said solution comprises copper ions in a concentration of between 14 and 120 mM and ethylenediamine, the molar ratio between ethylenediamine and copper being between 1.80 and 2.03 and the pH of the electrodeposition solution being between 6.6 and 7.5. The present invention also relates to the use of the said electrodeposition solution for the deposition of a copper seed layer, and to the method for depositing a copper a seed layer with the aid of the electrodeposition solution according to the invention.
    Type: Application
    Filed: May 4, 2009
    Publication date: December 3, 2009
    Applicant: ALCHIMER
    Inventors: Said ZAHRAOUI, Frederic RAYNAL
  • Publication number: 20090283414
    Abstract: An electrochemical co-deposition method and solution to plate uniform, defect free and smooth (In,Ga)—Se films with repeatability and controllable molar ratios of (In,Ga) to Se are provided. Such layers are used in fabrication of semiconductor and electronic devices such as thin film solar cells. In one embodiment, the present invention provides an alkaline electrodeposition solution that includes an In salt, a Se acid or oxide, a tartrate salt as complexing agent for the In species, and a solvent to electrodeposit an In—Se film possessing sub-micron thickness on a conductive surface.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 19, 2009
    Inventors: Jiaxiong Wang, Serdar Aksu, Bulent M. Basol
  • Publication number: 20090236232
    Abstract: An electrolytic plating solution includes a polar solvent, copper sulfate dissolved in the polar solvent, an accelerator including a sulfur compound, and a reducing agent having a smaller molecular weight than the accelerator.
    Type: Application
    Filed: March 19, 2009
    Publication date: September 24, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Tsuyoshi KANKI
  • Publication number: 20090236231
    Abstract: A method includes: immersing a semiconductive substrate in an electrodeposition composition, wherein at least 20 percent by weight of resin solids in the composition is a highly cross-linked microgel component, and applying a voltage between the substrate and the composition to form a dielectric coating on the substrate. A composition for use in electrodeposition includes a resin blend, a coalescing solvent, a catalyst, water, and a highly cross-linked migrogel, wherein at least 20 percent by weight of resin solids in the composition is the highly cross-linked microgel. Another composition for use in electrodeposition includes a surfactant blend, a low ion polyol, phenoxypropanol, a catalyst, water, a flexibilizer, and a highly cross-linked migrogel, wherein at least 20 percent by weight of resin solids in the composition is the highly cross-linked microgel.
    Type: Application
    Filed: March 17, 2009
    Publication date: September 24, 2009
    Applicant: PPG Industries Ohio, Inc.
    Inventors: Kelly L. Moore, Michael J. Pawlik, Michael G. Sandala, Craig A. Wilson
  • Patent number: 7591937
    Abstract: The invention relates to a method of fixing macro-objects to an electricity conducting- or semi-conducting surface by means of electrografting. The invention also relates to the electricity conducting- or semi-conducting-surfaces obtained using the aforementioned method and to the applications of same.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: September 22, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Christophe Bureau, Guy Deniau, José Gonzalez, Serge Palacin
  • Patent number: 7566482
    Abstract: A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kwang Su Choe, Keith E. Fogel, Devendra K. Sadana
  • Patent number: 7560016
    Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: July 14, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, John Stephen Drewery
  • Publication number: 20090166210
    Abstract: Methods and structures for electroplating shield structures for perpendicular thin film write poles having ultra thin non-magnetic top gaps on the order of a few nanometers are disclosed. Ultra thin, conductive seed layers serve a dual purpose as both plating seed layer and non-magnetic top gap for the write pole. Due to reduced current carrying capacity of ultra thin seed layers, an additional thick seed layer is also employed to aid delivering plating current to regions near the pole.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 2, 2009
    Inventors: Christian Rene Bonhote, Quang Le, Xhavin Sinha
  • Patent number: 7550071
    Abstract: Methods are described for the electrochemical assembly of organic molecules on silicon, or other conducting or semiconducting substrates, using iodonium salt precursors. Iodonium molecules do not assemble on conducting surfaces without a negative bias. Accordingly, the iodonium salts are preferred for patterning applications that rely on direct writing with negative bias. The stability of the iodonium molecule to acidic conditions allows them to be used with standard silicon processing. As a directed assembly process, the use of iodonium salts provides for small features while maintaining the ability to work on a surface and create structures on a wafer level. Therefore, the process is amenable for mass production. Furthermore, the assembled monolayer (or multilayer) is chemically robust, allowing for subsequent chemical manipulations and the introduction of various molecular functionalities for various chemical and biological applications.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: June 23, 2009
    Assignee: Sandia Corporation
    Inventors: Shawn M. Dirk, Stephen W. Howell, David R. Wheeler
  • Patent number: 7544281
    Abstract: An electrochemical plating apparatus and method for facilitating uniform current distribution across a wafer during loading into an ECP (electrochemical plating) apparatus is disclosed. The apparatus includes a bath container for containing a bath solution, an anode provided in the bath container, a cathode ring for supporting a wafer in the bath container and a current source electrically connected to the anode and the cathode ring. According to the method, a voltage potential is applied to the cathode ring as it is immersed into the solution and prior to immersion of the wafer in the solution, thereby facilitating a substantially uniform plating current across the wafer upon immersion of the wafer.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: June 9, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Wei Lin, Ming-Hsing Tsai
  • Patent number: 7540950
    Abstract: An electrically conductive body, which in particular includes a metal and/or an alloy and/or a semiconductor, includes an adhesion promoter layer provided on at least one surface of the electrically conductive body. The adhesion promoter layer includes a metal, in particular zinc, and a porous, in particular platelike and/or needle-shaped and/or sponge-like, surface structure.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: June 2, 2009
    Assignee: Infineon Technologies, AG
    Inventors: Edmund Riedl, Wolfgang Schober
  • Publication number: 20090127122
    Abstract: A multi-chambered system for electroplating metal layers on a semiconductor substrate. The system comprises a fluid reservoir having at least a first chamber and a second chamber. A cathode is located in the first chamber, an anode is located in the second chamber, and a shield is located between the cathode and anode. The cathode is configured to be electrically coupled to a semiconductor substrate locatable in the first chamber. The anode is configured to oppose a first major surface of the semiconductor substrate. The shield is configured to deter electrolytic fluid communication between the first and second chamber, other than though predefined openings in the shield.
    Type: Application
    Filed: November 21, 2007
    Publication date: May 21, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Nishath Yasmeen, Richard Aaron Ledesma
  • Publication number: 20090120497
    Abstract: The invention relates to a metallized solar cell and the method of making thereof that includes depositing a metal or metals such as silver, nickel, copper, tin, indium, gallium, or selenium or their alloys on solar cells in a manner to form more substantial and robust electrical contacts that can carry current more efficiently and effectively or to provide the active layers required to convert sunlight into electricity. These deposits also protect the underlying metallic materials from corrosion, oxidation or other environmental changes that would deleteriously affect the electrical performance of the cell. The invention also relates to the use of specialized electroplating chemistries that minimize residual stress and/or are free of organic sulfonic acids to minimize chemical attack on solar cell substrates or prior metallizations that include organic and/or inorganic binders or related materials for depositing the initial metallic portions of the cell.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 14, 2009
    Inventor: Robert A. SCHETTY, III
  • Publication number: 20090092367
    Abstract: A semiconductor substrate with anode pattern is anodized to be shaped into an optical lens. The anodization utilizes an electrolytic solution which etches out oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. After being removed of the porous layer, the substrate is treated to smooth out minute projections remaining in the top surface of the substrate, thereby obtaining the lens of good transmissivity.
    Type: Application
    Filed: August 24, 2006
    Publication date: April 9, 2009
    Applicant: Matsushita Electric Works, Ltd.
    Inventors: Yoshiaki Honda, Takayuki Nishikawa, Tomohiro Kamitsu
  • Publication number: 20090078313
    Abstract: A thin film solar cell including a Group IBIIIAVIA absorber layer on a defect free base including a stainless steel substrate is provided. The stainless steel substrate of the base is surface treated to reduce the surface roughness such as protrusions that cause shunts. In one embodiment, the surface roughness is reduced by coating surface with a thin silicon dioxide which fills the cavities and recesses around the protrusions and thereby reducing the surface roughness. After the silicon dioxide film is formed, a contact layer is formed over the ruthenium layer and the exposed portions of the substrate to complete the base.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 26, 2009
    Inventor: Bulent M. Basol
  • Publication number: 20090057154
    Abstract: An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 5, 2009
    Applicant: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, John M. Cotte, Hariklia Deligianni, Matteo Flotta
  • Patent number: 7497932
    Abstract: The present invention provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes a spin-rinse-dry (SRD) station disposed between the loading station and the mainframe, a rapid thermal anneal chamber attached to the loading station, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: March 3, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Yezdi Dordi, Donald J. Olgado, Ratson Morad, Peter Hey, Mark Denome, Michael Sugarman, Anna Marie Lloyd, legal representative, Joseph Stevens, Dan Marohl, Ho Seon Shin, Eugene Ravinovich, Robin Cheung, Ashok K. Sinha, Avi Tepman, Dan Carl, George Birkmaier, Mark Lloyd
  • Patent number: 7479213
    Abstract: A plating method is capable of preferentially precipitating a plated film fully and uniformly in trenches and via holes according to a mechanical and electrochemical process, and of easily forming a plated film having higher flatness surface without being affected by variations in the shape of trenches and via holes. The plating method includes a first plating process and a second plating process. The second plating process is performed by filling a plating solution between an anode and a substrate, with a porous member placed in the plating solution, repeatedly bringing the porous member and the substrate into and out of contact with each other, passing a current between the anode and the substrate while the porous member is being held in contact with the substrate.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: January 20, 2009
    Assignee: Ebara Corporation
    Inventors: Mizuki Nagai, Hiroyuki Kanda, Keiichi Kurashina, Satoru Yamamoto, Hidenao Suzuki, Koji Mishima, Brett C. Baker-O'Neal, Hariklia Deligianni, Keith Kwietniak
  • Publication number: 20080314754
    Abstract: A method for increasing an electrical resistance of a resistor. A fraction F of an exterior surface of a surface layer of a resistor of a semiconductor structure is exposed to the nitrogen-comprising molecules. An anodization electrical circuit is formed and includes: a DC power supply, an electrolytic solution including nitrogen, and the resistor partially immersed in the electrolytic solution. The DC power supply is activated and generates a voltage output, that causes an electrolytic reaction in the electrolytic solution near the resistor. The electrolytic reaction generates nitrogen ions from the nitrogen in the electrolytic solution. The fraction F is exposed to the nitrogen ions. A portion of the surface layer is nitridized by being reacted with the nitrogen ions at a temperature above ambient room temperature such that an electrical resistance of the resistor is increased.
    Type: Application
    Filed: September 2, 2008
    Publication date: December 25, 2008
    Inventors: Arne W. Ballantine, Daniel C. Edelstein, Anthony K. Stamper
  • Publication number: 20080314742
    Abstract: Aimed at providing an electrolytic Ni plating apparatus capable of suppressing passivation of the surface of a Ni anode, preventing current efficiency and rate of film formation from being degraded, providing a stable Ni plating so as to contribute to improvement in quality, and maintaining a stable production capacity. The electrolytic Ni plating apparatus of the present invention is provided with a nickel (Ni) anode having an average grain size of 10 ?m or smaller.
    Type: Application
    Filed: January 29, 2008
    Publication date: December 25, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hiroaki TACHIBANA
  • Publication number: 20080289967
    Abstract: A substrate holding and transporting assembly is disclosed. The substrate holding and transporting assembly includes a base plate and a pair of clamps connected to the base plate in a spaced apart orientation, the spaced apart orientation of the pair of clamps enable support of a substrate with at least two independent points. The substrate holding and transporting assembly also includes an electrode assembly connected to the base plate at a location that is substantially between the pair of clamps. The electrode assembly defined to impart an electrical contact to the substrate when present and held by the pair of clamps.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 27, 2008
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Aleksander Owczarz, Robert Knop, Mike Ravkin, Carl A. Woods
  • Patent number: 7449099
    Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: November 11, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, John Stephen Drewery
  • Publication number: 20080257743
    Abstract: A method of making an integrated circuit including a composition of matter for electrodepositing of chromium is disclosed. One embodiment provides a bath having a solution of a chromium salt in a substantially anhydrous organic solvent, to uses of certain chromium salts for electrodepositing and to processes for electrodepositing chromium.
    Type: Application
    Filed: April 19, 2007
    Publication date: October 23, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Johannes Lodermeyer, Edmund Riedl, Werner Robl
  • Patent number: 7435324
    Abstract: A method of selectively electroplating metal features on a semiconductor substrate having a conductive surface. An electrode assembly that includes a plurality of adjacent, mutually spaced and electrically isolated electrodes connected in series so as to be oppositely polarized when a voltage is applied thereacross is positioned over the substrate and an electrolyte solution is applied to the conductive surface. The electrode assembly and the conductive surface may be positioned in close proximity to, but without contacting, one another. A voltage is applied to the electrode assembly, which causes a metal film to selectively form on portions of the conductive surface that are positioned beneath an electrode exhibiting a positive polarity and, thus, negatively charged. Portions of the conductive surface positioned beneath electrodes exhibiting a negative polarity remain unplated.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: October 14, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Ramarajan, Whonchee Lee
  • Publication number: 20080230377
    Abstract: A capacitively coupled plasma reactor comprising a processing chamber, a first electrode, a second electrode and a thermoelectric unit. The processing chamber has an upper portion with a gas inlet and a lower portion, and the upper portion is in fluid communication with the lower portion. The first electrode has a front side and a backside and is positioned at the upper portion of the processing chamber. The second electrode is positioned in the lower portion of the processing chamber and is spaced apart from the front side of the first electrode. The thermoelectric unit is positioned proximate to the backside of the first electrode and is capable of heating and cooling the first electrode.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Applicant: Micron Technology, Inc.
    Inventor: Mark Kiehlbauch
  • Patent number: 7425256
    Abstract: An apparatus and method for plating a workpiece. The apparatus comprises, generally, an anode, a cathode, and a selective anode shield/material flow assembly. In use, both the anode and the cathode are immersed in a solution, and the cathode is used to support the workpiece. During an electroplating process, the anode and the cathode generate an electric field emanating from the anode towards the cathode, to generate a corresponding current to deposit an electroplating material on the workpiece. The selective shield/material flow assembly is located between the anode and the cathode, and forms a multitude of adjustable openings. These opening have sizes that are adjustable during the electroplating process for selectively and controllably adjusting the amount of electric flux passing through the selective shield/material flow assembly and the distribution of the electroplating material on the workpiece. The selective shield/material flow assembly can also be used with an electroless plating system.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: September 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Barrese, Gary Gajdorus, Allen H. Hopkins, John J. Konrad, Robert C. Schaffer, Timothy L. Wells
  • Publication number: 20080210568
    Abstract: An electrolytic copper plating method characterized in employing a phosphorous copper anode having a crystal grain size of 1,500 ?m (or more) to 20,000 ?m in an electrolytic copper plating method employing a phosphorous copper anode. Upon performing electrolytic copper plating, an object is to provide an electrolytic copper plating method of a semiconductor wafer for preventing the adhesion of particles, which arise at the anode side in the plating bath, to the plating object such as a semiconductor wafer, a phosphorous copper anode for electrolytic copper plating, and a semiconductor wafer having low particle adhesion plated with such method and anode.
    Type: Application
    Filed: March 3, 2008
    Publication date: September 4, 2008
    Applicant: NIPPON MINING & METALS CO., LTD.
    Inventors: Akihiro Aiba, Takeo Okabe
  • Publication number: 20080187480
    Abstract: A relatively thick electrode is positioned opposite the surface of a substrate/second electrode. The electrode and the substrate surface are both contacted by a solution including silicon nanoparticles. The substrate surface is completely immersed in the solution in a manner such that there is not an air/solution interface and there is no meniscus at the substrate surface. Application of electrical potential between the electrode and the substrate creates a film of silicon nanoparticles on the substrate. Drying of the film induces the film to roll up and form a silicon nanoparticle nanotube material. A film may be subdivided into an array of identical portions, and the identical portions will roll into identical tubes having same length and diameter. A silicon nanoparticle nanotube material of the invention includes nanotubes formed of silicon nanoparticles.
    Type: Application
    Filed: June 9, 2004
    Publication date: August 7, 2008
    Inventors: Munir H. Nayfeh, Sahraoui Chaieb
  • Patent number: 7388147
    Abstract: In a solar cell having p doped regions and n doped regions alternately formed in a surface of a semiconductor wafer in offset levels through use of masking and etching techniques, metal contacts are made to the p regions and n regions by first forming a base layer contacting the p doped regions and n doped regions which functions as an antireflection layer, and then forming a barrier layer, such as titanium tungsten or chromium, and a conductive layer such as copper over the barrier layer. Preferably the conductive layer is a plating layer and the thickness thereof can be increased by plating.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: June 17, 2008
    Assignee: Sunpower Corporation
    Inventors: William P. Mulligan, Michael J. Cudzinovic, Thomas Pass, David Smith, Richard M. Swanson
  • Publication number: 20080121527
    Abstract: A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate having submicron-sized features, and a concentrate for forming a corresponding electroplating bath. A substrate is immersed into an electroplating bath formed from the concentrate including ionic copper and an effective amount of a defect reducing agent, and electroplating the copper deposit from the bath onto the substrate to fill the submicron-sized reliefs. The occurrence of protrusion defects from superfilling, surface roughness, and voiding due to uneven growth are reduced, and macro-scale planarity across the wafer is improved.
    Type: Application
    Filed: January 8, 2008
    Publication date: May 29, 2008
    Applicant: ENTHONE INC.
    Inventors: John Commander, Richard Hurtubise, Vincent Paneccasio, Xuan Lin, Kshama Jirage
  • Publication number: 20080090414
    Abstract: A method of preparing an aqueous electroless deposition composition for electrolessly depositing Co or a Co alloy onto a substrate in manufacture of microelectronic devices by treating water or an aqueous electroless deposition composition with a deoxygenating treatment to reduce the oxygen concentration.
    Type: Application
    Filed: October 16, 2006
    Publication date: April 17, 2008
    Applicant: Enthone Inc.
    Inventors: Qingyun Chen, Richard Hurtubise, Vincent Paneccasio, Charles Valverde, Daniel Stritch
  • Publication number: 20080083625
    Abstract: A method for manufacturing a semiconductor device is provided. The method can include forming a pattern for a copper line on a semiconductor substrate, forming a barrier metal layer on the pattern, removing a natural oxide layer from the barrier metal layer using a basic compound, and depositing copper ions on the barrier metal layer. A copper seed layer is not necessary.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 10, 2008
    Inventor: SANG CHUL KIM
  • Patent number: 7338585
    Abstract: A method comprising forming an interconnection opening through a dielectric material to a contact point; and electroplating a interconnection comprising copper in the contact opening using an electroplating bath comprising an alkoxylated sulfopropylated alkylamine. A method comprising forming an interconnection opening through a dielectric material to a contact point; lining the interconnection opening with a barrier layer and a seed layer; and electroplating an interconnection comprising copper in the contact opening using an electroplating bath comprising an alkoxylated sulfopropylated alkylamine.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: March 4, 2008
    Assignee: Intel Corporation
    Inventors: Rohan N. Akolkar, Valery M. Dubin
  • Patent number: 7332066
    Abstract: A process for metallization of a workpiece, such as a semiconductor workpiece. In an embodiment, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: February 19, 2008
    Assignee: Semitool, Inc.
    Inventors: Linlin Chen, Gregory J. Wilson, Paul R. McHugh, Robert A. Weaver, Thomas L. Ritzdorf
  • Publication number: 20080029402
    Abstract: An electrochemical processing apparatus is provided, in which a substrate and an anode placed in a chamber are partitioned into a cathode region including the substrate and an anode region including the anode by placing a multi-layered structure of a filtration film and a cation exchange film so that the filtration film is positioned on the substrate side. A plating solution containing additives is introduced into the cathode region, whereby a substrate is plated.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 7, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tetsuya Kurokawa, Koji Arita, Kaori Noda
  • Patent number: 7323094
    Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that plates on electrical current density modifier portions (364) of structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: January 29, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cindy Reidsema Simpson, Matthew T. Herrick, Gregory S. Etherington, James Derek Legg
  • Patent number: 7316783
    Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: January 8, 2008
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
  • Patent number: 7314543
    Abstract: A device includes an integrated circuit and a deposited tin in electrical contact with a portion of the integrated circuit. The deposited tin is formed by electrodeposition from a bath. The deposited tin includes a residue characteristic of the bath. The bath includes a bath-soluble tin compound, a strong acid, and a sulfopropylated anionic surfactant. In another aspect, a composition includes between approximately 20 and 40 grams per liter of one of stannous methane sulfonate, stannous sulfate, and a mixture thereof, between approximately 100 and 200 grams per liter of one of methanesulfonic acid, sulfuric acid, and a mixture thereof, and between approximately 1 and 2 grams per liter of one or more polyethyleneglycol alkyl-3-sulfopropyl diethers. In another aspect, a method includes electroplating tin with a current density of greater than approximately 30 mA/cm2 and a plating efficiency of greater than approximately 95%.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: January 1, 2008
    Assignee: Intel Corporation
    Inventors: Ming Fang, Valery M. Dubin, Scott M. Haight
  • Publication number: 20070289873
    Abstract: Provided is a technique for wafer plating treatment that ensures that the plating film thickness becomes uniform on the total area of a plated wafer surface. This method of wafer plating includes: arranging a wafer in an opening of a plating tank; bringing a peripheral side of the wafer and a cathode electrode into contact with each other; supplying a plating liquid; causing the plating liquid that has reached the wafer to flow in the direction of a periphery of a wafer surface to be plated; and supplying a plating current by an anode electrode arranged within the plating tank so as to be opposed to the wafer and the cathode electrode, whereby the wafer is subjected to a plating treatment. In this method, the anode electrode has a shape almost the same shape as the wafer surface to be plated, a plurality of peripheral-edge current supplying sections are provided in a peripheral edge of the anode electrode, and a central current supplying section is provided in a center of the anode electrode.
    Type: Application
    Filed: June 1, 2007
    Publication date: December 20, 2007
    Inventor: Yuji Uchiumi
  • Patent number: 7288177
    Abstract: An apparatus and method for plating a workpiece. The apparatus comprises, generally, an anode, a cathode, and a selective anode shield/material flow assembly. In use, both the anode and the cathode are immersed in a solution, and the cathode is used to support the workpiece. During an electroplating process, the anode and the cathode generate an electric field emanating from the anode towards the cathode, to generate a corresponding current to deposit an electroplating material on the workpiece. The selective shield/material flow assembly is located between the anode and the cathode, and forms a multitude of adjustable openings. These opening have sizes that are adjustable during the electroplating process for selectively and controllably adjusting the amount of electric flux passing through the selective shield/material flow assembly and the distribution of the electroplating material on the workpiece. The selective shield/material flow assembly can also be used with an electroless plating system.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Barrese, Gary Gajdorus, Allen H. Hopkins, John J. Konrad, Robert C. Schaffer, Timothy L. Wells
  • Patent number: 7241372
    Abstract: A plating apparatus and a plating liquid removing method removes a plating liquid remaining on a substrate-contacting portion, or portions in its vicinity, of a substrate holding member. The plating apparatus comprises a head having a rotatable housing provided with a substrate holding member for holding a substrate, a plating process container, disposed below the head, for holding a plating liquid therein, and a plating liquid removing mechanism for removing plating liquid remaining on the substrate-contacting portion, or the portions in its vicinity, at an inner circumferential edge of the substrate holding member.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: July 10, 2007
    Assignee: Ebara Corporation
    Inventors: Satoshi Sendai, Kenya Tomioka, Katsumi Tsuda
  • Patent number: RE40218
    Abstract: The invention provides an apparatus and a method for achieving reliable, consistent metal electroplating or electrochemical deposition onto semiconductor substrates. More particularly, the invention provides uniform and void-free deposition of metal onto metal seeded semiconductor substrates having sub-micron, high aspect ratio features. The invention provides an electrochemical deposition cell comprising a substrate holder, a cathode electrically contacting a substrate plating surface, an electrolyte container having an electrolyte inlet, an electrolyte outlet and an opening adapted to receive a substrate plating surface and an anode electrically connect to an electrolyte. Preferably, a vibrator is attached to the substrate holder to vibrate the substrate in at least one direction, and an auxiliary electrode is disposed adjacent the electrolyte outlet to provide uniform deposition across the substrate surface.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: April 8, 2008
    Inventor: Uziel Landau