Abstract: A method of manufacturing a semiconductor device is to be provided, which improves filling performance of a conductive layer to be formed by an electrolytic plating process in an interconnect trench or a via hole, and achieves a higher in-plane uniformity in bottom-up performance. An electrolytic plating process to fill with a conductive layer at least one of an interconnect trench and a via hole formed in a dielectric layer on a semiconductor substrate includes a first step of executing a plating operation under a predetermined integrated current density, which is a product of a current density representing a current value supplied per unit area of a plating solution containing a material which constitutes the conductive layer and a plating time, and a second step of executing a plating operation under a lower current density than that of the first step.

Abstract: Embodiments of the invention generally provide an electrochemical plating system. The plating system includes a substrate loading station positioned in communication with a mainframe processing platform, at least one substrate plating cell positioned on the mainframe, at least one substrate bevel cleaning cell positioned on the mainframe, and a stacked substrate annealing station positioned in communication with at least one of the mainframe and the loading station, each chamber in the stacked substrate annealing station having a heating plate, a cooling plate, and a substrate transfer robot therein.

Abstract: An improved apparatus for treating plate-like workpieces with a designated chemical solution, including printed circuit boards, includes: (1) a tray for holding the chemical solution, with the tray having an open top which is configured to receive a horizontally-oriented workpiece, with the tray having a top edge with a portion of the edge forming a dam over which the solution may flow and an opening in its lower portion where the solution can enter the tray, (2) a reservoir tank situated below the tray, (3) a feed line connecting the reservoir tank and tray opening, (4) a drain that returns the solution that overflows the tray top edge to the reservoir tank, and (5) a pump that circulates the solution from the tank to the tray and over the horizontally situated workpiece.

Abstract: An improved copper ECD process. After the copper seed layer (116) is formed, a first portion of copper film (118) is plated onto the surface of the seed layer (116). The surface of the first portion of the copper film (118) is then rinsed to equalize the organic adsorption on all sites to prevent preferential copper growth in dense areas. After rinsing, the remaining copper of the copper film (118) is electrochemically deposited.

Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: In an anodization apparatus and an anodization method for electrochemically treating a target substrate by irradiating the target substrate with light, treatment of a large target substrate can be made possible with smaller constituent elements. The electrical contact with the target substrate by a contact member is realized by a plurality of contact members or by the movement of a contact member to change the electrical contact position. The target substrate is manufactured in advance so as to have such a structure that portions thereof to be in contact with the plural contact members are connected to portions of a conductive layer on a treatment part thereof respectively.

Abstract: A plating apparatus and method which smoothly perform contact of a plating liquid with a surface of the substrate and which can prevent air bubbles from remaining on the surface to be plated. The plating apparatus includes a plating bath containing a plating liquid in which an anode is immersed, a head portion for holding a substrate detachably and bringing a lower surface, to be plated, of the substrate into contact with an overflow surface of the plating liquid held in the plating bath, a drive mechanism for rotating the head portion, and a tilt mechanism for tilting the head portion so that the substrate held by the head portion is inclined relative to a horizontal plane.

Abstract: Disclosed are electrolyte compositions for depositing a tin alloy on a substrate. The electrolyte compositions include tin ions, ions of one or more alloying metals, an acid, a thiourea derivative, and an additive selected from alkanol amines, polyethylene imines, alkoxylated aromatic alcohols, and combinations thereof. Also disclosed are methods of depositing a tin alloy on a substrate and methods of forming an interconnect bump on a semiconductor device.

Abstract: A chemical control system for controlling the chemistry of a chemical solution having predetermined chemical constituents in a plating system, such as a NiFe plating system, employs a mix container for containing a plating solution and a hold container for containing a plating solution delivered from the mix container. A precision delivery arrangement delivers a precise predetermined quantum of a predetermined constituent of the plating solution to multiple mix containers and the hold containers. Transfer of plating solution between the mix and hold containers is effected by a transfer pump. Nitrogen gas that has been humidified with deionized water protects the plating solution from either acquiring water or becoming dehydrated, the humidified nitrogen gas being humidified to a predetermined relative humidity with respect to the temperature of the plating solution in the mix container. This is achieved by urging the nitrogen gas through a column that is at the same temperature as the plating solution.

Abstract: A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.

Abstract: A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.

Abstract: In the invention, there is provided a plating treatment technique which permits uniform plating treatment and easy replacement of articles to be plated without the effect of bubbles in a plating solution by improving wet plating apparatuses of the contact type to thereby solve problems such as the removal of bubbles in a plating solution and the removal of an adhering plating solution. Provided is a plating apparatus having a plating tank, which comprises: an opening which has a solution seal to prevent a plating solution from leaking when an article to be plated is placed on the opening; a solution-supply portion which supplies the plating solution; a solution-discharge portion which discharges the plating solution; and an anode which is opposed to the article to be plated that is placed, wherein the plating tank has rotational means for rotating the plating tank itself.

Abstract: In an electrochemical reactor used for electrochemical treatment of a substrate, for example, for electroplating or electropolishing the substrate, one or more of the surface area of a field-shaping shield, the shield's distance between the anode and cathode, and the shield's angular orientation is varied during electrochemical treatment to screen the applied field and to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film of conductive metal on the wafer.

Abstract: A method for filling recessed microstructures at a surface of a microelectronic workpiece, such as a semiconductor wafer, with metallization is set forth. In accordance with the method, a metal layer is deposited into the microstructures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed microstructures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties. Various novel apparatus for executing unique annealing processes are also set forth.

Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

Abstract: A process for fabricating a vertical spiral inductor within a multichip module package is disclosed. The process consists of depositing a pattern of bottom lines by electroplating copper on a substrate and then depositing an insulation pattern. Next, depositing a pattern of permeable material to form a core and then depositing polyimide to define vias and permeable core insulation. The vias are filled by electroplating copper. The vertical spiral inductor is formed and defined by next depositing a pattern of top metal (e.g. copper) lines by electroplating wherein the top metal lines are staggered with respect to the bottom metal lines. Lastly a top protective layer is deposited. The core is made from a permeable or non-permeable material.

Abstract: The present invention is directed to a method and apparatus for plating a surface of a semiconductor workpiece (wafer, flat panel, magnetic films, etc.) using a liquid conductor that makes contact with the outer surface of the workpiece. The liquid conductor is stored in a reservoir and pump through an inlet channel to the liquid chamber. The liquid conductor is injected into a liquid chamber such that the liquid conductor makes contact with the outer surface of the workpiece. An inflatable tube is also provided to prevent the liquid conductor from reaching the back face of the workpiece. A plating solution can be applied to the front face of the workpiece where a retaining ring/seal further prevents the plating solution and the liquid conductor from making contact with each other. In an alternative embodiment, electrical contacts may be formed using an inflatable tube that has either been coated with a conductive material or contains a conductive object.

Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.

Abstract: An apparatus for processing a material on a wafer surface includes a cavity defined by a peripheral wall and configured to direct a process solution and direct it to the surface to to a first wafer surface region without being directed to a second wafer surface region, a head configured to hold the wafer so that the surface of the wafer faces the cavity, and an electrical contact member positioned outside the cavity peripheral wall and configured to contact the second wafer surface region extending beyond the cavity, when the wafer is moved relative to the contact member. Advantages of the invention include substantially full surface treatment of the wafer.

Abstract: A semiconductor workpiece holder used in electroplating systems for plating metal layers onto a semiconductor workpieces, and is of particular advantage in connection with plating copper onto semiconductor materials. The workpiece holder includes electrodes which have a contact face which bears against the workpiece and conducts current therebetween. The contact face is provided with a contact face outer contacting surface which is made from a contact face material similar similar to the workpiece plating material which is to be plated onto the semiconductor workpiece. The contact face can be formed by pre-conditioned an electrode contact using a plating metal which is similar to the plating materials which is to be plated onto the semiconductor workpiece.

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

Abstract: A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200° C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.

Abstract: The present invention is directed to a copper bath composition and a process for the electroless and/or electrolytic plating of copper to fill vias and trenches during the manufacture of integrated circuits. Specifically, the copper bath composition comprises water, copper ions, hydroxide ions, a complexing agent to inhibit the formation of copper oxides, copper hydroxides and copper salts, a stabilizer to control the rate of electroless copper plating, a reducing agent to promote the electroless reduction of the copper ions to copper metal, and a catalyst to promote the electrolytic reduction copper ions to copper metal.

Abstract: A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.

Abstract: The chemical composition of thin films is modulated during their growth. A computer code has been developed to design specific processes for producing a desired chemical composition for various deposition geometries. Good agreement between theoretical and experimental results was achieved.

Abstract: The invention is related to a method of plating of a metal layer on a substrate. The method is particularly preferred for the formation of metallization structures for integrated circuits.

Abstract: A method of forming a metal layer on a substrate is disclosed. The metal layer is formed using a combined electrochemical plating/electrochemical mechanical polishing (ECP/EMP) process. In the ECP/EMP process, the metal layer is deposited on the substrate by contacting the substrate with a porous pad and then alternately applying a first electrical potential and a second electrical potential to an electrolyte plating solution. The first electrical potential functions to deposit metal on the substrate while the second electrical potential functions to remove metal from topographic portions thereof.

Abstract: Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the workpiece is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the workpiece frontal side surface, in its entirety, is thus permitted.

Abstract: A method of forming an oxide free copper interconnect, comprising the following steps. A substrate is provided and a patterned dielectric layer is formed over the substrate. The patterned dielectric layer having an opening exposing a portion of the substrate. The opening having exposed sidewalls. A copper seed layer is formed over the sidewalls of the opening. The copper seed layer is subjected to an electrochemical technique to eliminate any copper oxide formed over the copper seed layer. A bulk copper layer is electrochemically plated over the copper-oxide-free copper seed layer, filling the opening and forming the oxide-free copper interconnect.

Abstract: Method of synthesis of confined colloidal crystals using electrodeposition. The present invention provides a method of growing confined colloidal crystal structures using electrodeposition of monodispersed charged colloid spheres onto a substrate patterned with an array of electroconductive surface relief features on a surface of a substrate. In this approach, control over large-scale ordering is achieved via a planar pattern whose scale is on the order of tens of microns, a regime readily accessed through coarse lithography, laser micromachining, and holography.

Abstract: The present invention provides an edge cleaning system and method in which a directed stream of a mild etching solution is supplied to an edge area of a rotating workpiece, including the front surface edge and bevel, while a potential difference between the workpiece and the directed stream is maintained. In one aspect, the present invention provides an edge cleaning system that is disposed in the same processing chamber that is used for deposition or removal processing of the workpiece. In another aspect, the mild etching solution used for edge removal is also used to clean the front surface of the wafer, either simultaneously with or sequentially with the edge removal process.

Abstract: A method for electroplated metal annealing process. First, a semiconductor structure is provided, wherein the semiconductor structure has a plurality of semiconductor components, such as a gate electrode, a source region and a drain region, and a field oxide region. Second, a dielectric layer is formed over the semiconductor structure, and a via which exposes a part of the semiconductor structure is formed in the dielectric layer by the use of conventional lithographic and etching processes and an electroplated metal layer is formed over the dielectric layer; meanwhile, the via is filled with the electroplated metal layer. The electroplated metal layer is then annealed by a NH3 plasma process performed by plasma enhanced chemical vapor deposition (PECVD).

Abstract: An active part of a sensor is formed, for example, by micro-machined silicon wafers bearing electronic elements, electrical conductors, connection pads, and pins. The pads are electrically connected to the pin ends by conductive elements. Then the wafer and the pin ends are plunged into an electrolytic bath to make an electrolytic deposit of conductive metal on the pin ends, the pads, and the conductive elements that connect them. Finally, this metal is oxidized or nitrized to form an insulating coat on the pin ends, the pads, and the conductive elements that connect them. Such a sensor may find particular application as a sensor designed to work in harsh environments.

Abstract: There is provided a substrate processing apparatus and method which employs the so-called batch processing method of processing a plurality of substrates simultaneously, thereby increasing the throughput, and which can carry out processing, such as electroless plating, stably and securely with a relatively simple apparatus.

Abstract: A porous silicon structure is stabilized by anodically oxidizing the structure and then subjecting it to chemical functionalization to protect non-oxidized surface regions, preferably in the presence of 1-decene under thermal conditions. This process creates a protective organic monolayer on the surface of the structure, rendering it highly stable.

Abstract: This invention employs a novel approach to the copper metallization of a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.

Abstract: A method of fabricating a semiconductor device, having a reduced-oxygen Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants; and annealing the electroplated Cu—Zn alloy thin film (30); and a semiconductor device thereby formed. The method controls the parameters of pH, temperature, and time in order to form a uniform reduced-oxygen Cu—Zn alloy thin film (30), having a controlled Zn content, for reducing electromigration on the Cu—Zn/Cu structure by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate, for improving device reliability, and for increasing corrosion resistance.

Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.

Abstract: A method and apparatus for electrochemically depositing a metal into a high aspect ratio structure on a substrate are provided. In one aspect, a method is provided for processing a substrate including positioning a substrate having a first conductive material disposed thereon in a processing chamber containing an electrochemical bath, depositing a second conductive material on the first conductive material as the conductive material is contacted with the electrochemical bath by applying a plating bias to the substrate while immersing the substrate into the electrochemical bath, and depositing a third conductive material in situ on the second conductive material by an electrochemical deposition technique to fill the feature. The bias may include a charge density between about 20 mA*sec/cm2 and about 160 mA*sec/cm2. The electrochemical deposition technique may include a pulse modulation technique.

Abstract: Embodiments of the invention generally provide a method for removing a substrate from a processing fluid contained in a processing cell. The method includes tilting the substrate to a tilt angle, rotating the substrate, vertically moving the substrate upward out of the processing fluid, and applying an electrical removal bias to the substrate during the vertical movement of the substrate out of the processing fluid.

Abstract: A method for forming bonding pads on a printed circuit board (PCB) with circuit patterns is provided. A plurality of copper patterns are formed on the PCB which are electrically connected to the circuit patterns, and a filler is filled between the copper patterns such that an upper surface of the copper pattern is exposed. A plating layer is then applied to the exposed upper surface of the copper patterns. Protrusion of the plating layer at a lower portion of a copper pattern is prevented, thus reducing an interval between the wire bonding pad(s) and potentially increasing the number of bonding pads which may be effectively formed on a given PCB.

Abstract: The present invention pertains to an electrolytic copper plating method characterized in employing pure copper as the anode upon performing electrolytic copper plating, and performing electrolytic copper plating with the pure copper anode having a crystal grain diameter of 10 &mgr;m or less or 60 &mgr;m or more or a non-recrystallized anode.

Abstract: The present invention pertains to a more efficient system and method for forming rectifying junction contacts in PIN alloy-semiconductor devices using photoelectrical and chemical etching. The present invention provides a means of creating rectifying junction contacts on alloy-semiconductor devices such as CdTe and CdZnTe, among others. In addition, the present invention also provides a simple and low cost method for revealing wafer surface morphology of alloy-semiconductors, thus providing an efficient and effective means for selecting single grain semiconductor substrates. Further, the present invention provides radiation detectors employing such alloy-semiconductor devices having improved rectifying junctions as the detector element.

Abstract: Disclosed are methods for repairing seed layers prior to subsequent metallization during the manufacture of electronic devices. Also disclosed are electronic devices containing substantially continuous seed layers.

Abstract: A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.

Abstract: An electrochemical processing method is provided for forming a current carrying device for semiconductor chip packaging and similar applications. The method comprises selecting sections of a substrate to carry current wherein a selected section is at least partly covered with a voltage switchable dielectric material, rendering the voltage switchable dielectric material conductive, and electrochemically forming a current carrying material directly on the voltage switchable dielectric material. The voltage switchable dielectric material can have a characteristic voltage, such that when a voltage having a magnitude exceeding the characteristic voltage is applied to the voltage switchable dielectric material, the voltage switchable dielectric material switches from a dielectric material to a conductive material. When conductive, the voltage switchable dielectric material is amenable to electrochemical processing such as electroplating.

Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.

Abstract: A method is disclosed for electrolytically forming conductor structures from highly pure copper on surfaces of semiconductor substrates, which surfaces are provided with recesses, when producing integrated circuits. The method includes the steps of coating the surfaces of the semiconductor substrates with a full-surface basic metal layer in order to achieve sufficient conductance for the electrolytic depositions, depositing full-surface deposition of copper layers of uniform layer thickness on the basic metal layer by an electrolytic metal deposition method, and structuring the copper layer.