Coating Predominantly Semiconductor Substrate (e.g., Silicon, Compound Semiconductor, Etc.) Patents (Class 205/157)
  • Patent number: 6793796
    Abstract: Electroplating methods using an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, avoid defects in plated films on substrates having features with a range of aspect ratios, while providing good filling and thickness distribution. The methods include, in succession, applying DC cathodic current densities optimized to form a conformal thin film on a seed layer, to provide bottom-up filling, preferentially on features having the largest aspect ratios, and to provide conformal plating of all features and adjacent field regions. Including a leveling agent in the electroplating bath produces films with better quality after subsequent processing.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 21, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, David Smith, Steven T. Mayer, Jon Henri, Sesha Varadarajan
  • Publication number: 20040178078
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Patent number: 6790333
    Abstract: The present invention relates to a to-be-mounted electronic component to which functional alloy plating using a bonding material for mounting is applied with a substitute bonding material for solder (tin-lead alloy), and aims at providing alloy plating which has been put to a practical use in such a way that the function of existing alloy plating of this type has been significantly improved to eliminate toxic plating from various kinds of electronic components for use in electronic devices so that it is useful in protecting the environment. Functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that with Sn (tin) as a base, one of Bi (bismuth), Ag (silver) and Cu (copper) is selected, a Bi content to the Sn is set to 1.0% or less, the Bi content to the Sn is set to 2.0 to 10.0%, an Ag content to the Sn is set to 1.0 to 3.0%, the Ag content to the Sn is set to 3.0 to 5.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: September 14, 2004
    Assignee: Nishihara Rikoh Corporation
    Inventor: Masaaki Ishiyama
  • Publication number: 20040173464
    Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer.
    Type: Application
    Filed: March 19, 2004
    Publication date: September 9, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Suketu Parikh, Robin Cheung
  • Patent number: 6787047
    Abstract: A method for manufacturing a sensor, the sensor including a three-dimensional interdigital electrode arrangement positioned on a substrate, comprising applying a temperature sensing resistor onto the substrate by sputtering a first adhesion layer and a first metallic layer onto the substrate, applying a first resist layer to the first metallic layer, applying and structuring a first resist material on the first metallic layer, and after structuring, etching the first metallic layer in resist free areas; and applying a three-dimensional interdigital electrode arrangement onto the substrate by sputtering a second adhesion layer and a second metallic layer onto the substrate, applying and structuring a second resist material only to second metal layer, after the structuring, etching the second metallic layer in resist free areas to form valleys, and after etching the second metallic layer, applying an electroplating layer.
    Type: Grant
    Filed: November 7, 2000
    Date of Patent: September 7, 2004
    Assignee: Robert Bosch GmbH
    Inventors: Dietmar Hahn, Gottfried Flik, Alexandra Jauernig
  • Patent number: 6776893
    Abstract: A copper electroplating bath and a method to plate substrates with the bath are provided. The bath and method are particularly effective to plate electronic components such as semiconductive wafer VLSI and ULSI interconnects with void-free fill copper plating for circuitry forming vias and trenches and other small features less than 0.2 microns with high aspect ratios. The copper bath contains a bath soluble organic divalent sulfur compound, and a bath soluble polyether compound such as a block copolymer of polyoxyethylene and polyoxypropylene, a polyoxyethylene or polyoxypropylene derivative of a polyhydric alcohol and a mixed polyoxyethylene and polyoxypropylene derivative of a polyhydric alcohol. A preferred polyether compound is a mixed polyoxyethylene and polyoxypropylene derivative of glycerine. A preferred copper bath also contains a pyridine compound derivative.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: August 17, 2004
    Assignee: Enthone Inc.
    Inventors: Elena H. Too, Paul R. Gerst, Vincent Paneccasio, Jr., Richard W. Hurtubise
  • Patent number: 6776892
    Abstract: A semiconductor workpiece holder used in electroplating systems for plating metal layers onto a semiconductor workpieces, and is of particular advantage in connection with plating copper onto semiconductor materials. The workpiece holder includes electrodes which have a contact face which bears against the workpiece and conducts current therebetween. The contact face is provided with a contact face outer contacting surface which is made from a contact face material similar similar to the workpiece plating material which is to be plated onto the semiconductor workpiece. The contact face can be formed by pre-conditioned an electrode contact using a plating metal which is similar to the plating materials which is to be plated onto the semiconductor workpiece.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: August 17, 2004
    Assignee: Semitool, Inc.
    Inventors: Thomas L. Ritzdorf, Jeffrey I. Turner
  • Patent number: 6773571
    Abstract: The present invention pertains to methods and apparatus for electroplating a substantially uniform layer of a metal onto a work piece having a seed layer thereon. The total current of a plating cell is distributed among a plurality of anodes in the plating cell in order to tailor the current distribution in the plating electrolyte to compensate for resistance and voltage variation across a work piece due to the seed layer. Focusing elements are used to create “virtual anodes” in proximity to the plating surface of the work piece to further control the current distribution in the electrolyte during plating.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: August 10, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Evan E. Patton, Brian Paul Blackman, Jonathan D. Reid, Thomas Anand Ponnuswamy, Harold D. Perry
  • Publication number: 20040134789
    Abstract: A substrate processing apparatus fills a metal such as copper or the like in fine interconnection patterns or trenches defined in a semiconductor substrate. The substrate processing apparatus has a loading/unloading unit for placing a substrate cassette to allow a substrate to be loaded and unloaded, a substrate treating unit for treating a substrate, and a transfer robot for transferring a substrate between the loading/unloading unit and the substrate treating unit. The loading/unloading unit, the substrate treating unit, and the transfer robot are installed in a single facility. The loading/unloading unit has a rotary table which is horizontally rotatable for positioning the substrate cassette in a position to detect the substrate cassette placed in the loading/unloading unit and to remove the substrate from the substrate cassette with the transfer robot.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 15, 2004
    Inventors: Koji Mishima, Junji Kunisawa, Natsuki Makino, Norio Kimura, Hiroaki Inoue, Kenji Nakamura, Moriji Matsumoto, Takahiro Nanjo, Mitsuko Odagaki
  • Patent number: 6758957
    Abstract: Carbon nanoparticles including both nanofilaments and nanotubes produced by an electrochemical deposition method from organic solutions at room temperature, in which the formation and growth of carbon nanoparticles are stimulated by the catalyst, such as iron and nickel. It has been found that the electrochemical deposition conditions have a strong influence on the growth phenomenon of the carbon nanotubes. Scanning electron microscope (SEM) and transmitting electron microscope (TEM) characterizations show that the diameter of nanotubes is of the order of approximately 100 nm, and the length of filaments can be up to approximately 50 &mgr;m, depending on the size of catalyst particles.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: July 6, 2004
    Assignee: University of Central Florida
    Inventors: Dan Zhou, Lee Chow
  • Patent number: 6755954
    Abstract: An apparatus for electrochemical treatment of a substrate, in particular for electroplating an integrated circuit wafer. An apparatus preferably includes dynamically operable concentric anodes and dielectric shields in an electrochemical bath. Preferably, the bath height of an electrochemical bath, the substrate height, and the shape and positions of an insert shield and a diffuser shield are dynamically variable during electrochemical treatment operations. Step include varying anode current, bath height and substrate height, shield shape, and shield position.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: June 29, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Timothy Patrick Cleary, Michael John Janicki, Edmund B. Minshall, Thomas A. Ponnuswamy
  • Publication number: 20040118690
    Abstract: A method of forming a metal film of copper on the surface of a resin substrate by successively effecting the conditioning treatment, Pd activation treatment, electroless copper plating treatment and electrolytic copper plating treatment. In the conditioning treatment, a conditioning treatment solution is interposed in the form of a thin layer between the surface and a cover glass plate, and the surface is irradiated with ultraviolet light from the upper side of the cover glass plate. Irradiation with ultraviolet light in the presence of the treatment solution causes the molecules in the surface of the resin to chemically react with the component of the treatment solution, whereby the surface of the resin is more activated to improve the adhesion with copper that is deposited on the surface of the resin.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Masaaki Yoshitani
  • Publication number: 20040118694
    Abstract: Embodiments of the invention generally provide an electrochemical processing system configured to provide multiple chemistries for a single plating process. The multiple chemistries are generally delivered to individual plating cells positioned on the processing system. The individual chemistries may generally be used to conduct direct plating on a barrier layer, alloy plating, plating on a thin seed layer, optimized feature fill and bulk fill plating, plating with minimized defects, and/or any other plating process wherein multiple chemistries may be utilized to take advantage of the desirable characteristics of each chemistry.
    Type: Application
    Filed: May 14, 2003
    Publication date: June 24, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Michael X. Yang, Ming Xi, Russell C. Ellwanger, Eric B. Britcher
  • Patent number: 6753251
    Abstract: A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: June 22, 2004
    Assignee: Semitool, Inc.
    Inventors: Thomas L. Ritzdorf, Lyndon W. Graham
  • Patent number: 6746578
    Abstract: An apparatus and method for plating a workpiece. The apparatus comprises, generally, an anode, a cathode, and a selective anode shield/material flow assembly. In use, both the anode and the cathode are immersed in a solution, and the cathode is used to support the workpiece. During an electroplating process, the anode and the cathode generate an electric field emanating from the anode towards the cathode, to generate a corresponding current to deposit an electroplating material on the workpiece. The selective shield/material flow assembly is located between the anode and the cathode, and forms a multitude of adjustable openings. These opening have sizes that are adjustable during the electroplating process for selectively and controllably adjusting the amount of electric flux passing through the selective shield/material flow assembly and the distribution of the electroplating material on the workpiece. The selective shield/material flow assembly can also be used with an electroless plating system.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: June 8, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Barrese, Gary Gajdorus, Allen H. Hopkins, John J. Konrad, Robert C. Schaffer, Timothy L. Wells
  • Publication number: 20040099534
    Abstract: A method, apparatus and anode for plating copper or other metals onto a barrier or seed layer of a wafer surface is described. A copper layer of uniform thickness is plated on the surface by, for instance, maintaining a constant current density between the anode and wafer surface. Several configurations of anodes are described for obtaining the constant current density.
    Type: Application
    Filed: November 27, 2002
    Publication date: May 27, 2004
    Inventor: James Powers
  • Patent number: 6736953
    Abstract: A method of forming an electrically conductive structure on a substrate. An electrically conductive electrode layer is formed on the substrate, and an electrically conductive conduction layer is formed over the electrode layer. The conduction layer is formed by placing the substrate in a plating solution. A first current is applied to the substrate at a first bias and a first density for a first duration. A second current is applied to the substrate at a second bias and a second density for a second duration. The first current and the second current are cyclically applied at a frequency of between about thirty hertz and about one hundred and thirty hertz.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 18, 2004
    Assignee: LSI Logic Corporation
    Inventors: Mei Zhu, Zhihai Wang
  • Patent number: 6733649
    Abstract: A semiconductor workpiece holder for use in processing a semiconductor workpiece includes a workpiece support operatively mounted to support a workpiece in position for processing. A finger assembly is operatively mounted upon the workpiece support and includes a finger tip. The finger assembly is movable between an engaged position in which the finger tip is engaged against the workpiece, and a disengaged position in which the finger tip is moved away from the workpiece. Preferably, at least one electrode forms part of the finger assembly and includes an electrode contact for contacting a surface of said workpiece. At least one protective sheath covers at least some of the electrode contact. According to one aspect of the invention, a sheathed electrode having a sheathed electrode tip is positioned against a semiconductor workpiece surface in a manner engaging the workpiece surface with said sheathed electrode tip.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: May 11, 2004
    Assignee: Semitool, Inc.
    Inventors: Martin Bleck, Kenneth C. Haugan, Larry R. Radloff, Harry Geyer
  • Patent number: 6726823
    Abstract: A wafer chuck assembly for holding a wafer during electroplating and/or electropolishing of the wafer includes a wafer chuck for receiving the wafer. The wafer chuck assembly also includes an actuator assembly for moving the wafer chuck between a first and a second position. When in the first position, the wafer chuck is opened. When in the second position, the wafer chuck is closed.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: April 27, 2004
    Assignee: ACM Research, Inc.
    Inventors: Hui Wang, Felix Gutman, Voha Nuch
  • Patent number: 6723219
    Abstract: A method of electroplating metal onto a low conductivity layer combines a potential or current reversal waveform with variation in the amplitude and duration of the applied potential or current pulse. The method includes, over time, varying the duration of the pulse and continuously decreasing the amplitude of both the cathodic and anodic portions of the waveform across the surface of the low conductivity layer as the deposition zone moves from the center of the surface of the low conductivity layer to the outside edge. By virtue of the ability to vary the amplitude and duration of the pulse, the method facilitates the filling of structures in the center of the low conductivity layer without overdepositing on the outside edge, thus ensuring a controlled deposition of material across the surface of the low conductivity layer.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: April 20, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Dale W. Collins
  • Patent number: 6716334
    Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: April 6, 2004
    Assignee: Novellus Systems, Inc
    Inventors: Jonathan D. Reid, Steven W. Taatjes, Robert J. Contolini, Evan E. Patton
  • Publication number: 20040055894
    Abstract: In a process for producing a semiconductor member, and a solar cell, making use of a thin-film crystal semiconductor layer, the process comprises the steps of: (1) anodizing the surface of a first substrate to form a porous layer at least on one side of the substrate, (2) forming a semiconductor layer at least on the-surface of the porous layer, (3) removing the semiconductor layer at its peripheral region, (4) bonding a second substrate to the surface of the semiconductor layer, (5) separating the semiconductor layer from the first substrate at the part of the porous layer, and (6) treating the surface of the first substrate after separation and repeating the above steps (1) to (5).
    Type: Application
    Filed: September 24, 2003
    Publication date: March 25, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yukiko Iwasaki, Shoji Nishida, Kiyofumi Sakaguchi, Noritaka Ukiyo
  • Patent number: 6709563
    Abstract: There is provided a copper-plating liquid free from an alkali metal and a cyanide which, when used in plating of a substrate having an outer seed layer and fine recesses of a high aspect ratio, can reinforce the thin portion of the seed layer and can embed copper completely into the depth of the fine recesses. The plating liquid contains divalent copper ions and a completing agent, and an optional pH adjusting agent.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: March 23, 2004
    Assignee: Ebara Corporation
    Inventors: Mizuki Nagai, Shuichi Okuyama, Ryoichi Kimizuka, Takeshi Kobayashi
  • Patent number: 6709562
    Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: March 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Constantinou Andricacos, Hariklia Deligianni, John Owen Dukovic, Daniel Charles Edelstein, Wilma Jean Horkans, Chao-Kun Hu, Jeffrey Louis Hurd, Kenneth Parker Rodbell, Cyprian Emeka Uzoh, Kwong-Hon Wong
  • Patent number: 6706166
    Abstract: A method for improving an electrodeposited metal film uniformity and preventing metal deposition and peeling of deposited metal from an electrode during an electrodeposition and electropolishing process including providing a first anode electrode assembly and a semiconductor wafer plating surface disposed in an electrolyte bath including a plating metal for deposition onto the semiconductor wafer plating surface; providing at least one additional anode electrode assembly including the plating metal disposed peripheral to the first anode electrode assembly for selectively applying the cathodic electrical potential during an electropolishing process; and, periodically alternating between an electrodeposition process and electropolishing process with respect to the semiconductor wafer plating surface such that the plating metal is preferentially plated onto the at least one additional electrode assembly.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: March 16, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai
  • Patent number: 6706628
    Abstract: A method for forming a thin film and a method for fabricating a liquid crystal display device using the same are provided. The method provides a process that is simplified. Uniform thin film characteristics can be obtained. The method for forming a thin film includes the steps of forming a diffusion barrier film on a substrate, forming a metal seed layer on the diffusion barrier film, removing a metal oxide film formed on a surface of the metal seed layer using an electric plating method, and depositing metal on the metal seed layer in which the metal oxide film is removed.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: March 16, 2004
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Soo Kil Kim, Jong Uk Bae, Jae Jeong Kim
  • Publication number: 20040035707
    Abstract: Methods used in semiconductor electroplating systems, such as for plating copper, onto a semiconductor wafer or other semiconductor workpiece. The methods apply to patterned metal layers plated onto a seed layer which is partially protected by an overlying photoresist or other coating. The methods employ an electrode assembly which has a boot which seals about a contact face of the electrode. The sealing is performed by engaging the seal against photoresist to prevent corrosion of the seal layer. The area enclosed by the sealing includes a via which is surrounded by the seal. The electrode contact extends through the via to provide electrical contact with the metallic seed layer. Plating of copper or other metal proceeds at exposed seed layer areas.
    Type: Application
    Filed: April 7, 2003
    Publication date: February 26, 2004
    Inventors: Robert W. Batz, Kenneth C. Haugan, Harry J. Geyer, Robert W. Berner
  • Publication number: 20040035708
    Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.
    Type: Application
    Filed: April 17, 2003
    Publication date: February 26, 2004
    Applicant: Semitool, Inc.
    Inventors: Linlin Chen, Thomas Taylor
  • Patent number: 6695962
    Abstract: An anode assembly by which a solution can be supplied to a surface of a semiconductor substrate includes a housing defining an internal housing volume into which the solution can flow. A closure is provided for the internal housing volume, and the solution can be discharged from the internal housing volume through the closure towards the surface of the semiconductor substrate. A filter divides the internal housing volume into a first chamber and a second chamber located between the first chamber and the closure. During supply of the solution to the surface, a flow of the solution into the second chamber occurs at a higher rate than a flow of the solution into the first chamber, and the flows are blended in the second chamber.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: February 24, 2004
    Assignee: NuTool Inc.
    Inventors: Cyprian E. Uzoh, Homayoun Talieh, Bulent M. Basol
  • Publication number: 20040031693
    Abstract: A process for metallization of a workpiece, such as a semiconductor workpiece. In an embodiment, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
    Type: Application
    Filed: February 27, 2003
    Publication date: February 19, 2004
    Inventors: Linlin Chen, Gregory J. Wilson, Paul R. McHugh, Robert A. Weaver, Thomas L. Ritzdorf
  • Publication number: 20040026257
    Abstract: Apparatus and methods are disclosed for electroplating conductive films on semiconductor wafers, wherein field adjustment apparatus is located in a reservoir between a cathode and an anode to influence the electric field used in the plating process. Field adjustment apparatus is presented having one or more apertures, which may be selectively plugged to adjust the electrical fields during plating.
    Type: Application
    Filed: August 8, 2002
    Publication date: February 12, 2004
    Inventors: David Gonzalez, Matthew W. Losey
  • Publication number: 20040026254
    Abstract: Method for selectively metallizing dielectric materials, the method includes: adhesively covering dielectric materials with an activating layer comprising a conductive material, which layer is subsequently structured by way of laser ablation; and using a subsequent laser treatment to structure the activating layer in such a way that discrete conductive structures are formed, which are subsequently metallized.
    Type: Application
    Filed: August 4, 2003
    Publication date: February 12, 2004
    Inventors: Jurgen Hupe, Walter Kronenberg, Jorg Kickelhain, Dieter J. Meier
  • Patent number: 6685815
    Abstract: An electro-chemical deposition apparatus and method are generally provided. In one embodiment of the invention, an electro-chemical deposition apparatus includes a housing having a substrate support disposed therein and adapted to rotate a substrate. One or more electrical contact elements are disposed on the substrate support. A drive system is disposed proximate the housing. The drive system is magnetically coupled to and adapted to rotate the substrate support. In another embodiment, a method of plating a substrate includes the steps of covering a substrate supported within a housing with electrolyte, and displacing a portion of the electrolyte from the housing prior to electrically biasing the substrate, and electrically biasing the substrate.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: February 3, 2004
    Assignee: Applied Materials Inc.
    Inventor: Nicolay Kovarsky
  • Publication number: 20040016647
    Abstract: Embodiments of the invention provide a method for plating copper into features formed on a semiconductor substrate. The method includes positioning the substrate in a plating cell, wherein the plating cell includes a catholyte volume containing a catholyte solution, an anolyte volume containing an anolyte solution, an ionic membrane positioned to separate the anolyte volume from the catholyte volume, and an anode positioned in the anolyte volume. The method further includes applying a plating bias between the anode and the substrate, plating copper ions onto the substrate from the catholyte solution, and replenishing the copper ions plated onto the substrate from the catholyte solution with copper ions transported from the anolyte solution via the ionic membrane, wherein the catholyte solution has a copper concentration of greater than about 51 g/L.
    Type: Application
    Filed: July 8, 2003
    Publication date: January 29, 2004
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Michael X. Yang, Nicolay Y. Kovarsky
  • Patent number: 6679983
    Abstract: Disclosed are electrolytes for copper electroplating that provide enhanced fill of small features with less overplate. Also disclosed are methods of plating substrates, such as electronic devices, using such electrolytes.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: January 20, 2004
    Assignee: Shipley Company, L.L.C.
    Inventors: Denis Morrissey, Robert D. Mikkola, Jeffrey M. Calvert
  • Publication number: 20040000485
    Abstract: In an electroplating apparatus for semiconductor wafers, the currents to each of a plurality of contact portions contacting the wafer edge are individually adjustable and/or a parameter indicative of the current flow in each contact portion may be determined. Moreover, for precise control of the currents, means are provided for monitoring the currents.
    Type: Application
    Filed: November 25, 2002
    Publication date: January 1, 2004
    Inventors: Axel Preusse, Gerd Marxsen
  • Patent number: 6670308
    Abstract: An epitaxial article and method for forming the same includes a substrate having a textured surface, and an electrochemically deposited substantially single orientation epitaxial layer disposed on and in contact with the textured surface. The epitaxial article can include an electromagnetically active layer and an epitaxial buffer layer. The electromagnetically active layer and epitaxial buffer layer can also be deposited electrochemically.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: December 30, 2003
    Assignee: UT-Battelle, LLC
    Inventor: Amit Goyal
  • Publication number: 20030234182
    Abstract: A copper damascene process for a mechanically weak low k dielectric layer is described. Electropolishing is used to etch back the copper. A sacrificial conductive layer beneath the barrier layer assures complete planarization of the copper.
    Type: Application
    Filed: June 19, 2002
    Publication date: December 25, 2003
    Inventor: Tatyana Andryushchenko
  • Patent number: 6664633
    Abstract: A method for depositing a metal conduction layer in a feature of a substrate is provided. The method includes forming the feature in the substrate, the feature having a width dimension of less than about a tenth of a micron. A barrier layer is deposited on the substrate, preferably using a self ionized plasma deposition process, where the barrier layer has a thickness of no more than about three hundred angstroms. A substantially continuous seed layer is deposited on the barrier layer, where the seed layer has a thickness of less than about three hundred angstroms. A conduction layer is deposited on the seed layer from an alkaline electroplating bath, where the electroplating bath contains an electroplating solution selected from the group consisting a pyrophosphate solution, an alkaline cyanide solution and an alkaline metal ion complexing solution. The process is adaptable to electroplating features on a substrate wherein the features have a width dimension of less than about one tenth of a micron.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: December 16, 2003
    Assignee: LSI Logic Corporation
    Inventor: Mei Zhu
  • Patent number: 6660154
    Abstract: Disclosed are methods for repairing or enhancing discontinuous metal seed layers prior to subsequent metallization during the manufacture of electronic devices. Such repair methods do not require the use of a second electroplating bath.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: December 9, 2003
    Assignee: Shipley Company, L.L.C.
    Inventors: David Merricks, Denis Morrissey, Martin W. Bayes, Mark Lefebvre, James G. Shelnut, Donald E. Storjohann
  • Patent number: 6660152
    Abstract: According to the invention, silicon nanoparticles are applied to a substrate using an electrochemical plating processes, analogous to metal plating. An electrolysis tank of an aqueous or non-aqueous solution, such as alcohol, ether, or other solvents in which the particles are dissolved operates at a current flow between the electrodes. In applying silicon nanoparticles to a silicon, metal, or non-conducting substrate, a selective area plating may be accomplished by defining areas of different conductivity on the substrate. Silicon nanoparticle composite platings and stacked alternating material platings are also possible. The addition of metal ions into the silicon nanoparticle solution produces a composite material plating. Either composite silicon nanoparticle platings or pure silicon nanoparticle platings may be stacked with each other or with convention metal platings.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: December 9, 2003
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Munir H. Nayfeh, Gennadiy Belomoin, Adam Smith, Taysir Nayfeh
  • Patent number: 6656339
    Abstract: Methods of forming a nano-supported catalyst on a substrate and at least one carbon nanotube on the substrate are comprised of configuring a substrate with an electrode (102), immersing the substrate with the electrode into a solvent containing a first metal salt and a second metal salt (104) and applying a bias voltage to the electrode such that a nano-supported catalyst is at least partly formed with the first metal salt and the second metal salt on the substrate at the electrode (106). In addition, the method of forming at least one carbon nanotube is comprised of conducting a chemical reaction process such as catalytic decomposition, pyrolysis, chemical vapor deposition, or hot filament chemical vapor deposition o grow at least one nanotube on the surface of the nano-supported catalyst (108).
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: December 2, 2003
    Assignee: Motorola, Inc.
    Inventors: Albert A. Talin, Bernard F. Coll, Kenneth A. Dean, Matthew Stainer
  • Patent number: 6652727
    Abstract: A continuous layer of a metal is electrodeposited onto a substrate having both hydrodynamically inaccessible recesses and hydrodynamically accessible recesses on its surface by a two-step process in which the hydrodynamically inaccessible recesses are plated using a pulsed reversing current with cathodic pulses having a duty cycle of less than about 50% and anodic pulses having a duty cycle of greater than about 50% and the hydrodynamically accessible recesses are then plated using a pulsed reversing current with cathodic pulses having a duty cycle of greater than about 50% and anodic pulses having a duty cycle of less than about 50%.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: November 25, 2003
    Assignee: Faraday Technology Marketing Group, LLC
    Inventors: E. Jennings Taylor, Jenny J. Sun, Maria E. Inman
  • Publication number: 20030213697
    Abstract: A method for reducing or avoiding semiconductor wafer peripheral defects and contamination during and following electrodeposition including providing a wafer chuck assembly sealably attached to a back side of a semiconductor wafer leaving an exposed peripheral portion of the back side of the semiconductor wafer the backside parallel to a front side of the semiconductor wafer comprising a process surface; contacting at least the semiconductor process surface with a process solution; and, simultaneously directing a pressurized flow of gas onto the exposed peripheral portion such that the pressurized flow of gas covers the exposed peripheral portion including being radially directed outward toward the periphery of the semiconductor wafer.
    Type: Application
    Filed: May 16, 2002
    Publication date: November 20, 2003
    Applicant: Taiwain Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Wei Chou
  • Publication number: 20030209444
    Abstract: A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 13, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wen Su, Shih-Wei Chou, Ching-Hua Hsieh, Shau-Lin Shue
  • Publication number: 20030209445
    Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.
    Type: Application
    Filed: June 10, 2003
    Publication date: November 13, 2003
    Inventors: Homayoun Talieh, Cyprian Uzoh, Bulent M. Basol
  • Publication number: 20030205477
    Abstract: An electrode assembly arrangement for improving an electrodeposition process and method for using the same the electrode assembly arrangement including a first electrode assembly and a second electrode assembly positioned to carry a metal containing electrolyte from the first electrode assembly to the second electrode assembly for deposition of the metal upon applying an electrical potential therebetween; at least one additional electrode assembly including a means for selectively applying an electrical potential thereto the at least one additional electrode assembly positioned to attract an electrolyte flow upon applying an electrical potential between the at least one additional electrode assembly and the second electrode assembly.
    Type: Application
    Filed: May 6, 2002
    Publication date: November 6, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai
  • Patent number: 6638410
    Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: October 28, 2003
    Assignee: Semitool, Inc.
    Inventors: Linlin Chen, Thomas Taylor
  • Patent number: 6632345
    Abstract: In accordance with one embodiment of the invention, a process for applying a metal to a workpiece is set forth. The workpiece initially includes a seed layer deposited on at least a portion of a surface thereof that is generally unsuitable for bulk electrochemical deposition. The process starts with this workpiece and repairs the seed layer by depositing a metal using a first electrochemical deposition process to provide a repaired seed layer that is suitable for subsequent bulk electrochemical deposition. After the seed layer has been repaired, a bulk metal deposition over the repaired seed layer is executed by electrochemically depositing a bulk amount of a metal onto the repaired seed layer using a second electrochemical deposition process. The processing parameters of the second electrochemical deposition process are different from processing parameters used in the first electrochemical deposition process. A corresponding apparatus is also set forth.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: October 14, 2003
    Assignee: Semitool, Inc.
    Inventor: LinLin Chen
  • Publication number: 20030183530
    Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai, Winston Shue, Mong-Song Liang