Etching Of Coating Patents (Class 205/223)
  • Publication number: 20030121791
    Abstract: Various embodiments of the invention present techniques for forming structures (e.g. HARMS-type structures) via an electrochemical extrusion (ELEX™) process. Preferred embodiments perform the extrusion processes via depositions through anodeless conformable contact masks that are initially pressed against substrates that are then progressively pulled away or separated as the depositions thicken. A pattern of deposition may vary over the course of deposition by including more complex relative motion between the mask and the substrate elements. Such complex motion may include rotational components or translational motions having components that are not parallel to an axis of separation. More complex structures may be formed by combining the ELEX™ process with the selective deposition, blanket deposition, planarization, etching, and multi-layer operations of EFAB™.
    Type: Application
    Filed: October 15, 2002
    Publication date: July 3, 2003
    Applicant: University of Southern California
    Inventor: Adam L. Cohen
  • Patent number: 6552256
    Abstract: A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers each have a separate electrical connection and a common ground, thereby forming a three terminal device. The thermionic cooler is comprised of a superlattice barrier surrounded by cathode and anode layers grown onto an appropriate substrate, one or more metal contacts with a finite surface area deposited on top of the cathode layer, and one or more mesas of different areas formed by etching around the contacts to the anode layer. The thermoelectric cooler is defined by metal contacts deposited on the anode layer or the substrate itself. A backside metal is deposited on the substrate for connecting to the common ground.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: April 22, 2003
    Assignee: The Regents of the University of California
    Inventors: Ali Shakouri, Christopher J. LaBounty, John E. Bowers
  • Publication number: 20030066755
    Abstract: An anode of a cell for the electrowinning of aluminium comprises a nickel-iron alloy substrate having an openly porous nickel metal rich outer portion whose surface is electrochemically active. The outer portion is optionally covered with an external integral nickel-iron oxide containing surface layer which adheres to the nickel metal rich outer portion of the nickel-iron alloy and which in use is pervious to molten electrolyte. During use, the nickel metal rich outer portion contains cavities some or all of which are partly or completely filled with iron and nickel compounds, in particular oxides, fluorides and oxyfluorides.
    Type: Application
    Filed: June 3, 2002
    Publication date: April 10, 2003
    Inventors: Jean-Jacques Duruz, Thinh T. Nguyen, Vittorio De Nora
  • Patent number: 6544663
    Abstract: An object of the present invention is to provide a copper foil having excellent adhesion to an etching resist layer, without performing physical polishing such as buffing in pre-treatment of an etching process to form a circuit from the copper foil. To attain the object, in electroforming, a titanium material having a grain size number of 6.0 or more is employed as a copper deposition surface of the rotating drum cathode, and glue and/or gelatin is added in an amount of 0.2-20 mg/l to a copper sulfate solution, thereby producing a drum foil. An electrodeposited copper foil obtained from the drum foil, wherein 20% or more of the crystals present in a shiny side surface of the electrodeposited copper foil have a twin-crystal structure, is used for producing copper-clad laminates.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: April 8, 2003
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Osamu Nakano, Takashi Kataoka, Sakiko Taenaka, Naohito Uchida, Noriko Hanzawa
  • Patent number: 6531047
    Abstract: A surface modification method for an aluminum substrate, which comprises treating a Ni—P plated aluminum substrate with a functional water having a plus or minus oxidation-reduction potential for a predetermined period of time in a washing step after a polishing step of the Ni—P plated aluminum substrate.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: March 11, 2003
    Assignee: Mediken Inc.
    Inventors: Takamitsu Kato, Mitsugi Maekawa, Yuichi Hyakusoku, Tadao Tokushima, Masaaki Kato
  • Publication number: 20030038038
    Abstract: The present invention relates to a method for forming a planar conductive surface on a wafer. In one aspect, the present invention uses a no-contact process with electrochemical deposition, followed by a contact process with electrochemical mechanical deposition.
    Type: Application
    Filed: July 22, 2002
    Publication date: February 27, 2003
    Inventors: Bulent M. Basol, Cyprian E. Uzoh, Homayoun Talieh
  • Publication number: 20030034250
    Abstract: A method of immersing a substrate into electrolyte solution for electroplating, the method comprising connecting an electric source between an anode immersed in the electrolyte solution and a seed layer formed on the substrate. A first voltage level of the seed layer is biased to be equal to, or more positive than, a second voltage level of the anode. The substrate is then immersed into the electrolyte solution.
    Type: Application
    Filed: January 18, 2001
    Publication date: February 20, 2003
    Applicant: Applied Materials, Inc.
    Inventors: H. Peter W. Hey, Yezdi N. Dordi
  • Publication number: 20030019836
    Abstract: A method for the fabrication of electrical contacts using metal forming, masking etching, and soldering techniques is presented. The method produces a plurality of specialized electrical contacts, capable of use in an interposer, or other device, including non-permanent or permanent electrical connections providing contact wipe, soft spring rates, durability, and significant amounts of travel.
    Type: Application
    Filed: July 27, 2001
    Publication date: January 30, 2003
    Inventors: Bradley E. Clements, Joseph M. White
  • Patent number: 6500324
    Abstract: An electroplating system (30) and process makes electrical current density across, a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: December 31, 2002
    Assignee: Motorola, Inc.
    Inventors: Cindy Reidsema Simpson, Matthew T. Herrick, Gregory S. Etherington, James Derek Legg
  • Patent number: 6495020
    Abstract: The present invention is a method of producing an electrode probe assembly, comprising, providing a flexible polymer substrate bearing a coating of conductive material and using photolithography and electroplating to form a set of contacts and conductors on the flexible polymer substrate. A resilient material substrate is provided and laminated to the flexible polymer substrate. The assembly may be sized and shaped so that it may be driven through brain tissue.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: December 17, 2002
    Assignee: MicroHelix, Inc.
    Inventor: John W. Swanson
  • Patent number: 6475629
    Abstract: Adhesive film useful for the production of semiconductor devices is produced from a siloxane-modified polyamideimide resin composition, comprising 100 parts by weight of a siloxane-modified polyamideimide resin and 1 to 200 parts by weight of a thermosetting resin ingredient.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: November 5, 2002
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kazumasa Takeuchi, Tetsuya Saito, Ken Nanaumi
  • Publication number: 20020139682
    Abstract: Systems and methods to remove or lessen the size of metal particles that have formed on, and to limit the rate at which metal particles form or grow on, workpiece surface influencing devices used during electrodeposition are presented. According to an exemplary method, the workpiece surface influencing device is occasionally placed in contact with a conditioning substrate coated with an inert material, and the bias applied to the electrodeposition system is reversed. According to another exemplary method, the workpiece surface influencing device is conditioned using mechanical contact members, such as brushes, and conditioning of the workpiece surface influencing device occurs, for example, through physical brushing of the workpiece surface influencing device with the brushes. According to a further exemplary method, the workpiece surface influencing device is rotated in different direction during electrodeposition.
    Type: Application
    Filed: October 17, 2001
    Publication date: October 3, 2002
    Inventors: Bulent M. Basol, Cyprian Uzoh, Homayoun Talieh
  • Patent number: 6440288
    Abstract: Disclosed is a method for forming an aluminum oxide film of a large surface area on an electrode for a high voltage electrolytic capacitor. In accordance with the method, an oxide film of a uniform thickness is formed, prior to a process of etching the oxide film. A re-anodization is then partially conducted for an etched portion of the oxide film. The resultant oxide film has an increased surface area. The method of the invention makes it possible to prepare a dielectric oxide film having characteristics of a uniform thickness and a large surface area. In accordance with the invention, it is possible to expect an increase in the capacitance of electrolytic capacitors.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: August 27, 2002
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Su Il Pyun, Woo Jin Lee
  • Publication number: 20020112963
    Abstract: Methods are disclosed for manufacturing coils for use in a charged-particle-beam (CPB) optical system such as would be used in a CPB imaging apparatus or CPB lithography apparatus. In an embodiment, on a surface of a coil substrate is formed a mask layer defining channels corresponding to a coil pattern. Using the mask layer as a mask, a pattern of conductive coil-forming material is applied to the substrate surface in the channels. Coil elements formed on the substrate surface by this method exhibit steep sides and a desired aspect ratio. To such end, the depth of the channels desirably is greater than the desired thickness of the coil elements. Alternatively, a metal layer (for use as an electroplating electrode) is formed on a surface of the substrate. The metal layer is coated with a resist at a thickness of at least 0.1 mm. The resist is removed by lithography from regions where coil elements are to be formed. In the regions, conductive metal is grown by electroplating to form the coil elements.
    Type: Application
    Filed: February 22, 2002
    Publication date: August 22, 2002
    Applicant: Nikon Corporation
    Inventors: Katsushi Nakano, Ichiro Ono, Masami Masuko, Akira Okada
  • Publication number: 20020108864
    Abstract: The present invention relates to an arc processing method and device with simultaneous chemical etching wherein the device comprises a conductive electrode, being the cathode, an auxiliary electrode, being the anode, an conductive fluid, and an non-conductive work piece for processing. Processing, and precision processing in particular, of non-conductive materials is obtained by simultaneous arc discharge and etching that are brought about by chemical reactions associated with cathode and anode. Moreover, the present invention discloses simultaneous arc processing and chemical etching that offers improved processing efficiency over conventional arc processing.
    Type: Application
    Filed: February 9, 2001
    Publication date: August 15, 2002
    Applicant: Industrial Technology Research Institute
    Inventors: Ching-Tang Yang, Hung-Yin Tsai, Tung-Chuan Wu
  • Publication number: 20020100859
    Abstract: A mold for a microlens includes a substrate at least a portion of which is electrically conductive, such as an electrically-conductive substrate or a substrate with an electrode layer, an insulating mask layer formed on the substrate and including an opening or plural openings, and a plated layer electroplated in the opening and on the mask layer. A first condition that a diameter or width (&phgr;) of the opening has a relation of &phgr;≦0.35R, wherein (R) is a radius of curvature of the plated layer right above the opening, or a second condition that the diameter or width (&phgr;) of the opening is &phgr;≦10 &mgr;m, is met.
    Type: Application
    Filed: July 26, 1999
    Publication date: August 1, 2002
    Inventors: TAKAYUKI YAGI, YASUHIRO SHIMADA, TAKAYUKI TESHIMA, TAKASHI USHIJIMA
  • Patent number: 6406607
    Abstract: An inkjet printer nozzle plate having a non-wetting surface of uniform thickness and an orifice wall of tapered contour, and method of making the nozzle plate. In the method a metal masking layer is deposited on a glass substrate, the masking layer having an opening therethrough for passage of light only through the opening. Next, a negative photoresist layer is deposited on the masking layer, the negative photoresist layer being capable of photochemically reacting with the light. A light source passes light through the substrate, so that the light also passes only through the opening in the form of a tapered light cone. This tapered light cone will define the tapered contour of a nozzle plate orifice wall to be formed. The negative photoresist layer photochemically reacts with the light only in the light cone to define a light-exposed region of hardened negative photoresist.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: June 18, 2002
    Assignee: Eastman Kodak Company
    Inventors: Jeffrey I. Hirsh, Edwin A. Mycek, Larry L. Lapa
  • Publication number: 20020070118
    Abstract: A method for forming a nanolaminate structure is provided which comprises plating a substrate with layers of substantially a first metal and substantially a second metal using an electrolytic plating process and controlling the plating current to obtain a desired current density at the cathode, which is maintained within a predefined range.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventors: Chris M. Schreiber, Mordechay Schlesinger, Robert Martinez, Haim Feigenbaum, William Robert Crumly
  • Patent number: 6375822
    Abstract: A process for enhancing the solderability of a surface, particularly copper surfaces upon printed circuit boards, is disclosed. The surface is plated using a silver plating solution. The plated surface is then further treated with a solution that comprises an organic heterocyclic mercapto compound and most preferably an alkali metal hydroxide.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: April 23, 2002
    Inventor: Lev Taytsas
  • Patent number: 6368484
    Abstract: A method is described for electroplating a metal structure in a feature formed in a substrate. A seed layer of the metal is deposited on the top surface and on the bottom and sidewalls of the feature. The seed layer is then selectively removed from the top surface, so that only a portion of the seed layer remains in the feature on at least the bottom thereof. The metal is then electroplated using this portion of the seed layer, so that the metal fills the feature. The removal of the seed layer from the top surface causes no electroplating to occur on the top surface.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: April 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, Peter S. Locke, Kevin S. Petrarca, David M. Rockwell, Seshadri Subbanna
  • Patent number: 6361627
    Abstract: A process for controlling grain growth in the microstructure of thin metal films (e.g., copper or gold) deposited onto a substrate. In one embodiment, the metal film is deposited onto the substrate to form a film having a fine-grained microstructure. The film is heated in a temperature range of 70-100°C. for at least five minutes, wherein the fine-grained microstructure is converted into a stable large-grained microstructure. In another embodiment, the plated film is stored, after the step of depositing, at a temperature not greater than −20° C., wherein the fine-grained microstructure is stabilized without grain growth for the entire storage period.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: March 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Patrick W. DeHaven, Charles C. Goldsmith, Jeffery L. Hurd, Suryanarayana Kaja, Michele S. Legere, Eric D. Perfecto
  • Patent number: 6325909
    Abstract: A method of producing Y-junction carbon nanotubes. An alumina template with branched growth channels is produced after which individual Y-junction carbon nanotubes are grown directly by pyrolysis of acetylene using cobalt catalysis. The use of a branched growth channel allows the natural simultaneous formation of a very large number of individual but well-aligned three-port Y-junction carbon nanotubes with excellent uniformity and control over the length (up to several tens &mgr;m) and diameter (15-100 nm) of the “stem” and “branches” separately. These Y-junctions offer the nanoelectronics community a new base material for molecular scale electronic devices including for example transistors and rectifiers.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: December 4, 2001
    Assignee: The Governing Council of The University of Toronto
    Inventors: Jing Li, Christo Papadopoulos, Jingming Xu
  • Publication number: 20010042690
    Abstract: The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surface of the wafer, when the wafer is disposed between a cathode and an anode, and preventing accumulation of the conductive material to areas other than the predetermined area by mechanically polishing the other areas while the conductive material is being applied.
    Type: Application
    Filed: December 14, 2000
    Publication date: November 22, 2001
    Applicant: NuTool, Inc.
    Inventor: Homayoun Talieh
  • Patent number: 6299752
    Abstract: An anode foil treatment method produces a useful high quality oxide with inherently high capacitance at voltages as high as 750 Volts or more. The anode foil treatment method comprises a series of formation and relaxation steps. Oxide layer formation is performed in a forming mixture that includes a high molecular weight dicarboxylic acid that is made into a salt and a strong base. The concentration of the dicarboxylic acid is carefully monitored and kept within a narrow band. The complex by-product of the dicarboxylic salt created during formation process is kept below a fixed maximum level.
    Type: Grant
    Filed: March 10, 1999
    Date of Patent: October 9, 2001
    Assignee: Pacesetter, Inc.
    Inventors: Thomas F. Strange, Timothy R. Marshall
  • Patent number: 6290836
    Abstract: An electrode (1) having an active surface for contacting an electrolyte. The electrode (1) comprises first and second metallic materials (2, 3) arranged to provide a number of first metallic material to second metallic material interfaces at the active surface. The invention also relates to a method of making such an electrode (1) and to an electrolysis cell provided with such an electrode (1).
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: September 18, 2001
    Inventor: Christopher Robert Eccles
  • Patent number: 6270647
    Abstract: A system for electroplating a semiconductor wafer is set forth. The system comprises a first electrode in electrical contact with the semiconductor wafer and a second electrode. The first electrode and the semiconductor wafer form a cathode during electroplating of the semiconductor wafer. The second electrode forms an anode during electroplating of the semiconductor wafer. A reaction container defining a reaction chamber is also employed. The reaction chamber comprises an electrically conductive plating solution. At least a portion of each of the first electrode, the second electrode, and the semiconductor wafer contact the plating solution during electroplating of the semiconductor wafer. An auxiliary electrode is disposed exterior to the reaction chamber and positioned for contact with plating solution exiting the reaction chamber during cleaning of the first electrode to thereby provide an electrically conductive path between the auxiliary electrode and the first electrode.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: August 7, 2001
    Assignee: Semitool, Inc.
    Inventors: Lyndon W. Graham, Kyle Hanson, Thomas L. Ritzdorf, Jeffrey I. Turner
  • Patent number: 6268017
    Abstract: A method for providing a partial plating to a lead pin, comprising the steps of plating an entire surface of the lead pin; covering a first part of a plated surface of the lead pin by a gel member; and subjecting a second part of the plated surface of the lead pin, which extends out of the gel member, to a metal-coating removing agent, to remove a metal coating of the second part of the plated surface. The plating step may include providing a composite plating on the entire surface of the lead pin, and the subjecting step may include removing an uppermost metal layer of the composite plating by the metal-coating removing agent. The composite plating may include a nickel base layer and a gold uppermost layer deposited on the nickel base layer. The gel member may be formed from a non-oily clay or paper-mache for handcraft use.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: July 31, 2001
    Assignee: Fujitsu Takamisawa Component Limited
    Inventors: Masayuki Takeuchi, Katsumasa Yoshinari, Kazuyiki Futaki, Kouji Nishimura, Yoshinobu Miyanoo, Ryoji Arai, Nobuyuki Takei
  • Patent number: 6231744
    Abstract: An array of nanowires having a relativley constant diameter and techniques and apparatus for fabrication thereof are described. In one embodiment, a technique for melting a material under vacuum and followed by pressure injection of the molten material into the pores of a porous substrate produces continuous nanowires. In another embodiment, a technique to systematically change the channel diameter and channel packing density of an anodic alumina substrate includes the steps of anodizing an aluminum substrate with an electrolyte to provide an anodic aluminum oxide film having a pore with a wall surface composition which is different than aluminum oxide and etching the pore wall surface with an acid to affect at least one of the surface properties of the pore wall and the pore wall composition.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: May 15, 2001
    Assignee: Massachusetts Institute of Technology
    Inventors: Jackie Y. Ying, Zhibo Zhang, Lei Zhang, Mildred S. Dresselhaus
  • Patent number: 6224738
    Abstract: This present invention is directed to a method of etching anodic foil for electrolytic capacitors and provides a method of electrolytically growing a porous oxide mask on a surface of a high purity etchable strip of anodic foil for forming etch tunnels at strategic locations on the foil. Unetched high purity aluminum foil is placed in a prepared electrolyte doped with chloride. By passing current through the foil, a porous oxide mask is formed on the surface of the anode foil, with an optimized pore spacing. This oxide mask is then partially removed with a stripping agent in order to expose the underlying anode foil at the bottom of the mask pores to the etch solution. The mask is not removed completely, and the anode foil is exposed only at the pore sites. The foil can then be etched using a conventional etch solution. Etch pits and tunnels form only at the pore sites.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: May 1, 2001
    Assignee: Pacesetter, Inc.
    Inventors: Katherine Crawford Sudduth, Thomas Flavian Strange
  • Patent number: 6174425
    Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: January 16, 2001
    Assignee: Motorola, Inc.
    Inventors: Cindy Reidsema Simpson, Matthew T. Herrick, Gregory S. Etherington, James Derek Legg
  • Patent number: 6143157
    Abstract: A shield is applied to a permeable core in a predetermined pattern, where the predetermined pattern covers less than the entire surface area of the permeable core.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: November 7, 2000
    Assignee: VLT Corporation
    Inventors: Lance L. Andrus, Cruz R. Calderon, Craig R. Davidson, Patrizio Vinciarelli
  • Patent number: 6139713
    Abstract: A plurality of recesses having the same interval and array as those of pores of an alumina film, which are to be formed in anodizing, are formed on a smooth surface of an aluminum plate in advance, and then, the aluminum plate is anodized. With this process, the roundness of the pores of the porous anodized alumina film and the uniformity of pore size are improved, and the pores are regularly arrayed at a predetermined interval. The recesses are formed by pressing a substrate having a plurality of projections on its surface against the aluminum plate surface to be anodized.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: October 31, 2000
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hideki Masuda, Masashi Nakao, Toshiaki Tamamura
  • Patent number: 6136208
    Abstract: The present invention discloses a planar microprobe and method of manufacturing the same. The present invention utilizes semiconductor process technologies that includes electroplating technology and sacrificial layer technology to integrate constituent elements on a silicon wafer having an insulator layer. The planar microprobe comprises: an upper cantilever beam including a first electrode; a supporting pad coupled to the upper cantilever beam; and a lower cantilever beam coupled to the supporting pad, situated below the upper cantilever beam and spaced by a distance from the upper cantilever beam. Besides, the lower cantilever beam comprises: a second electrode in cooperation with the first electrode to control a vertical displacement of the lower cantilever beam by applying an external voltage thereto. A tip is coupled to the second electrode. The microprobe is manufactured by depositing a photoresist sacrificial layer on a lower cantilever beam. Metal is electroplated to form an upper cantilever beam.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: October 24, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Rou-Fu Chou, Wen-Syang Hsu, Shih-Che Lo, Hsi-Fu Lin
  • Patent number: 6099745
    Abstract: In a rigid/flex circuit board and fabricating process, patterns of electrical traces are formed by etching conductive layers on outer surfaces of a flexible multi-layer circuit structure. A protective barrier material is deposited on the etched traces using an "electroless" process, such as immersion of the flexible circuit board in an aqueous solution containing ionic tin. The protective barrier material adheres to and encapsulates the copper traces. An outer circuit structure including a bondfilm of epoxy-impregnated fiberglass ("prepreg" bondfilm) and a copper foil layer is laminated onto the flexible circuit structure. The prepreg bondfilm has a window area removed by routing or an equivalent process prior to being laminated to the flexible structure. The window area defines a flex area of the rigid/flex circuit board that will be relatively flexible.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: August 8, 2000
    Assignee: Parlex Corporation
    Inventors: Darryl McKenney, Arthur Demaso, Craig Wilson
  • Patent number: 6056864
    Abstract: In-laid metal, e.g., copper or copper alloy, contacts and conductive routing patterns are formed in recesses in the surface of a substrate by a damascene-type process, comprising depositing a layer of an electrically conductive material filling the recesses and covering the substrate surface, reducing the thickness of the layer by a process providing a faster rate of layer removal than that obtained by chemical-mechanical polishing (CMP), and subjecting the remaining layer thickness to CMP processing to (a) substantially remove the remaining layer thickness and (b) render the exposed upper surface of the material filling the recesses substantially coplanar with the substrate surface, whereby increased manufacturing throughput, greater planarity, and reduced defects are obtained.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: May 2, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Robin W. Cheung
  • Patent number: 6045677
    Abstract: A microchannel plate and method of manufacturing same is provided. The microchannel plate includes a plate consisting of an anodized material and a plurality of channels which are formed during the anodization of the material and extend between the two sides of the plate. Electrodes are also disposed on each side of the plate for generating an electrical field within the channels. Preferably, the material is alumina and the channels are activated such that the channel walls are conductive and highly secondary emissive.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: April 4, 2000
    Assignee: NanoSciences Corporation
    Inventors: Charles P. Beetz, Jr., Robert W. Boerstler, John Steinbeck, David R. Winn
  • Patent number: 5997709
    Abstract: Methods of providing diffusing risers on a fresnel lens die having a plurality of optical facets, wherein adjacent optical facets are separated by a riser, the method including the steps of depositing a difflusing layer on the plurality of optical facets and the risers, and selectively removing the diffusing layer from the plurality of optical facets, wherein the diffusing layer remains substantially intact on the risers. The diffusing layer can be deposited in an electrolyte bath substantially free of grain refiners.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: December 7, 1999
    Assignee: Minnesota Mining and Manufacturing Co.
    Inventor: Harlan L. Krinke
  • Patent number: 5997713
    Abstract: An element with elongated, high aspect ratio channels such as microchannel plate is fabricated by electrochemical etching of a p-type silicon element in a electrolyte to form channels extending through the element. The electrolyte may be an aqueous electrolyte. For use as a microchannel plate, the; the silicon surfaces of the channels can be converted to insulating silicon dioxide, and a dynode material with a high electron emissivity can be deposited onto the insulating surfaces of the channels. New dynode materials are also disclosed.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: December 7, 1999
    Assignee: NanoSciences Corporation
    Inventors: Charles P. Beetz, Jr., Robert W. Boerstler, John Steinbeck, David R. Winn
  • Patent number: 5989405
    Abstract: A dresser includes a super-abrasive fixed by electroplating on a working face which is disposed perpendicular to the axis of rotation of the dresser, the height of protrusion of particles of the super-abrasive is 5 to 30% of an average diameter of the particles, and a process for producing such a dresser includes temporarily fixing the super-abrasive in an amount to form a single layer to a base metal by electroplating, removing loose stones in the temporarily fixed super-abrasive by a grinder or shaking, electroplating a surface having the temporarily fixed super-abrasive with a metal until thickness of the plating metal reaches height of the most protruded part of the super-abrasive or until particles of the super-abrasive are completely buried in the plating metal, and working the electroplated surface for abrasive protrusion to expose most protruded parts of the super-abrasive resulting in a high accuracy dresser which enables dressing of a polishing pad in a short time and eliminates the releasing of par
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: November 23, 1999
    Assignee: Asahi Diamond Industrial Co., Ltd.
    Inventors: Yasunori Murata, Kenji Kakui
  • Patent number: 5944976
    Abstract: A process for forming adjacent moats or holes in an electrically non-insulating substrate wherein an electrically insulating masking layer is deposited on the substrate. To form two adjacent moats or holes, the masking layer has an opening whose width is chosen so that it extends over a part of the overall width of the two moats or holes to be formed, and whose shape corresponds to the shape of the moats or holes to be formed. The surface of the masked substrate is then subjected to an anodic oxidation, with the oxidation voltage chosen to be so high that two adjacent moats or holes are formed per opening in the masking layer.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: August 31, 1999
    Assignee: Micronas Intermetall GmbH
    Inventor: Gunter Igel
  • Patent number: 5944975
    Abstract: A method of fabricating an emitter plate 12 for use in a field emission device comprising the steps of providing an insulating substrate 18 and forming a first conductive layer 13 on the insulating substrate 18. This is followed by the steps of forming an insulating layer 20 on the first conductive layer 13 and forming a second conductive layer 22 on the insulating layer 20. Then, a plurality of apertures 34 are formed through the second conductive layer 22 and through the insulating layer 20. A lift-off layer 36 is then formed on the second conductive layer 22. The lift-off layer 36 is formed by a plating process wherein the plating bath has a pH between 2.25 and 4.5, and current densities of 1 to 2O mA/cm.sup.2. The method may further comprise depositing conductive material through the plurality of apertures 34 to form a microtip 14 in each of the plurality of apertures 34. The excess deposited conductive material 14' and the lift-off layer 36 are then removed from the second conductive layer 22.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: August 31, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Arthur M. Wilson, Chi-Cheong Shen, Saroja Ramamurthi
  • Patent number: 5911863
    Abstract: In a method of manufacturing foils of plastic material which are electrically conductive in a transverse direction, but not in the plane of the foil wherein micropassages are formed in the foil by etching nucleus traces which are generated by exposure to a heavy ion beam, conductive layers are deposited on one side of the foil and the micropassages are filled by electrolytic metal ion depositions from the other side until caps are formed on the passages. After dissolving the two conductive layers, the steps are repeated to form caps also on the passages at the other side of the foil so as to provide for good contacting capabilities at both sides of the foil.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: June 15, 1999
    Assignee: Gesellschaft fur Schwerionenforschung mbH
    Inventors: Johann Vetter, Dobri Dobrev, Norbert Angert
  • Patent number: 5902475
    Abstract: Disclosed herewithin is a method of fabricating a stent which involves processing a tubular member whereby no connection points to join the edges of a flat pattern are necessary. The method includes the steps of a) removing contaminates from a tubular member, b) coating the outside surface of the tubular member with a photo-sensitive resist material, c) placing the tubular member in an apparatus designed to simultaneously rotate the tubular member while passing a specially configured photographic frame negative between a UV light source and the tubular member, thereby exposing a specified pattern of UV light to the resist coated tubular member, d) exposing the outside surface of the tubular member to a photoresist developer for a specified period of time, e) rinsing the excess developer and uncured resist from the outside surface of the tubular member, f) treating the tubular member with a electro-chemical process to remove uncovered metal.
    Type: Grant
    Filed: April 8, 1997
    Date of Patent: May 11, 1999
    Assignee: Interventional Technologies, Inc.
    Inventors: Thomas Trozera, Gary W. Gomringer
  • Patent number: 5858198
    Abstract: A process for electroplating a metal clad substrate by coating the substrate with a coating of carbonaceous particles. The coating of particles is applied to the substrate from an aqueous dispersion and then the coating is saturated with an etchant for the metal cladding on the substrate to undercut the carbonaceous coating and facilitate its removal from areas where plating is undesired.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: January 12, 1999
    Assignee: Shipley Company, L.L.C.
    Inventors: Steven M. Florio, Jeffrey P. Burress, Carl J. Colangelo, Edward C. Couble, Mark J. Kapeckas
  • Patent number: 5811215
    Abstract: According to the present invention there is provided a method for preparing a hydrophilic surface of an aluminum lithographic base comprising the steps of roughening and anodizing a side of an aluminum foil and sealing said side of the aluminum foil with hot water within a temperature range from 70.degree. C. to 100.degree. C. for at least 5 seconds and rinsing said side of the aluminum foil with water characterized in that between said hot water treatment and said rinsing said side of the aluminum foil is treated with an aqueous silicate solution within a temperature range from 70.degree. C. to 100.degree. C. for at least 5 seconds.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: September 22, 1998
    Assignee: Agfa-Gevaert, N.V.
    Inventors: Marc Van Damme, Joan Vermeersch
  • Patent number: 5738776
    Abstract: A process for electroplating a metal clad substrate by coating the substrate with a coating of carbonaceous particles. The coating of particles is applied to the substrate from an aqueous dispersion and then the coating is saturated with an etchant for the metal cladding on the substrate to undercut the carbonaceous coating and facilitate its removal from areas where plating is undesired.
    Type: Grant
    Filed: January 19, 1996
    Date of Patent: April 14, 1998
    Assignee: Shipley Company, L.L.C.
    Inventors: Steven M. Florio, Jeffrey P. Burress, Carl J. Colangelo, Edward C. Couble, Mark J. Kapeckas
  • Patent number: 5705027
    Abstract: The method is to selectively etch the etching residue in non-conductive state occurring in semiconductor manufacturing process. A silicon substrate cassette is used in such selective etching.In removing the etching residue in non-conductive state occurring in semiconductor manufacturing process, by applying a positive potential to part of conductive silicon substrates in an etching solution, the contact surfaces between the silicon substrates and the portion electrically connected thereto and the chemical etching solution are anodically oxidized to protect with a passive film, while only the etching residue in non-conductive state is selectively removed by isotropic etching, thereby achieving the purpose.
    Type: Grant
    Filed: November 1, 1995
    Date of Patent: January 6, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiharu Katayama, Naoko Ootani
  • Patent number: 5681443
    Abstract: An electrolytic cell comprised of a tank for holding electrolytic solution, and a drum rotatable about a horizontal axis having a non-conductive cylindrical outer surface disposed within the tank, and a plurality of elongated, like anodes arranged about the outer surface of the drum. The anodes together form a generally continuous cylindrical surface spaced from, and generally conforming to, the outer surface of the drum. Each of the anodes has at least one end projecting through the tank. A plurality of power sources is provided together with connection means for connecting groups of one or more of the projecting ends of the anodes to each power source.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: October 28, 1997
    Assignee: Gould Electronics Inc.
    Inventors: Thomas J. Ameen, Robert D. DeWitt, Peter Peckham, Ronald K. Haines, Adam G. Bay
  • Patent number: 5650042
    Abstract: In an SOI substrate having a base substrate, an insulating film and a semiconductor active layer, a potential difference is given between the base substrate and an etching solution or among the base substrate, the semiconductor active layer and the etching solution to form a uniform depletion layer on the active layer side from the interface between the insulating film and the active layer. The semiconductor active layer is uniformly thinned down by etching using a solution or by the combination of chemical or electro-chemical surface and etching with the resultant reaction product. In this case, the individual electrodes are provided with seal members to prevent the base substrate electrode and the active layer electrode from contacting the etching solution or the reaction solution due to the etching using the etching solution or the chemical reaction using the reaction solution.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: July 22, 1997
    Assignee: NEC Corporation
    Inventor: Atsushi Ogura
  • Patent number: 5645707
    Abstract: In a bonding method for a chip-type electronic part, the electronic part is prefixed onto an element-mounting section of a wiring substrate by using a non-conductive adhesive agent while an external metal electrode of the electronic part is brought close to, or in contact with the metal wiring pattern formed on the wiring substrate. Then, the wiring substrate, on which the electronic part has been prefixed, is subjected to an electroplating process while it is immersed into plating liquid containing a metal component, so that the metal component, which is deposited on the metal wiring pattern, grows to form a metal layer, and the external metal electrode and the metal wiring pattern are thus electrically connected to each other through the metal layer.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: July 8, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masatoshi Omoto