Forming Or Treating Mask Used For Its Nonetching Function (e.g., Shadow Mask, X-ray Mask, Etc.) Patents (Class 216/12)
  • Patent number: 11787689
    Abstract: A MEMS sensor with a media access opening in its carrier board. The MEMS sensor has an integrally filter mesh closing the media access opening. The mesh can be applied in unstructured form over the whole surface of the carrier board. Then, a structuring is performed to produce preferably at the same time a perforation forming the filter mesh.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: October 17, 2023
    Assignee: TDK Corporation
    Inventor: Wolfgang Pahl
  • Patent number: 11508908
    Abstract: A method for manufacturing a mask may include the following steps: preparing a substrate; providing a first coating, which may be optically transparent, may cover a covered portion of the substrate, and may expose exposed portions of the substrate; forming a scattering layer between the first coating layer and the covered portion of the substrate; and removing the exposed portions of the substrate to form mask holes.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 22, 2022
    Inventors: Jeongkuk Kim, Kyuhwan Hwang
  • Patent number: 11296012
    Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu
  • Patent number: 11203528
    Abstract: Solid or liquid N—H free, C-free, and Si-rich perhydropolysilazane compositions comprising units having the following formula [—N(SiH3)x(SiH2—)y], wherein x=0, 1, or 2 and y=0, 1, or 2 when x+y=2; and x=0, 1 or 2 and y=1, 2, or 3 when x+y=3 are disclosed. Also disclosed are synthesis methods and applications for the same.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: December 21, 2021
    Assignees: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude, American Air Liquide, Inc.
    Inventors: Antonio Sanchez, Gennadiy Itov, Manish Khandelwal, Cole Ritter, Peng Zhang, Jean-Marc Girard, Zhiwen Wan, Glenn Kuchenbeiser, David Orban, Sean Kerrigan, Reno Pesaresi, Matthew Damien Stephens, Yang Wang, Guillaume Husson
  • Patent number: 11201078
    Abstract: Methods and apparatus for substrate position calibration for substrate supports in substrate processing systems are provided herein. In some embodiments, a method for positioning a substrate on a substrate support includes: obtaining a plurality of backside pressure values corresponding to a plurality of different substrate positions on a substrate support by repeatedly placing a substrate in a position on the substrate support, and vacuum chucking the substrate to the substrate support and measuring a backside pressure; and analyzing the plurality of backside pressure values to determine a calibrated substrate position.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 14, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tomoharu Matsushita, Aravind Kamath, Jallepally Ravi, Cheng-Hsiung Tsai, Hiroyuki Takahama
  • Patent number: 11085110
    Abstract: Provided is a method of manufacturing a mask includes preparing a first conductive layer. The first conductive layer includes a third portion having a mesh shape in a plurality of cell regions on a substrate, a second portion disposed between the cell regions, and a first portion surrounding the third portion and the second portion. The method further includes preparing a second conductive layer including at least one opening on the first conductive layer. The method also includes oxidizing a part of the first conductive layer exposed through the at least one opening of the second conductive layer. The method further includes preparing a plating layer on the first conductive layer and the second conductive layer, and removing the first conductive layer and the second conductive layer from the plating layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 10, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Hyunjun Kim
  • Patent number: 10978300
    Abstract: Embodiments are disclosed that reduce gouging during multi-patterning processes using thermal decomposition materials. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as cores during multiple patterning processes. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as a gap fill material during multiple patterning processes. By using thermal decomposition material, gouging of an underlying layer, such as a hard mask layer, can be reduced or suppressed for patterned structures being formed using the self-aligned multi-patterning processes because more destructive etch processes, such as plasma etch processes, are not required to remove the thermal decomposition materials.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 13, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuki Kikuchi, Toshiharu Wada, Kaoru Maekawa, Akiteru Ko
  • Patent number: 10964606
    Abstract: A film forming system is to form an organic film on a substrate having a pattern formed on a surface thereof, includes: an organic film formation section configured to perform an organic film formation treatment on the substrate to form the organic film on the substrate; a film thickness measurement section configured to measure a film thickness of the organic film on the substrate; and an ultraviolet treatment section configured to perform an ultraviolet irradiation treatment on the organic film on the substrate to remove a surface of the organic film. In the film forming system, the organic film formation section, the film thickness measurement section, and the ultraviolet treatment section are disposed side by side in this order along a transfer direction of the substrate.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: March 30, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Satoru Shimura, Masashi Enomoto
  • Patent number: 10720328
    Abstract: An etching method for etching an etching target film using a first organic film processed to have a plurality of line patterns formed on the etching target film, an oxide film conformally formed on a front surface of the etching target film so as to provide a space between adjacent line patterns, and a second organic film formed to embed the space, includes etching back the second organic film and the oxide film using an etching gas whose etching selection ratio is adjusted for the second organic film based on a line width and a width of the space so as to cause an upper surface of the first organic film to be exposed, removing the oxide film between the line pattern and the space, and etching the etching target film using the first organic film and the second organic film as a mask.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 21, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Hotaka Maruyama, Katsunori Tanaka
  • Patent number: 10665785
    Abstract: A method of manufacturing a mask includes attaching a first mask base substrate and a second mask base substrate to opposite sides of an adhesive layer, forming a photoresist layer on the first and second mask base substrates, exposing and developing the photoresist layer to remove the photoresist layer on effective area at centers of surfaces of the first and second mask base substrates such that the first photoresist layer remains on non-effective areas at edges of surfaces of the first mask base substrate and the second mask base substrate, etching the effective area to form a stepped groove on the first and second mask base substrates, separating the first and second mask base substrates from the adhesive layer, and forming a pattern hole in the effective area of first and second mask base substrates, each with the first stepped groove thereon.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youngdae Kim, Sangjin Park, Minjae Jeong
  • Patent number: 10643874
    Abstract: A substrate liquid processing apparatus includes a liquid processing unit, a processing liquid circulating line, and a boiling state detecting unit provided in a processing bath of the liquid processing unit. The controller controls a supply pump of the processing liquid circulating line based on a signal from the boiling state detecting unit, and adjusts a pressure of a supplied phosphoric acid aqueous solution in a flow path so as to adjust the boiling state of the phosphoric acid aqueous solution to a desired state.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 5, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Tanaka, Tsukasa Hirayama, Takao Inada
  • Patent number: 10585112
    Abstract: Provided is an acceleration sensor capable of realizing a simultaneous operation method of signal detection and servo control in place of a time-division processing method, by an MEMS process in which a manufacturing variation is large. The acceleration sensor is an MEMS capacitive acceleration sensor and has capacitive elements for signal detection and capacitive elements for servo control different from the capacitive elements for the signal detection. A voltage to generate force in a direction reverse to a detection signal of acceleration by the capacitive elements for the signal detection is applied to the capacitive elements for the servo control.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: March 10, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takashi Oshima, Yuki Furubayashi
  • Patent number: 10497534
    Abstract: An aperture system of an electron beam apparatus includes a plurality of apertures each including a first area including at least one through hole allowing an electron beam to pass therethrough and a second area disposed outside the first area and including first and second alignment keys, wherein two apertures, among the plurality of apertures, include the first alignment keys arranged in mutually overlapping positions and having the same size, and an aperture, excluding the two apertures, among the plurality of apertures, includes the second alignment keys arranged to overlap the first alignment keys and having an area larger than an area of the first alignment keys.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Ho Lee, Jong Mun Park, Byoung Sup Ahn, Jin Choi, Shuichi Tamamushi
  • Patent number: 10394114
    Abstract: The present disclosure provides a phase shift mask. The phase shift mask includes a transparent substrate; an etch stop layer disposed on the substrate; and a tunable transparent material layer disposed on the etch stop layer and patterned to have an opening, wherein the tunable transparent material layer is designed to provide phase shift and has a transmittance greater than 90%.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee
  • Patent number: 10339260
    Abstract: A method of determining a characteristic of a guiding template for guiding self-assembly of block copolymer to form an entirety of a design layout, or a portion thereof, including a plurality of design features, each design feature including one or more elemental features, the method including selecting a characteristic of a guiding template for each of the one or more elemental features of the plurality of design features from a database or a computer readable non-transitory medium, the database or the computer readable non-transitory medium storing a characteristic of a guiding template for each of the one or more elemental features, and determining the characteristic of the guiding template to form the entirety of the design layout, or the portion thereof, by combining the selected characteristic of the guiding template for the one or more elemental features for each of the plurality of design features.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: July 2, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Bart Laenens, Sander Frederik Wuister
  • Patent number: 10319583
    Abstract: Methods for forming a spacer comprising depositing a film on the top, bottom and sidewalls of a feature and treating the film to change a property of the film on the top and bottom of the feature so that the film can be selectively etched from the top and bottom of the feature relative to the film on the sidewalls of the feature.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 11, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Ning Li, Mihaela Balseanu, Li-Qun Xia
  • Patent number: 10134581
    Abstract: Methods for forming a spacer comprising depositing a film on the top, bottom and sidewalls of a feature and treating the film to change a property of the film on the top and bottom of the feature. Selectively dry etching the film from the top and bottom of the feature relative to the film on the sidewalls of the feature using a high intensity plasma.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: November 20, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Ning Li, Mihaela Balseanu, Li-Qun Xia, Dongqing Yang, Anchuan Wang
  • Patent number: 9925759
    Abstract: A printing screen for and method of printing elongate structures on substrates (S), the printing screen comprising first and second layers (3, 5) of different material, the first layer (3) providing a surface over which a printing element is in use traversed and including a plurality of elongate first printing apertures (7) across which extend a plurality of bridges (9) at spaced intervals, and the second layer (5) in use overlying the substrate (S) and including a plurality of elongate second printing apertures (15) through which printing medium is in use printed onto the underlying substrate (S), each of the second printing (15) apertures being located in registration with respective ones of the first printing apertures (7) in the first layer (3).
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: March 27, 2018
    Assignee: ASM Assembly Systems Switzerland GmbH
    Inventor: Tom Falcon
  • Patent number: 9880215
    Abstract: An inspection method for a blanking device for multi-beams, for inspecting whether a separate blanking system of the blanking device is defective, includes, using the blanking device, measuring a value of current flowing from a power source for supplying voltage based on a difference between a first potential and a second potential to each of a plurality of separate blanking systems, in a state where the first potential is applied to a first electrode from a first potential applying unit and the second potential is applied to a second electrode from a corresponding second potential applying unit in at least one second potential applying unit in each of a plurality of separate blanking systems of the blanking device, and determining, when a measured current value is a finite value and equal to or below a preset threshold, that a separate blanking system where a short circuit has occurred exists.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: January 30, 2018
    Assignee: NuFlare Technology, Inc.
    Inventor: Hiroshi Yamashita
  • Patent number: 9835955
    Abstract: Described herein is a method for simulating an image formed within a resist layer on a substrate resulting from an incident radiation, wherein the method accounts for scattering of the incident radiation due to features in or underlying the resist layer. Embodiments of the invention include calculating a forward propagating electric field or forward propagating magnetic field resultant from the incident radiation at a depth in the resist layer, calculating a backward propagating electric field or backward propagating magnetic field resultant from the incident radiation at the depth in the resist layer, and calculating a radiation field at the depth in the resist layer from the forward propagating electric field or forward propagating magnetic field and from the backward propagating electric field or backward propagating magnetic field.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: December 5, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventor: Peng Liu
  • Patent number: 9812325
    Abstract: Techniques herein provide a process to reform or flatten asymmetric spacers to form a square profile which creates symmetric spacers for accurate pattern transfer. Initial spacer formation typically results in spacer profiles with a curved or sloped top surfaces. This asymmetric top surface is isolated while protecting a remaining lower portion of the spacer. The top surface is removed using a plasma processing step resulting in spacers having a squared profile that enables further patterning and/or accurate pattern transfer.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: November 7, 2017
    Inventors: Nihar Mohanty, Akiteru Ko
  • Patent number: 9755059
    Abstract: A transistor device including a cap layer is described. One embodiment of such a device includes cap layer between a gate and a semiconductor layer. In one embodiment, the thickness of the cap layer is between 5 nm and 100 nm. In another embodiment, the cap layer can be doped, such as delta-doped or doped in a region remote from the semiconductor layer. Devices according to the present invention can show capacitances which are less drain bias dependent, resulting in improved linearity.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: September 5, 2017
    Assignee: CREE, INC.
    Inventor: Saptharishi Sriram
  • Patent number: 9711366
    Abstract: Methods of selectively etching metal-containing materials from the surface of a substrate are described. The etch selectively removes metal-containing materials relative to silicon-containing films such as silicon, polysilicon, silicon oxide, silicon germanium and/or silicon nitride. The methods include exposing metal-containing materials to halogen containing species in a substrate processing region. A remote plasma is used to excite the halogen-containing precursor and a local plasma may be used in embodiments. Metal-containing materials on the substrate may be pretreated using moisture or another OH-containing precursor before exposing the resulting surface to remote plasma excited halogen effluents in embodiments.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 18, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Nitin K. Ingle, Jessica Sevanne Kachian, Lin Xu, Soonam Park, Xikun Wang, Jeffrey W. Anthis
  • Patent number: 9577134
    Abstract: Methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells, are described. In an example, a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. The method also involves implanting, through a stencil mask, dopant impurity atoms in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. The method also involves forming, through the stencil mask, a capping layer on and substantially in alignment with the implanted regions of the silicon layer. The method also involves removing the non-implanted regions of the silicon layer, wherein the capping layer protects the implanted regions of the silicon layer during the removing. The method also involves annealing the implanted regions of the silicon layer to form doped polycrystalline silicon emitter regions.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: February 21, 2017
    Assignee: SunPower Corporation
    Inventor: Timothy Weidman
  • Patent number: 9529127
    Abstract: A method producing a refractive or diffractive optical device, including: production, in a first layer, of at least one inclined general profile approximated by a staircase profile including plural stairsteps; production of the profile including: forming buffer patterns on the first layer and at least one sequence including: forming masking patterns, so each masking pattern includes at least one edge situated above a buffer pattern and covers at least one area of the first layer not masked by the buffer patterns, the forming the masking patterns also defining, for the first layer, plural free areas not masked by the masking patterns or by the buffer patterns; etching the free areas to form trenches in the first layer. The production of the profile also includes: removing the masking patterns, removing the buffer patterns revealing walls previously covered by the buffer patterns, and then an isotropic etching to remove the walls.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: December 27, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Michel Heitzmann
  • Patent number: 9472417
    Abstract: Methods of selectively etching metal-containing materials from the surface of a substrate are described. The etch selectively removes metal-containing materials relative to silicon-containing films such as silicon, polysilicon, silicon oxide, silicon germanium, silicon carbide, silicon carbon nitride and/or silicon nitride. The methods include exposing metal-containing materials to halogen containing species in a substrate processing region. No plasma excites the halogen-containing precursor either remotely or locally in embodiments.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: October 18, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Nitin K. Ingle, Jessica Sevanne Kachian, Lin Xu, Soonam Park, Xikun Wang, Jeffrey W. Anthis
  • Patent number: 9448468
    Abstract: A reflective mask blank, a reflective mask, and methods for manufacturing those, which suppress reflectance at a light-shielding frame. The reflective mask includes a substrate, a multilayered reflective layer formed on the substrate, an absorption layer formed on the multilayered reflective layer, and a frame-shaped light-shielding frame area at which the absorption layer has a film thickness larger than a film thickness at other areas. The multilayered reflective layer is diffused and mixed at the light-shielding frame area through melting.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 20, 2016
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Masahito Tanabe, Norihito Fukugami, Yo Sakata, Tooru Komizo, Takashi Haraguchi
  • Patent number: 9437562
    Abstract: A manufacturing method of a semiconductor device includes placing a mask having an opening on an external region of a top face of a substrate to locate an end portion of the opening of the mask just above a concave portion formed on the top face of the substrate, the external region being located outside the concave portion. The manufacturing method further includes: growing a conductive film on part of the top face of the substrate through the mask after the mask is placed on the substrate, the part of the top face containing the concave portion; and removing the mask from the substrate after the conductive film is grown.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: September 6, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takashi Ushijima, Atsushi Imai, Jiro Nohara
  • Patent number: 9436092
    Abstract: Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: September 6, 2016
    Assignee: Newport Fab, LLC
    Inventors: George Talor, Edward Preisler, David J. Howard
  • Patent number: 9390935
    Abstract: Provided is an etching method for forming a space with an aspect ratio of 50 or more in a workpiece including a silicon oxide film and a hard mask. The etching method includes: a first step of exposing the workpiece to plasma of a fluorocarbon-based gas within a processing container of a capacitively coupled plasma processing apparatus which includes a placing table serving as a lower electrode and an upper electrode; and a second step of further exposing the workpiece to the plasma of a fluorocarbon-based gas within a processing container of a capacitively coupled plasma processing apparatus which includes a placing table serving as a lower electrode and an upper electrode. A distance between the placing table and the upper electrode in the first step is at least 5/3 times of a distance between the placing table and the upper electrode in the first step.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 12, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Maju Tomura, Hikaru Watanabe, Fumiya Kobayashi, Kazuhiro Kubota, Masanobu Honda
  • Patent number: 9321074
    Abstract: A mask frame assembly for thin film deposition including a frame having an opening portion and a support portion, and a mask having a deposition area in a position corresponding to the opening portion, wherein the mask includes a first layer including the deposition area and a peripheral portion disposed outside the deposition area and a second layer including a first surface and a second surface opposite to the first surface, at least a part of the first surface of the second layer faces the first layer and contacts the peripheral portion, and the second surface is welded to the support portion of the frame.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jung-Woo Ko, Sang-Shin Lee, Taek-Kyo Kang, Seung-Ju Hong
  • Patent number: 9059019
    Abstract: A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Junli Wang, Yunpeng Yin
  • Publication number: 20150144588
    Abstract: A method to control thermal energy transport uses mobile coherent interfaces in nanoscale ferroelectric films to scatter phonons. The thermal conductivity can be actively tuned, simply by applying an electrical potential across the ferroelectric material and thereby altering the density of these coherent boundaries to directly impact thermal transport at room temperature and above. The invention eliminates the necessity of using moving components or poor efficiency methods to control heat transfer, enabling a means of thermal energy control at the micro- and nano-scales.
    Type: Application
    Filed: November 18, 2014
    Publication date: May 28, 2015
    Inventors: Jon Ihlefeld, Patrick Edward Hopkins
  • Patent number: 9040428
    Abstract: Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface includes peaks of pillars which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Augustin J. Hong, Woo-Shik Jung, Jeehwan Kim, Jae-Woong Nahum, Devendra K. Sadana
  • Patent number: 9031684
    Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Han Cheng, Chin-Hsiang Lin, Chi-Ming Yang, Chun-Lin Chang, Chih-Hong Hwang
  • Patent number: 9000455
    Abstract: A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly.
    Type: Grant
    Filed: March 10, 2013
    Date of Patent: April 7, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Ming-Shing Lee, Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Chang Chen, Ming-Hua Lo, Chu-Ching Tsai
  • Publication number: 20150085974
    Abstract: An X-ray mask structure includes a unibody support substrate having at least one thinned portion surrounded by a wall portion, a top layer disposed on the at least one thinned portion of the support substrate, and a plurality of X-ray absorber patterns disposed on the top layer over the at least one thinned portion. The top layer and the at least one thinned portion form a laminated membrane, wherein the at least one thinned portion and the wall portion provide mechanical support for the top layer, and the laminated membrane provides mechanical support for the plurality of X-ray absorber patterns.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 26, 2015
    Applicant: NATIONAL SYNCHROTRON RADIATION RESEARCH CENTER
    Inventor: Bor Yuan SHEW
  • Patent number: 8980108
    Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Yu, Ting-Hao Hsu, Chia-Ching Huang
  • Publication number: 20150069010
    Abstract: A patterning method includes steps of forming a first copolymer layer comprising a first diblock copolymer which has portions which are phase incompatible. The first copolymer layer is annealed to form a first phase pattern including a first phase dispersed in a second surrounding phase. The first copolymer is then etched forming a first topographic pattern that corresponds to the first phase pattern. A second copolymer layer of a second diblock copolymer is then formed over the first topographic pattern, and then annealed to generate a second phase pattern offset from the first topographic pattern. Etching is used to form a second topographic pattern corresponding to the second phase pattern. The first and second topographic patterns are then transferred to the substrate. The patterning method can be used, for example, to form patterned recording layers for magnetic storage devices.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira WATANABE, Katsuya SUGAWARA, Kazutaka TAKIZAWA, Kaori KIMURA
  • Publication number: 20150059643
    Abstract: A new type of fine metal mask (FMM) used in OLED production and the method of manufacturing it, wherein the FMM includes a frame made of a metal substrate with a plurality of through holes, a layer of fine mask electroformed on the surface of the frame so that said fine mask and said frame are seamlessly integrated, said fine mask is divided into a pattern area and a border area, and the pattern area corresponds to the through holes on the frame, and the method of manufacturing such an FMM comprising the steps of: A. providing a metal substrate by cutting an invar alloy or stainless steel plate to a desired size; B. providing an fine mask by adding a photoresist layer on the metal substrate, exposing a desired pattern onto said photoresist layer, and electroforming a metal base layer and a metal layer with a low thermal expansion coefficient; and C.
    Type: Application
    Filed: February 20, 2014
    Publication date: March 5, 2015
    Inventors: Weichong Du, Jianwei Han, Wenhui Mei
  • Publication number: 20150040826
    Abstract: A method for manufacturing a metal mask includes defining pattern areas exposing an upper surface, and a lower surface opposite to the upper surface, of a thin plate; and etching the upper and lower surfaces of the thin film plate exposed by the pattern areas, to reduce a thickness of the thin film plate by a predetermined thickness and form deposition openings in the metal mask. The etching the upper and lower surfaces of the thin film plate includes both a wet-etching method and a dry-etching method.
    Type: Application
    Filed: April 9, 2014
    Publication date: February 12, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Sung-Woo JUNG, Sang-Yun LEE, Yong-Hwan KIM
  • Patent number: 8927180
    Abstract: A method of manufacturing a mask may include forming initial ribs and removing edge portions of the initial ribs to form final ribs, each of which has a top width smaller than that of the initial rib. A space between the initial ribs may be smaller than a width of a slit limited by the final ribs.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Valeriy Prushinskiy, Wonsik Hyun, HeungYeol Na, Minsoo Kim, YoungShin Pyo, JaeMin Hong
  • Publication number: 20140377903
    Abstract: A method for producing a vapor deposition mask capable of satisfying both enhancement in definition and reduction in weight even when a size is increased, and a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition are provided. A vapor deposition mask is produced by the steps of preparing a metal plate with a resin layer in which a resin layer is provided on one surface of a metal plate, forming a metal mask with a resin layer by forming a slit that penetrates through only the metal plate, for the metal plate in the metal plate with a resin layer, and thereafter, forming a resin mask by forming openings corresponding to a pattern to be produced by vapor deposition in a plurality of rows lengthwise and crosswise in the resin layer by emitting a laser from the metal mask side.
    Type: Application
    Filed: January 11, 2013
    Publication date: December 25, 2014
    Inventors: Toshihiko Takeda, Hiroyuki Nishimura, Katsunari Obata
  • Publication number: 20140367356
    Abstract: In some examples, a process to generate an in-situ hardmask layer on porous dielectric materials using the densifying action of a plasma in conjunction with a sacrificial polymeric filler, the latter which enables control of the hardmask thickness as well as a well-defined interface with the underlying ILD.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventors: Geraud Jean-Michel Dubois, Theo J. Frot, Teddie P. Magbitang, Willi Volksen
  • Publication number: 20140356769
    Abstract: A method of manufacturing a mask, the method including forming initial ribs such that forming the initial ribs includes forming at least two photoresist patterns such that the at least two photoresist patterns have different widths, are formed on at least one side of a mask substrate, and overlap each other, and performing an etching process at least two times; and forming final ribs such that the final ribs have curved sides having a different curvature radius than a curvature radius of initial curved sides of the initial ribs and have defined slit patterns, forming the final ribs including removing all but one of the at least two photoresist patterns, and performing an etching process.
    Type: Application
    Filed: April 24, 2014
    Publication date: December 4, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Valeriy PRUSHINSKIY, Minsoo KIM
  • Publication number: 20140291306
    Abstract: A mask substrate that includes a first area and a second area surrounding the first area is provided. Then, a laser beam is irradiated on the mask substrate to at least partly remove a material of the second area. After that, a physical force is applied to the mask substrate to separate the first area from the mask substrate thereby forming an opening through the mask substrate.
    Type: Application
    Filed: September 9, 2013
    Publication date: October 2, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Doh-Hyoung LEE, Jun Ho JO
  • Publication number: 20140290574
    Abstract: A method of manufacturing a fine metal mask is provided. The method of manufacturing a fine metal mask includes: forming a first recessed portion in a first surface of a base member; forming an edge portion of the first recessed portion in a uniform depth; forming a second recessed portion in a second surface of the base member, the second surface being opposite to the first surface; and communicating the first recessed portion and the second recessed portion of the base member. A fine metal mask produced by the inventive method is also described and may be used to fabricate OLEDs having better resolution and an increased aperture ratio in comparison with OLEDs prepared using the fine metal masks of the conventional art.
    Type: Application
    Filed: October 16, 2013
    Publication date: October 2, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jung-Hoon KIM
  • Patent number: 8845908
    Abstract: A method of mitigating asymmetric lens heating in photolithographically patterning a photo-imagable material using a reticle includes determining where first hot spot locations are expected to occur on a lens when using a reticle to pattern a photo-imagable material. The reticle is then fabricated to include non-printing features within a non-printing region of the reticle which generate additional hot spot locations on the lens when using the reticle to pattern the photo-imagable material. Other implementations are contemplated, including reticles which may be independent of method of use or fabrication.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Scott L. Light, Dan Millward, Yuan He, Kaveri Jain, Lijing Gou, Zishu Zhang, Anton deVilliers, Michael Hyatt, Jianming Zhou
  • Publication number: 20140283742
    Abstract: A deposition mask assembly having a plurality of deposition masks consecutively arranged in parallel is discussed. The deposition mask has a frame coupled with the plurality of deposition masks, wherein cross section of one end of each deposition mask having first and second sectors which are asymmetric and meet each other at a first contact point, wherein the first sector has a first radius and a first center angle, and connected to an upper surface of the deposition mask, the second sector has a second radius different from the first radius and a second center angle different from the first center angle, and connected to a lower surface of the deposition mask, and the contact point is asymmetric, pointed and protruded horn-shaped or arrow-shaped.
    Type: Application
    Filed: June 4, 2014
    Publication date: September 25, 2014
    Inventors: Chong-Hyun PARK, Tae-Hyung KIM, Il-Hyun LEE
  • Publication number: 20140263164
    Abstract: Polymer films comprising crosslinked random copolymers and methods for making the films are provided. Also provided are polymer films comprising random copolymers that are covalently linked to an underlying substrate. The polymer films can be incorporated into structures in which the films are employed as surface-modifying layers for domain-forming block copolymers and the structures can be used for pattern transfer applications via block copolymer lithography. The crosslinks between the random copolymer chains in the polymer films or the links between the random copolymer chains and the substrate surface are characterized in that they can be cleaved under relatively mild conditions.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Wisconsin Alumni Research Foundation
    Inventor: Wisconsin Alumni Research Foundation