Forming Or Treating Mask Used For Its Nonetching Function (e.g., Shadow Mask, X-ray Mask, Etc.) Patents (Class 216/12)
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Publication number: 20080261129Abstract: A selective surface treatment method using a block copolymer, a black matrix and a method of manufacturing the same, and a nozzle plate and a method of manufacturing the same are provided. According to the selective surface treatment method, a block copolymer layer including a hydrophilic polymer block and a hydrophobic polymer block is formed on a predetermined surface of a substrate.Type: ApplicationFiled: October 23, 2007Publication date: October 23, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Tae-woon Cha, Wou-sik Kim, Seong-jin Kim
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Publication number: 20080230511Abstract: In one embodiment of the present invention, a halogen-free plasma etch processes is used to define a feature in a multi-layered masking stack including an amorphous carbon layer. In a particular embodiment, oxygen (O2), nitrogen (N2), and carbon monoxide (CO) are utilized to etch the amorphous carbon layer to form a mask capable of producing sub-100 nm features in a substrate film having a reduced line edge roughness value. In another embodiment, the present invention employs an O2 plasma pretreatment preceding the halogen-free amorphous carbon etch to first form an oxidized silicon region in a patterned photoresist layer to increase the selectivity of the amorphous carbon etch relative to a patterned photoresist layer containing unoxidized silicon.Type: ApplicationFiled: March 21, 2007Publication date: September 25, 2008Inventors: Jong Mun Kim, Judy Wang, Ajey M. Joshi, Jingbao Liu, Bryan Y. Pu
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Patent number: 7425275Abstract: A method of fabricating a vertically tapered structure. The method includes placing a spacer layer at a predetermined area on a wafer, placing a mask layer at a predetermined area on the spacer layer, and over-etching the spacer layer, by etching a certain area below the mask layer, fabricating a cantilever type shadow mask having the spacer layer and the mask layer. Thus, it is possible to fabricate the vertically tapered structure of several tens of microns. The vertically tapered structure can be used as the optical waveguide in the optical device to minimize junction loss that may occur between the optical waveguide and the optical fiber.Type: GrantFiled: August 15, 2005Date of Patent: September 16, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Duk-yong Choi
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Publication number: 20080203053Abstract: A reliable magnetic recording medium manufacturing method is provided in which a resin material used for processing a recording layer into a concavo-convex pattern can be removed reliably. In the magnetic recording medium manufacturing method, an energy ray curable resin material is spread over a continuous recording layer. Then, a stamper having a predetermined concavo-convex pattern is brought into contact with the resin material to transfer the concavo-convex pattern to the resin material, and the resin material is irradiated with energy rays such that the irradiation energy on a portion excluding the edge portion of the resin material is greater than that on the edge portions. The curing reaction proceeds to a greater extent in the portion excluding the edge portions than in the edge portions. Then, the resin material is etched and removed such that more resin material is removed from the edge portions than from the other portion.Type: ApplicationFiled: February 21, 2008Publication date: August 28, 2008Applicant: TDK CORPORATIONInventors: Narutoshi Fukuzawa, Kazuhiro Hattori, Minoru Fujita, Daisuke Yoshitoku
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Publication number: 20080197107Abstract: A method of fabricating a grayscale mask includes preparing a quartz wafer; depositing a layer of Si3N4 on the quartz wafer; depositing a layer of titanium/TEOS directly on the Si3N4 layer on the backside of the quartz wafer; removing the layer of Si3N4 from the front side of the quartz wafer; depositing a layer of SRO directly on the front side of the quartz wafer; patterning a microlens array on the SRO layer; etching the SRO layer to form a microlens array in the SRO layer; depositing a layer of titanium; patterning and etching the titanium layer; depositing a layer of SiOxNy on the SRO microlens array; CMP to planarize the layer of SiOxNy removing the titanium/TEOS layer from the backside of the quartz wafer; bonding the planarized SiOxNy to a quartz reticle plate; and etching to remove Si3N4 from the bonded structure to form a grayscale mask reticle.Type: ApplicationFiled: February 20, 2007Publication date: August 21, 2008Inventors: Wei Gao, Bruce D. Ulrich, Yoshi Ono
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Patent number: 7407890Abstract: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.Type: GrantFiled: April 21, 2006Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventor: Haining S. Yang
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Patent number: 7393457Abstract: The present invention is to provide a method for making a shadow mask for an opposed discharge plasma display panel by etching one lateral surface of a metal slab to produce a plurality of parallel and equidistant barrier ribs along the vertical and horizontal directions on the lateral surface and a discharging cell by enclosing every four adjacent barrier ribs. A shadow hole is formed at the middle of each discharging cell and etched through the metal slab, and at least one groove interconnected to the shadow holes is produced on another lateral surface of the metal slab by utilizing a rolling process or a stamping process. The adjacent grooves are interconnected with each other, and a plurality of air guide channels is formed on another lateral side, such that a shadow mask can be made in a simple and fast manner, chemical pollutions caused by a traditional double-sided etching can be minimized, and the product yield rate and the manufacturing cost can be effectively improved and lowered.Type: GrantFiled: September 15, 2006Date of Patent: July 1, 2008Assignee: Marketech International CorporationInventors: Hsu-Pin Kao, Jang-Jeng Liang, Sheng-Wen Hsu, Hsu-Chia Kao
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Publication number: 20080099426Abstract: A method and apparatus for etching photomasks are provided herein. The apparatus includes a process chamber with a shield above a substrate support. The shield comprises a plate with apertures, and the plate has two zones with at least one characteristic, such as material or potential bias, that is different from each other. The method provides for etching a photomask substrate with a distribution of ions and neutral species that pass through the shield.Type: ApplicationFiled: October 30, 2006Publication date: May 1, 2008Inventors: Ajay Kumar, Madhavi R. Chandrachood, Richard Lewington, Darin Bivens, Amitabh Sabharwal, Sheeba J. Panayil, Alan Hiroshi Ouye
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Publication number: 20080088221Abstract: A shadow mask, a method of manufacturing the shadow mask, and a method of forming a thin film using the shadow mask are provided. The shadow mask includes an upper layer and a lower layer. The upper layer includes a first opening. The lower layer is formed on a lower surface of the upper layer around the first opening and includes an opening having the same size as the first opening. When the thin film is formed using the shadow mask, the lower layer of the shadow mask is close to the edge of a cavity of a substrate, and a position on which the thin film may be formed as defined by the lower layer of the shadow mask. Therefore, the thickness of the thin film can be uniform.Type: ApplicationFiled: March 29, 2007Publication date: April 17, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-whan Chung, Seok-jin Kang, Hyun-koo Jeong
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Publication number: 20080070128Abstract: Embodiments of methods of etching EUV photomasks are provided herein. In one embodiment, a method of etching an extreme ultraviolet photomask includes providing a photomask comprising, in order, a substrate, a multi-material layer, a capping layer, and a multi-layer absorber layer, the multilayer absorber layer comprising a self-mask layer disposed over a bulk absorber layer, wherein the self-mask layer comprises tantalum and oxygen and the bulk absorber layer comprises tantalum and essentially no oxygen; etching the self-mask layer using a first etch process; and etching the bulk absorber layer using a second etch process different than the first, wherein the etch rate of the bulk absorber layer is greater than the etch rate of the self-mask layer during the second etch process.Type: ApplicationFiled: September 15, 2006Publication date: March 20, 2008Applicant: Applied Materials, Inc.Inventors: Banqiu Wu, Madhavi R. Chandrachood, Ajay Kumar
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Patent number: 7344908Abstract: The present invention relates to an AFM (atomic force microscope) cantilever including a field effect transistor (FET) and a method for manufacturing the same; and, more particularly, to a method for manufacturing an AFM cantilever including an FET formed by a photolithography process, wherein an effective channel length of the FET is a nano-scale. Therefore, The present invention can easily implement a simulation for manufacturing the AFM cantilever including the FET by accurately controlling the effective channel length. And also, the present invention can manufacture the AFM cantilever including the FET having the effective channel ranging several tens to several hundreds nanometers by applying the low price photolithography device, thereby enhancing an accuracy and yield of the manufacturing process and drastically reducing process costs.Type: GrantFiled: December 21, 2006Date of Patent: March 18, 2008Assignee: Korea Electronics Technology InstituteInventors: Moon Suhk Suh, Jin-Koog Shin, Churl Seung Lee, Kyoung IL Lee
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Patent number: 7338609Abstract: A method to provide a ground point for second, or subsequent, e-beam mask-writing steps by selectively removing the photoresist edge bead of a photomask substrate to expose the underlying chrome layer. The selective removal leaves at least one tab of photoresist edge bead over the chrome layer. After the first e-beam mask writing step and subsequent etch, the tab can be removed to expose a portion of the chromium layer that can act as a new ground point for a second e-beam etch. Also, a nozzle for use in selectively removing the edge bead to leave a tab of photoresist edge bead.Type: GrantFiled: January 17, 2006Date of Patent: March 4, 2008Assignee: Micron Technology, Inc.Inventor: J. Brett Rolfson
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Patent number: 7338736Abstract: A phase shift mask includes a first non-phase shift region, a first phase shift region adjacent the first non-phase shift region, a second non-phase shift region, a second phase shift region adjacent the second non-phase shift region, and an opaque region interposed between said second phase shift and non-phase shift regions. The first and second non-phase shift regions transmit an exposure light at its original phase, whereas the first and second phase shift regions invert the phase of the exposure light. The phase shift mask is manufactured by first forming a layer of opaque material on a transparent mask substrate. The first phase shift region and the second phase and non-phase shift regions are formed by selectively etching the opaque material and underlying portions of the mask substrate to form recesses in the substrate.Type: GrantFiled: June 3, 2004Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Myung-Ah Kang, In-Kyun Shin
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Patent number: 7332098Abstract: The present invention provides a phase shift mask and fabricating method thereof, by which a critical dimension of a semiconductor pattern can be accurately formed in a manner of compensating a boundary step difference between an active area and an insulating layer. The present invention includes a transparent substrate and at least two halftone layers on the transparent substrate to have light transmittance lower than that of the transparent substrate, each comprising front and rear parts differing in thickness from each other.Type: GrantFiled: December 30, 2004Date of Patent: February 19, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Jun Seok Lee
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Publication number: 20080006602Abstract: An exemplary coating apparatus (40) for fabricating a color filter (3) includes a supporting table (44) and a dispenser (48). The supporting table supports a substrate (30) that serves as a foundation of the color filter. The dispenser includes plural first nozzles (412) for spraying a first color photo-resist onto the substrate, plural second nozzles (422) for spraying a second color photo-resist onto the substrate, and plural third nozzles (432) for spraying a third color photo-resist onto the substrate. The first, second and third nozzles simultaneously spray the first, second and third color photo-resists onto respective different locations on the substrate. Therefore three corresponding color resins can be formed on the substrate in a single coating step. Thus, a cost of fabricating the color filter is reduced.Type: ApplicationFiled: July 9, 2007Publication date: January 10, 2008Inventor: Chun-Pin Huang
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Patent number: 7309652Abstract: Disclosed are a method for removing a photoresist layer and a method for forming a metal line using the same. The method for removing a photoresist pattern, including the steps of: forming a bottom layer on a substrate by using the photoresist pattern as a mask; and removing the photoresist pattern with use of a high density plasma (HDP) apparatus. The method for forming a metal line, including the steps of: preparing a semi-finished substrate including an inter-layer insulation layer; forming a photoresist pattern on the inter-layer insulation layer; forming an opening by etching the inter-layer insulation layer with use of the photoresist pattern as an etch mask; removing the photoresist pattern by using a high density plasma (HDP) apparatus; and forming the metal line by filling the opening with a predetermined material.Type: GrantFiled: June 6, 2005Date of Patent: December 18, 2007Assignee: MagnaChip Semiconductor, Ltd.Inventor: Sang-Wook Ryu
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Patent number: 7306742Abstract: A template 1 is brought close to or in contact with a surface to be patterned 111 and patterns are formed with liquid 62 on the surface 111. This method comprises the steps of: bringing the template 1 close to or essentially in contact with the surface 111, supplying liquid 62 to a plurality of through holes 12 established in the pattern transfer region 10 of the template 1 for supplying the liquid 62, and separating the template 1 from the surface 111 after the liquid 62 is adhered to the surface 111 via the through holes 12.Type: GrantFiled: April 29, 2003Date of Patent: December 11, 2007Assignee: Seiko Epson CorporationInventors: Satoshi Nebashi, Takao Nishikawa, Tatsuya Shimoda
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Patent number: 7287468Abstract: A structure and associated methods of formation. The structure includes a layered configuration comprising a copper layer, a first layer, and a second layer. The copper layer consists essentially of copper. The first and second layers are disposed on opposite sides of the copper layer and are in direct mechanical contact with the copper layer. The first and second layers each consist essentially of a same alloy of nickel and cobalt having a weight percent concentration of cobalt in a range of 3% to 21%. A through hole in the layered configuration extends completely through the first layer, the copper layer, and the second layer, wherein a first opening in the layered configuration extends completely through the first layer and does not extend into any portion of the second layer.Type: GrantFiled: May 31, 2005Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Harry David Cox, Hsichang Liu, Nike Oluwakemi Medahunsi, Krystyna Waleria Semkow
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Patent number: 7185419Abstract: A mask frame assembly for evaporation includes a mask and a frame which supports the mask. The mask includes a metal layer having a predetermined pattern, and a coating layer which is formed on a surface of the metal layer so as to increase a precision of the predetermined pattern and a surface roughness of the mask.Type: GrantFiled: May 30, 2003Date of Patent: March 6, 2007Assignee: Samsung SDI Co., Ltd.Inventors: Chang Ho Kang, Tae Seung Kim
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Patent number: 7115193Abstract: Provided is a sputtering target, backing plate or apparatus inside a sputtering device in which an electrical discharge machining mark is formed on the face to which unwanted films during sputtering are deposited, and the electrical discharge machining mark is formed from numerous inclined protrusions having a depression angle of less than 90°. When necessary, chemical etching is further performed to the portions subject to such electrical discharge machining. Thereby, the separation and flying of deposits arising from the face to which unwanted films of the target, backing plate and apparatus inside the sputtering device are deposited can be prevented.Type: GrantFiled: December 19, 2001Date of Patent: October 3, 2006Assignee: Nippon Mining & Metals Co., Ltd.Inventor: Hideyuki Takahashi
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Patent number: 7115207Abstract: Disclosed is a method of manufacturing a metal mask for an integrated circuit chip interconnect solder bump. The invention deposits a very thick photoresist on both sides of a very thick molybdenum foil sheet (the molybdenum sheet is at least 8 mils thick and the photoresist is at least 5 microns thick). Then the process exposes and develops the photoresist to produce at least one opening having a diameter of at least 5 mil. The invention simultaneously etches both sides of the molybdenum foil using a very low etchant spray pressure of approximately 5 psi to form at least one via in the molybdenum foil that has a diameter of at least 12 mil and a knife-edge of 0.2 mil. The photoresist is removed after the etching process.Type: GrantFiled: July 1, 2003Date of Patent: October 3, 2006Assignee: International Businss Machines CorporationInventors: Peter H. Berasi, Michael F. Jerome, Doris P. Pulaski, Robert P. Rippstein
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Patent number: 7056624Abstract: Methods of manufacturing a single sided engraving phase shift mask that includes a shifter part and a non-shifter part mutually adjacent on a substrate, and a shading layer pattern formed with a shading film and wherein a side wall part of a dug-down part has round, crooked portions at top and bottom corners of the sidewall part. The method includes forming a resist pattern having a selective opening at the shifter part, forming a dug-down part corresponding to the shifter part by using the resist pattern, wet etching the whole surface at the dug-down part forming side of the substrate, forming a shading film on the substrate, forming a resist pattern on the shading film, and forming a shading pattern having prescribed openings at the shifter part and non-shifter part.Type: GrantFiled: February 15, 2002Date of Patent: June 6, 2006Assignee: Dai Nippon Printing Co., Ltd.Inventor: Haruo Kokubo
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Patent number: 7047094Abstract: A computer implemented method for LSI mask manufacturing stores performance information of a lithography unit, connected to a network, in a lithography unit database. The method receives a lithography data and a lithography reservation condition from a user terminal connected to the network. The method stores the lithography data in a lithography data database. The method searches for a lithography unit matching to the lithography reservation condition, generating a list of lithography units, and sending the list to the user terminal. In addition, the method receives information of a lithography unit specified by the user terminal and sending a lithography request to the lithography unit specified by the user terminal.Type: GrantFiled: March 26, 2003Date of Patent: May 16, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Kiyomi Koyama
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Patent number: 7033665Abstract: A precision mask for deposition is provided that includes a first brace having a plurlaity of sections placed in parallel to each other at given intervals. The first brace forms portions that define a plurality of first openings. The precision mask for deposition also includes at least one second brace that is placed on the first brace so as to intersect with the first brace. The second brace forms portions that define a plurality of second openings. The second brace is joined to the first brace at a point where the second brace intersects with the first brace.Type: GrantFiled: January 20, 2004Date of Patent: April 25, 2006Assignee: Seiko Epson CorporationInventors: Shinichi Yotsuya, Takayuki Kuwahara
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Patent number: 7033708Abstract: A focus monitor on an alternating phase shift mask may include sub-wavelength features which have a depth corresponding to an etch depth of primary features on the mask (e.g., a 180° etch depth), but which produce an effective phase shift of about 60° to 120°.Type: GrantFiled: May 20, 2003Date of Patent: April 25, 2006Assignee: Intel CorporationInventor: Edita Tejnil
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Patent number: 7025891Abstract: A method of treating a molybdenum (moly) mask used in a C4 process to pattern C4 contacts. The moly mask has a wafer side which contacts a wafer during the C4 process and has a rough surface that includes spikes/projections of moly. The moly mask also has a non wafer side and a plurality of holes extending through the mask to pattern C4 contacts in the C4 process. An adhesive layer, such as an adhesive tape, is applied to the non wafer side of the moly mask, to enable a polishing tool to pull a vacuum on the non wafer side of the moly mask in spite of the presence of the holes to secure the moly mask during a subsequent polishing step. The tape also functions as a cushion so that defects on the non wafer side of the moly mask do not replicate through the moly mask to the polished wafer side of the moly mask.Type: GrantFiled: August 29, 2003Date of Patent: April 11, 2006Assignee: International Business Machines CorporationInventors: Steven R. Codding, Timothy C. Krywanczyk, Joseph D. Danaher, John C. Malinowski, James R. Palmer, Melvin T. Kelly, Caitlin W. Weinstein, Wolfgang Sauter
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Patent number: 7018747Abstract: A photomask and a method for making the same in which an opaque feature (38) is formed on a transparent substrate (32) and a depression (44) is etched in the transparent substrate (32) adjacent to the opaque feature (38). The depression (44) is etched to a depth such that a phase difference between light passing through the substrate (32) outside the depression (44) and light passing through the depression is 180°. In one embodiment, the depression (44) is formed in the substrate directly adjacent to an edge of the opaque feature (38). In another embodiment, the depression (58) surrounds a mesa structure (59) formed in the substrate (50), and the opaque feature (62) resides on the mesa structure (59). The depression (58) may be laterally spaced from an edge of the opaque feature (62).Type: GrantFiled: October 1, 2002Date of Patent: March 28, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Wei E. Wu, Bernard J. Roman
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Patent number: 6986850Abstract: A method to provide a ground point for second, or subsequent, e-beam mask-writing steps by selectively removing the photoresist edge bead of a photomask substrate to expose the underlying chrome layer. The selective removal leaves at least one tab of photoresist edge bead over the chrome layer. After the first e-beam mask writing step and subsequent etch, the tab can be removed to expose a portion of the chromium layer that can act as a new ground point for a second e-beam etch. Also, a nozzle for use in selectively removing the edge bead to leave a tab of photoresist edge bead.Type: GrantFiled: July 7, 2003Date of Patent: January 17, 2006Assignee: Micron Technology, Inc.Inventor: J. Brett Rolfson
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Patent number: 6955726Abstract: A mask frame assembly includes a frame having an opening and a mask having at least two unit mask elements. Both ends of each unit mask element are fixed to the frame in a state of tension. The unit mask elements include a unit masking pattern, and overlap each other on a predetermined width to form a single mask pattern block. Each unit mask element has a recessed wall in an overlapping portion thereof so as to maintain the thickness of the mask constant at an overlap between the unit mask elements. Accordingly, the mask frame assembly reduces distortion in an evaporation pattern due to an increase in the size of a mask pattern, facilitates the adjustment of a total pitch of evaporation patterns, and prevents evaporation from occurring at undesired positions.Type: GrantFiled: June 3, 2003Date of Patent: October 18, 2005Assignee: Samsung SDI Co., Ltd.Inventors: Chang Ho Kang, Tae Seung Kim
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Patent number: 6926840Abstract: A method of mounting a deposition mask onto a flexible frame for use in vacuum deposition of material through a pealable deposition mask in forming an OLED, including the steps of providing a plate with the pealable deposition mask formed thereon; providing the flexible frame having border portions, such border portions defining a frame opening which corresponds to border portions on the pealable deposition mask; aligning and then securing the border portions of the flexible frame to the border portions of the pealable deposition mask and removing the flexible frame and secured pealable deposition mask from the plate; and mounting the flexible frame with the pealable deposition mask in a carrier which maintains planarity of the pealable deposition mask during subsequent vacuum deposition of material.Type: GrantFiled: December 31, 2002Date of Patent: August 9, 2005Assignee: Eastman Kodak CompanyInventor: Thomas K. Clark
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Patent number: 6922010Abstract: The present invention provides a shadow mask having an improved resistance to an impact such as vibration or dropping so as to keep a constant quality of a color cathode-ray tube.Type: GrantFiled: September 26, 2001Date of Patent: July 26, 2005Assignee: Dai Nippon Printing Co., Ltd.Inventors: Takayasu Komatsu, Hirofumi Hideshima, Akira Makita, Yutaka Matsumoto, Takuya Ogio
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Patent number: 6919147Abstract: The present invention provides a production method for a halftone phase mask which has an SiO2 substrate, an overlying refractory metal SixNy phase shifter layer (2) and an overlying chromium oxide or chromium mask layer (3), having the following steps: provision of a mask (4) on the chromium oxide or chromium mask layer (3); etching of the chromium oxide or chromium mask layer (3) for the purpose of forming a hard mask from the chromium oxide or chromium mask layer (3) in a first etching step; selective etching of the refractory metal SixNy phase shifter layer (2) using the hard mask in a plasma with a chlorine-containing and/or hydrogen-chloride-containing main gas in a second etching step with a predetermined cathode power of at least 20 W.Type: GrantFiled: September 25, 2002Date of Patent: July 19, 2005Assignee: Infineon Technologies AGInventors: Josef Mathuni, Gunther Ruhl
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Patent number: 6893976Abstract: A method of producing a shadow mask having a set of apertures (the set of apertures including a given aperture with an aperture boundary) uses a wafer having at least a first silicon layer, a second silicon layer, and an insulator layer between the first and second silicon layers. A first portion of the first silicon layer within the aperture boundary is removed. This produces a second portion of the first silicon layer, which remains within the aperture boundary. The second silicon layer within the aperture boundary is removed, as well as the insulator layer within the aperture boundary. The second portion of the first silicon layer remaining within the aperture boundary then is removed.Type: GrantFiled: September 5, 2002Date of Patent: May 17, 2005Assignee: Analog Devices, Inc.Inventors: Maurice S. Karpman, Swaminathan Rajaraman
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Patent number: 6893575Abstract: A mask has a monocrystal substrate having opposite surfaces which are planes having Miller indices {110}. A plurality of penetrating holes are formed in the monocrystal substrate. An opening shape of each of the penetrating holes is a polygon and each side of the polygon is parallel with a plane in a group of the {111} planes. The wall surfaces of the penetrating holes are the {111} planes. In the method of manufacturing a mask, openings are formed in the etching resistant film corresponding to the shape of the penetrating holes and the monocrystal substrate is etched.Type: GrantFiled: September 19, 2002Date of Patent: May 17, 2005Assignee: Seiko Epson CorporationInventor: Shinichi Yotsuya
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Patent number: 6890447Abstract: A sacrificial film is formed on a substrate and a mask layer is formed on the sacrificial film. An opening having a predetermined pattern is formed through the mask layer. The sacrificial film exposed in the opening is removed to form a cave broader than the opening on the substrate. A noble metal thin film is deposited on the whole substrate surface. The sacrificial film 12 is dissolved and removed to form a noble metal thin film pattern.Type: GrantFiled: August 1, 2002Date of Patent: May 10, 2005Assignee: Yamaha CorporationInventors: Kiyoshi Natsume, Hiroshi Naito
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Patent number: 6875547Abstract: A method of crystallizing amorphous silicon using a mask having a transmitting portion including a plurality of stripes, wherein end lines of at least two stripes are not collinear; and a blocking portion enclosing the plurality of stripes includes the steps of setting the mask over a substrate having an amorphous silicon layer, applying a first laser beam to a first area of the amorphous silicon layer through the mask, thereby forming a first crystallization region, moving the substrate in a first direction, thereby disposing the blocking portion of the mask over the first crystallization region, and applying a second laser beam to the first area of the amorphous silicon layer through the mask, thereby forming a second crystallization region.Type: GrantFiled: April 22, 2003Date of Patent: April 5, 2005Assignee: LG. Philips LCD Co., Ltd.Inventor: Sang-Hyun Kim
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Patent number: 6800214Abstract: A method for correcting characteristics of an attenuated phase-shift mask having an attenuated layer including (a) storing a data in a memory, which shows a correlation between characteristics and process conditions, (b) measuring the characteristics of the attenuated phase-shift mask, (c) calculating a appropriate process condition from the result of the step (b) and the data stored in the memory; and (d) soaking the attenuated phase-shift mask into a liquid solution for a certain time-that is calculated in the step (c) to change thickness and composition of the attenuated layer.Type: GrantFiled: November 21, 2002Date of Patent: October 5, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Katsuhiro Takushima
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Patent number: 6793778Abstract: A method for fabricating a transducer with landing pads without edge fences is described. Preferably an adhesion layer and then the pad layer are deposited in voids in a photoresist. The thickness of the masking layer on the surface of the pad layer should be sufficient to protect pad layer during the subsequent ashing step, but the thickness of the masking material at the sidewalls on the pad layer fences should be thin enough so that the fences are not protected during ashing. After stripping the photoresist material, the structure is ashed preferably by an oxygen-containing plasma. The ashing process, with assistance from mechanical abrasion, removes the fence structures on the pad layer, since the thinner masking layer at the sidewalls provides less protection to the fence structures than is provided to the bulk of the pad layer where the masking layer is thicker.Type: GrantFiled: July 15, 2002Date of Patent: September 21, 2004Assignee: Hitachi Global Storage Technologies Netherlands N.V.Inventors: Detlef Gador, Cherngye Hwang, Eun Kyoung Row, Ning Shi
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Publication number: 20040178170Abstract: The present invention provides a mask blank used for the charged particle beam exposure made by employing an SOI substrate having a silicon membrane higher reliability in quality, without the problem of deformation due to the compression stress of a silicon oxide film as an intermediate layer of the SOI substrate, and provides a method for forming a mask blank and a mask used for the charged particle beam exposure. The mask blank used for the charged particle beam exposure made by employing an SOI substrate having a front-side silicon membrane and a back-side silicon layer with a silicon oxide layer interposed therebetween is characterized in that the back-side silicon layer and the silicon oxide film of said SOI substrate are partially removed to form an opening to be an exposed region and an etching stop layer having lower stress is formed in the opening.Type: ApplicationFiled: December 16, 2003Publication date: September 16, 2004Inventor: Kenichi Morimoto
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Publication number: 20040178169Abstract: Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N2; fluorocarbon (CHF3, C4F8, C4F6, CF2, CH2F2, CH3F); an oxidizer (O2, CO2), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (−20 to 60°).Type: ApplicationFiled: March 12, 2003Publication date: September 16, 2004Applicant: International Business Machines CorporationInventors: Sadanand V. Desphande, David Dobuzinsky, Arpan Mahorowala, Tina Wagner, Richard Wise
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Patent number: 6790377Abstract: An electroplating method includes forming a layer, the forming of the layer includes: a) contacting a substrate with a first article, the first article includes a support and a conformable mask disposed in a pattern on the support; b) electroplating a first metal from a source of metal ions onto the substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the substrate. The method may further involve one or more of (1) selectively depositing or non-selectively depositing one or more additional materials to complete formation of the layer, (2) planarizing deposited material after each deposition or after all depositions for a layer, and/or (3) forming layers adjacent previously formed layers to build up a structure from a plurality of adhered layers. Electroplating articles and electroplating apparatus are also disclosed.Type: GrantFiled: January 28, 2000Date of Patent: September 14, 2004Assignee: University of Southern CaliforniaInventor: Adam L. Cohen
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Patent number: 6741377Abstract: The invention provides a method for fabricating an optical device comprising at least one optical component formed on a transparent substrate. The method comprises determining an area of the substrate that is to be light-absorbing; and fabricating a light-absorbing mask on the determined area prior to fabricating the at least one optical component. The invention also provides an optical device comprising a substrate; and first and second optical components formed on the substrate, wherein the first optical component has two modes, each mode producing a different optical response to light incident thereupon, and wherein the second optical component absorbs light and is formed on the substrate before the first optical component is formed.Type: GrantFiled: July 2, 2002Date of Patent: May 25, 2004Assignee: Iridigm Display CorporationInventor: Mark W. Miles
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Patent number: 6716081Abstract: A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as an anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the multi-layered structure by forming a desired pattern of openings therein by way of, for example, etching. Such a template may, for example, be used in the alignment and adherence of spacer structures to an electrode plate during the fabrication of flat panel displays. When used in this context, the construction of such a template results in more precise control of the patterning and sizing of the holes formed therein which thereby allows for more precise placement of spacer structures as well as the use of spacer structures exhibiting relatively higher aspect ratios during the fabrication of flat panel displays.Type: GrantFiled: April 1, 2002Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventors: Won-Joo Kim, Robert J. Hanson, David H. Chun, Gary A. Evans, Seungwoo Lee, Jim J. Browning
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Patent number: 6716362Abstract: A method of etching a substrate, includes measuring a reflectance signal from a reflective material deposited on the substrate as the substrate is being etched, correlating the substrate etch rate to the reflectance signal from the reflective material, and using the etch relation between the substrate and the reflective material to determine the etch target.Type: GrantFiled: October 24, 2000Date of Patent: April 6, 2004Assignee: International Business Machines CorporationInventor: Jason Michael Benz
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Patent number: 6712903Abstract: Disclosed is a mask for evaluating selective epitaxial growth process. The disclosed mask comprises a mask pattern for resistance measurement to measure sheet resistance of grown single crystal silicon in a first area, a mask pattern for selectivity evaluation to evaluate selectivity of single crystal silicon growth in a second area diagonal to the first area, mask patterns for facet generation evaluation, having different shapes, to evaluate facet generation of grown single crystal silicon in a third area, mask patterns for loading effect evaluation, having different shapes, to evaluate growth of single crystal silicon by loading effect in the upper part of a fourth area and a mask pattern for uniformity evaluation to evaluate uniformity of grown single crystal silicon in the lower part of the pattern for loading effect evaluation in the fourth area.Type: GrantFiled: December 31, 2001Date of Patent: March 30, 2004Assignee: Hynix Semiconductor, Inc.Inventor: Woo Seock Cheong
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Publication number: 20040058252Abstract: The present invention provides a production method for a halftone phase mask which has an SiO2 substrate, an overlying refractory metal SixNy phase shifter layer (2) and an overlying chromium oxide or chromium mask layer (3), having the following steps: provision of a mask (4) on the chromium oxide or chromium mask layer (3); etching of the chromium oxide or chromium mask layer (3) for the purpose of forming a hard mask from the chromium oxide or chromium mask layer (3) in a first etching step; selective etching of the refractory metal SixNy phase shifter layer (2) using the hard mask in a plasma with a chlorine-containing and/or hydrogen-chloride-containing main gas in a second etching step with a predetermined cathode power of at least 20 W.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Inventors: Josef Mathuni, Gunther Ruhl
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Patent number: 6706201Abstract: For manufacturing substrate materials which are needed for the manufacture of electrical circuit carriers, methods are known in which metal layers are applied to a dielectric substrate by means of a glow discharge process and thereafter additional metal layers are applied by means of electroplating processes. These methods however are not suitable for the manufacture of substrate materials which are suitable for high frequency applications in the gigahertz range. The invention starts from the previously-mentioned methods and solves the described problem through the use of fluoropolymers and through coating of these materials by means of a glow discharge process with nickel, since by this means even very smooth surfaces of the substrate can be securely coated. The metallised materials can be coated with additional metal layers from electroless or electrolytic deposition baths.Type: GrantFiled: December 21, 2000Date of Patent: March 16, 2004Assignee: Atotech Deutschland GmbHInventors: Heinrich Meyer, Ralf Schulz, Roland Heinz, Eckart Klusmann
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Publication number: 20040033425Abstract: The invention refers to a procedure for etching of materials at the surface by focussed electron beam induced chemical reactions at said surface. The invention is characterized in that in a vacuum atmosphere the material which is to be etched is irradiated with at least one beam of molecules, at least one beam of photons and at least one beam of electrons, whereby the irradiated material and the molecules of the beam of molecules are excited in a way that a chemical reaction predetermined by said material and said molecules composition takes place and forms a reaction product and said reaction product is removed from the material surface —irradiation and removal step.Type: ApplicationFiled: May 2, 2003Publication date: February 19, 2004Inventors: Hans Wilfried Peter Koops, Klaus Edinger
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Publication number: 20040026360Abstract: A plurality of penetrating holes are formed in a substrate, each of the penetrating holes connecting a first opening and a second opening larger than the first opening. An etching resistant film is formed on a first surface of the substrate avoiding areas in which the first openings will be formed, part of the second surface in which the penetrating holes are formed being exposed so as to expose areas each of which includes two or more of the second openings. Small holes are formed in the formation regions for each of the penetrating holes. Etching having crystal orientation dependence is performed from both the first and second surfaces of the substrate.Type: ApplicationFiled: April 14, 2003Publication date: February 12, 2004Applicant: Seiko Epson CorporationInventors: Shinichi Yotsuya, Kazushige Umetsu, Daisuke Sawaki
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Patent number: RE39913Abstract: The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from this modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.Type: GrantFiled: May 22, 2003Date of Patent: November 6, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hun-Jan Tao, Huan-Just Lin, Fang-Cheng Chen