Forming Pattern Using Lift Off Technique Patents (Class 216/40)
  • Patent number: 11462404
    Abstract: An imprint apparatus forms a pattern on a substrate by an imprint process which includes a process of bringing an imprint material on the substrate into contact with a mold, a process of curing the imprint material, and a separating process of separating a cured product of the imprint material and the mold. The apparatus includes a substrate holding mechanism which includes a substrate chuck configured to chuck the substrate by sucking the substrate. The substrate chuck has a through hole, and the substrate holding mechanism suppresses a state in which a suction force by which the substrate chuck sucks the substrate is reduced due to the through hole and a gap which is formed between a back surface of the substrate and an upper surface of the substrate chuck in the separating process.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: October 4, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Naosuke Nishimura
  • Patent number: 11304303
    Abstract: Methods for forming electrical circuitries on three-dimensional (3D) structures and devices made using the methods. A method includes forming selectively shaped 3D structures using additive manufacturing. The method includes forming undercuts on upper-level pedestals of the 3D structures that effectively act as overhanging deposition masks for selectively preventing deposition of a selected material on a corresponding portions of lower levels. The method includes simultaneously forming and electrically isolating materials directionally deposited on the 3D structure.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: April 12, 2022
    Assignee: DUJUD LLC
    Inventor: Reza Abbaspour
  • Patent number: 11136673
    Abstract: A method of micro-texturing a substrate surface is disclosed, including printing a maskant on the substrate surface to define exposed surface zones on the substrate surface. The method further includes forming a micro-texture on the substrate surface by removing material from the exposed surface zones, and removing the maskant from the substrate surface.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: October 5, 2021
    Assignee: The Boeing Company
    Inventors: Raj Desai, Caitlin Elizabeth Auffinger, Conor Van Camp, Edward Greene
  • Patent number: 10808330
    Abstract: The present invention relates to a process for producing one or more electrical contacts on a component, comprising (a) applying one or more coatings on the component, where at least one of the coatings is a coating of an electrically conductive material, (b) applying a self-passivating metal or semiconductor and/or a dielectric material on the coated component, (c) structuring the passivating coating by laser treatment or etching, (d) contacting the structured coating with an electroplating bath, (e) etching the regions not covered with the galvanically deposited metal.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 20, 2020
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Markus Glatthaar, Jonas Bartsch, Sven Kluska, Thibaud Hatt, Andreas Rodofili, Martin Hermle
  • Patent number: 10699899
    Abstract: Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl3, antimony alkylamines, and antimony alkoxides, such as Sb(OEt)3. The oxygen source may be, for example, ozone. In some embodiments the antimony oxide thin films are deposited in a batch reactor. The antimony oxide thin films may serve, for example, as etch stop layers or sacrificial layers.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 30, 2020
    Assignee: ASM International N.V.
    Inventors: Raija H. Matero, Linda Lindroos, Hessel Sprey, Jan Willem Maes, David de Roest, Dieter Pierreux, Kees van der Jeugd, Lucia D'Urzo, Tom E. Blomberg
  • Patent number: 10510854
    Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mrunal A. Khaderbad, Hsueh Wen Tsau, Chia-Ching Lee, Da-Yuan Lee, Hsiao-Kuan Wei, Chih-Chang Hung, Huicheng Chang, Weng Chang
  • Patent number: 10345707
    Abstract: This disclosure relates to a process for stripping an organic film on a patterned semiconductor substrate. The process includes treating the organic film with an aqueous stripper composition to remove the organic film in one step. The organic film includes at least a first layer and a second layer, the first layer has a dissolution rate of at most about 0.01?/min in a developer at 25° C., and the second layer has a dissolution rate of greater than about 0.01?/min in the developer at 25° C.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 9, 2019
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Raj Sakamuri, Sanjay Malik, Ognian Dimov
  • Patent number: 10167546
    Abstract: Compositions of matter capable of being cast and cured to form a microreplicated pattern on a substrate, and further capable of swelling on exposure to water so as to release from that substrate. Water swellable acrylic polymers formed from these compositions, and methods of using same in nanoimprint lithography are also disclosed.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: January 1, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: John T. Strand, David B. Olson
  • Patent number: 10096733
    Abstract: Methods of preparing a dispersion of colloidal nanocrystals (NCs) for use as NC thin films are disclosed. A dispersion of NCs capped with ligands may be mixed with a solution containing chalcogenocyanate (xCN)-based ligands. The mixture may be separated into a supernatant and a flocculate. The flocculate may be dispersed with a solvent to form a subsequent dispersion of NCs capped with xCN-based ligands.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 9, 2018
    Assignee: The Trustees of the University of Pennsylvania
    Inventors: Cherie R. Kagan, Aaron T. Fafarman, Ji-Hyuk Choi, Weon-Kyu Koh, David K. Kim, Soong Ju Oh, Yuming Lai, Sung-Hoon Hong, Sangameshwar Rao Saudari, Christopher B. Murray
  • Patent number: 10035296
    Abstract: A substrate useful for imprint lithography having a location thereon defining an imprint field, the imprint field further defined by an interior region, a perimeter region surrounding the interior region, and a border, with the perimeter region further including fluid control features. A polymerizable material deposited on the substrate at the imprint field location is allowed to spread on the substrate, with the fluid control relief features redirecting the spreading of the polymerizable material so as to minimize spreading of the polymerizable material beyond the imprint field border as further imprint lithography techniques are then performed.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 31, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Zhengmao Ye, Niyaz Khusnatdinov, Edward Brian Fletcher
  • Patent number: 9828285
    Abstract: Described herein are methods for improved transfer of graphene from formation substrates to target substrates. In particular, the methods described herein are useful in the transfer of high-quality chemical vapor deposition-grown monolayers of graphene from metal, e.g., copper, formation substrates to ultrathin, flexible glass targets. The improved processes provide graphene materials with less defects in the structure.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 28, 2017
    Assignees: Corning Incorporated, ICFO—THE INSTITUTE OF PHOTONIC SCIENCES, INSTITUCIÓ CATALANA DE RECERCA I ESTUDIS AVANÇATS (ICREA)
    Inventors: Benedict Yorke Johnson, Xinyuan Liu, Prantik Mazumder, Kamal Kishore Soni, Tonglai Chen, Miriam Marchena, Valerio Pruneri
  • Patent number: 9816004
    Abstract: A pattern forming method includes forming a guide mask layer including a first feature having a first opening width, a second feature having a second opening width, a third feature having a third opening width. The first width being less than the second width and greater than the third width. A self-organizing material having a phase-separation period is disposed on the guide mask layer to at least partially fill the first, second, and third features. The self-organizing material is process to the cause phase-separation into first and second polymer portions. The first width is greater than the phase-separation period and the third width is less. A masking pattern is formed on the first layer by removing the second polymer portions and leaving the first polymer portions. The masking pattern is then transferred to the first layer.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: November 14, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Ayako Kawanishi, Yusuke Kasahara, Hiroki Yonemitsu
  • Patent number: 9520481
    Abstract: A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 13, 2016
    Assignee: Pragmatic Printing Limited
    Inventors: John James Gregory, Richard David Price
  • Patent number: 9472400
    Abstract: The disclosure relates to a method for making an epitaxial structure. A carbon nanotube film is placed on an epitaxial growth surface of a substrate. The carbon nanotube film defines a number of apertures so that part of the epitaxial growth surface is exposed from the apertures to form a first exposed part. A mask preform layer is deposited on the epitaxial growth surface to cover the carbon nanotube film. A thickness of the mask preform layer is smaller than a thickness of the carbon nanotube film so that a first part of the mask preform layer is deposited on surfaces of the carbon nanotube film and a second part of the mask preform layer is deposited on the first exposed part of the epitaxial growth surface. The carbon nanotube film is removed. An epitaxial layer is grown on the epitaxial growth surface.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: October 18, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 9381731
    Abstract: Epitaxial lift off systems and methods are presented. In one embodiment a tape is disposed on the opposite side of the epitaxial material than the substrate is used to hold the epitaxial material during the etching and removal steps of the ELO process. In various embodiments, the apparatus for removing the ELO film from the substrates without damaging the ELO film may include an etchant reservoir, substrate handling and tape handling mechanisms, including mechanisms to manipulate (e.g., cause tension, peel, widen the etch gap, etc.) the lift off component during the lift off process.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: July 5, 2016
    Assignee: ALTA DEVICES, INC.
    Inventors: Brian Brown, Brian Burrows, David Berkstressor, Gang He, Thomas J Gmitter
  • Patent number: 9136127
    Abstract: The invention discloses a method of fabricating a GOI silicon wafer, a GOI silicon wafer, and a method of GOI detection on the fabricated GOI silicon wafer, where the method of fabricating a GOI silicon wafer includes: in a process of fabricating a trench-type VDMOS, after a trench is formed and a gate oxide layer is grown, a poly-silicon layer is grown; and after the poly-silicon layer is grown, a mask of a metal layer is aligned with a silicon substrate with the poly-silicon layer grown, where the mask of the metal layer is a mask used in formation of the metal layer in the process of fabricating the VDMOS; and at least one pattern for GOI detection is formed on the silicon substrate with the poly-silicon layer grown, through the aligned mask of the metal layer in a photo-lithography to form a GOI silicon wafer.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: September 15, 2015
    Assignees: PEKING UNIVERSITY FOUNDER GROUP CO., LTD., FOUNDER MICROELECTRONICS INTERNATIONAL CO., LTD.
    Inventors: Wanli Ma, Wenkui Zhao
  • Patent number: 9081274
    Abstract: According to one embodiment, a pattern forming method includes, forming a first mask on a film to be processed, forming a guide that has a pattern including first openings and second openings, forming a second mask which covers the first openings and does not cover the second openings, etching the first mask using the second mask and the guide as a mask, removing the second mask, applying a self-assembling material into the first openings and the second openings, heating the self-assembling material to form a self-assembled pattern including a first polymer portion and a second polymer portion, etching the first polymer portion, etching the first mask using the second polymer portion and the guide as a mask, and processing the film to be processed using the first mask as a mask.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirokazu Kato
  • Publication number: 20150136450
    Abstract: There are provided a touch panel and a method of manufacturing the same. The touch panel includes: a substrate; and a plurality of fine conductive lines, each of the fine conductive lines including a first black layer formed to have a predetermined pattern, a metal layer formed in accordance with the first black layer, and a second black layer formed on the upper and side surfaces of the metal layer.
    Type: Application
    Filed: February 20, 2014
    Publication date: May 21, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sung HAN, Yang Je Lee
  • Patent number: 9023221
    Abstract: A method of forming a multi-layer graphene includes forming a stack of a graphitizing metal catalyst layer and graphene by repeatedly performing a cycle of first forming the graphitizing metal catalyst layer on a substrate, and then forming the graphene on the graphitizing metal catalyst layer, and removing the graphitizing metal catalyst layer.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-sung Woo, Jae-young Choi, Won-mook Choi, Hyeon-jin Shin, Seon-mi Yoon
  • Publication number: 20150079708
    Abstract: When a coating film 4 is formed on a substrate 1, on which elements 3 are formed, by an ALD film forming method or the like, the coating film 4 is partially removed in a simple step. A method for manufacturing an electronic device includes a step of coating the substrate 1 partially with a partially coating member 2, a step of forming the elements 3 on the substrate 1, a step of forming the coating film 4 on the substrate 1 to cover the elements 3 and the partially coating member 2, and a step of forming a crack 4A in the coating film 4 on the partially coating member 2.
    Type: Application
    Filed: March 27, 2012
    Publication date: March 19, 2015
    Applicants: TOHOKU PIONEER CORPORATION, PIONEER CORPORATION
    Inventors: Jun Sugahara, Hidetaka Ohazawa, Shinsuke Tanaka, Hiromu Nara, Hiroki Tan
  • Publication number: 20150077833
    Abstract: An electrowetting display includes first and second substrates facing each other, an electrowetting layer, a first electrode, a second electrode, and a hydrophobic barrier layer. The electrowetting layer is disposed between the first substrate and the second substrate and includes a first fluid and a second fluid, and the first fluid has an electrical conductivity or a polarity. The first electrode is disposed on the first substrate, and the second electrode forms an electric field in cooperation with the first electrode to control a position of the first fluid. The hydrophobic barrier layer is disposed between the first substrate and the electrowetting layer to cover the first electrode and includes a first surface making contact with the first electrode and a second surface having a hydrophobicity stronger than a hydrophobicity of the first surface and making contact with the electrowetting layer.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 19, 2015
    Inventors: SungHoon Yang, Woo Yong Sung
  • Patent number: 8968584
    Abstract: A method for manufacturing a liquid ejection head includes the steps of: disposing an etching mask layer on a substrate having a first face and a second face that is on an opposite side of the first face, the etching mask layer being disposed on the second face; forming a concave line pattern at a region of the etching mask layer other than a region where an opening for the support port is to be formed; providing an etching opening at the etching mask layer; performing anisotropic etching from a side of the second face using the etching mask layer provided with the etching opening as a mask, thus forming the supply port at the substrate; comparing the line pattern with a recess generated at the substrate, thus selecting a device chip for liquid ejection; and connecting the selected device chip to a liquid supply part.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: March 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jun Yamamuro, Yoshinori Tagawa, Satoshi Ibe, Hiroto Komiyama, Kouji Hasegawa, Shiro Sujaku
  • Patent number: 8961800
    Abstract: Functional nanoparticles may be formed using at least one nano-lithography step. In one embodiment, sacrificial material may be patterned on a multi-layer substrate using an imprint lithography system. The pattern may be further etched into the multi-layer substrate. Functional material may then be deposited on multi-layer substrate and solidified. At least a portion of the functional material may then be removed to provide a crown surface exposing pillars. Pillars may be removed from multi-layer substrate forming functional nanoparticles.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: February 24, 2015
    Assignees: Board of Regents, The University of Texas System, Molecular Imprints, Inc.
    Inventors: Sidlgata V. Sreenivasan, Shuqiang Yang, Frank Y. Xu, Vikramjit Singh
  • Patent number: 8951426
    Abstract: An implantable medical device formed from one or more layers of thin film polymer is assembled by providing by adhesively securely one or more polymer coupons on individual rigid backings. After each coupon is shaped or components mounted to the coupon, the coupons are bonded together. The adhesive is dissolved to remove the device from the backing or backings to which it is attached.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: February 10, 2015
    Assignee: Stryker Corporation
    Inventors: Robert Brindley, John Janik, Edward Chia-Ning Tang
  • Publication number: 20150017275
    Abstract: A fine concavo-convex structure product (10) is provided with an etching layer (11), and a resist layer (12) comprised of a heat-reactive resist material for dry etching provided on the etching layer (11), a concavo-convex structure associated with opening portions (12a) formed in the resist layer (12) is formed in the etching layer (11), a pattern pitch P of a fine pattern of the concavo-convex structure ranges from 1 nm to 10 ?m, a pattern depth H of the fine pattern ranges from 1 nm to 10 ?m, and a pattern cross-sectional shape of the fine pattern is a trapezoid, a triangle or a mixed shape thereof. The heat-reactive resist material for dry etching has, as a principal constituent element, at least one species selected from the group consisting of Cu, Nb, Sn, Mn, oxides thereof, nitrides thereof and NiBi.
    Type: Application
    Filed: January 24, 2013
    Publication date: January 15, 2015
    Inventor: Yoshimichi Mitamura
  • Publication number: 20140374379
    Abstract: According to one embodiment, a pattern forming method includes, forming a first mask on a film to be processed, forming a guide that has a pattern including first openings and second openings, forming a second mask which covers the first openings and does not cover the second openings, etching the first mask using the second mask and the guide as a mask, removing the second mask, applying a self-assembling material into the first openings and the second openings, heating the self-assembling material to form a self-assembled pattern including a first polymer portion and a second polymer portion, etching the first polymer portion, etching the first mask using the second polymer portion and the guide as a mask, and processing the film to be processed using the first mask as a mask.
    Type: Application
    Filed: February 14, 2014
    Publication date: December 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hirokazu KATO
  • Patent number: 8914970
    Abstract: A tunneling magnetoresistive sensor has an extended pinned layer wherein both the MgO spacer layer and the underlying ferromagnetic pinned layer extend beyond the back edge of the ferromagnetic free layer in the stripe height direction and optionally also beyond the side edges of the free layer in the trackwidth direction. A patterned photoresist layer with a back edge is formed on the sensor stack and a methanol (CH3OH)-based reactive ion etching (RIE) removes the unprotected free layer, defining the free layer back edge. The methanol-based RIE terminates at the MgO spacer layer without damaging the underlying reference layer. A second patterned photoresist layer may be deposited and a second methanol-based RIE may be performed if it is desired to have the reference layer also extend beyond the side edges of the free layer in the trackwidth direction.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: December 23, 2014
    Assignee: HGST Netherlands B.V.
    Inventor: Jordan Asher Katine
  • Patent number: 8906247
    Abstract: The present disclosure provides a patterning process for an oxide film, including: covering a barrier layer composition on a substrate to form a patterned barrier layer, wherein the barrier layer composition includes an inorganic component and an organic binder with a weight ratio of 50-98:2-50; forming an oxide film on the patterned barrier layer and the substrate, wherein a thickness ratio (D1/D2) of the barrier layer (D1) to the oxide film (D2) is about 5-2000; and lifting off the barrier layer and the oxide film thereon, while leaving portions of the oxide film on the substrate.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: December 9, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Chin-Ching Lin, Yu-Chun Chen, En-Kuang Wang, Mei-Ching Chiang, Yi-Chen Chen
  • Patent number: 8906706
    Abstract: A method of fabricating workpieces includes one or more layers on a substrate that are masked with an ion implantation mask comprising two or more layers. The mask layers include a first mask layer closer to the substrate, and a second mask layer on the first mask layer. The method also comprises ion implanting one or more of the layers on the substrate. Ion implantation may form portions with altered physical properties from the layers under the mask. The portions may form a plurality of non-magnetic regions corresponding to apertures in the mask.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 9, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Kanaiyalal C. Patel, Kurt A. Rubin
  • Patent number: 8877076
    Abstract: A substrate treatment apparatus is used for treating a major surface of a substrate with a chemical liquid. The substrate treatment apparatus includes: a substrate holding unit which holds the substrate; a chemical liquid supplying unit having a chemical liquid nozzle which supplies the chemical liquid onto the major surface of the substrate held by the substrate holding unit; a heater having an infrared lamp to be located in opposed relation to the major surface of the substrate held by the substrate holding unit to heat the chemical liquid supplied onto the major surface of the substrate by irradiation with infrared radiation emitted from the infrared lamp, the heater having a smaller diameter than the substrate; and a heater moving unit which moves the heater along the major surface of the substrate held by the substrate holding unit.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 4, 2014
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Sei Negoro, Ryo Muramoto, Toyohide Hayashi, Koji Hashimoto, Yasuhiko Nagai
  • Patent number: 8877073
    Abstract: Systems, methods, and processes for forming imprint lithography templates from a multi-layer substrate are described. The multi-layer substrate may include a block copolymer layer positioned on a substrate layer. The block copolymer layer may include two or more domains. At least one domain may have a different composition sensitivity than another domain such that the domains have different reactions to a specific process. Reaction of the domains to the specific process may provide a pattern in the block copolymer layer. The pattern may be transferred into the substrate layer to form the imprint lithography template.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: November 4, 2014
    Assignee: Canon Nanotechnologies, Inc.
    Inventors: Gerard M. Schmid, Douglas J. Resnick, Sidlgata V. Sreenivasan, Frank Y. Xu
  • Publication number: 20140305904
    Abstract: The present invention discloses a nanoimprint apparatus and method useful in the cost-effective mass production of nanostructures over large areas on various substrates or surfaces, especially suitable for non-flat substrates or curved surfaces. The nanoimprint apparatus is composed of a wafer stage, a vacuum chuck, a substrate, a UV-curable nanoimprint resist and the like. The method implementing large-area nanopatterning based on the apparatus includes the following steps: (1) pretreatment, (2) imprinting, (3) curing, (4) demolding, (5) post treatment and (6) transferring of imprinted patterns. By utilizing the apparatus and the approach, large-area, and/or high-aspect-ratio micro/nanostructures can be mass produced, especially on a non-flat substrate or a curved surface or a fragile substrate at low cost and high throughput.
    Type: Application
    Filed: October 25, 2012
    Publication date: October 16, 2014
    Inventor: Hongbo Lan
  • Patent number: 8846537
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Publication number: 20140287083
    Abstract: A method using directed self-assembly of block copolymers (BCPs) for making an imprint template has the required patterns for both the features in the template's active area and the optically-detectable alignment marks in the template's non-active area. A chemical contrast pattern defined by a lithographic technique forms patterns of lines in both the active area and non-active area, as well as patterns of featureless gap regions in the non-active area. The pattern of lines has the BCP components aligned as lamellae perpendicular to the substrate, while the pattern of featureless gap regions has the BCP components aligned as lamellae parallel to the substrate. The patterns of lines and featureless gap regions in the non-active area define the optically detectable alignment marks. One of the BCP components is removed, leaving the other BCP component as an etch mask to fabricate the imprint template.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 25, 2014
    Applicant: HGST Netherlands B.V.
    Inventors: He Gao, Lei Wan
  • Publication number: 20140263171
    Abstract: A method for forming a wet-etchable, sacrificial lift-off layer or layers compatible with high temperature processing, a sacrificial layer, defined as consisting of a single film of one material or multiple films of multiple materials, that can tolerate high temperatures, is deposited on a substrate, called the original substrate, by sputtering or another suitable technique (e.g. evaporation, pulsed laser deposition, wet chemistry, etc.). Intermediate steps result in a lift-off layer attached to the lift-off substrate, that allow for separating the product from the original substrate.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 18, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Jesse A. Frantz, Jason D. Myers, Robel Y. Bekele, Jasbinder S. Sanghera
  • Publication number: 20140255206
    Abstract: Embodiments of the invention relate generally to turbine blades and, more particularly, to the formation of cooling channels on a surface of a turbine blade and turbine blades including such cooling channels. In one embodiment, the invention provides a method of forming a cooling channel along a surface of a turbine blade, the method comprising: applying a first mask material to a first portion of a surface of a turbine blade; forming a first barrier layer atop the first mask material and atop a second portion of the surface of the turbine blade; removing the first mask material and the barrier layer atop the first mask material to expose the first portion of the surface of the turbine blade; and etching the first portion of the surface of the turbine blade to form a cooling channel along the surface of the turbine blade.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: David Bruce Knorr, Kathleen Blanche Morey
  • Patent number: 8790520
    Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes punching a plurality of segments out of at least one sheet of substrate material to form a plurality of layers of the Z-directed component. A channel is formed through the substrate material either before or after the segments are punched. At least one of the formed layers includes at least a portion of the channel. A conductive material is applied to at least one surface of at least one of the formed layers. A stack of the formed layers is combined to form the Z-directed component.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: July 29, 2014
    Assignee: Lexmark International, Inc.
    Inventors: Paul Kevin Hall, Keith Bryan Hardin, Zachary Charles Nathan Kratzer, Qing Zhang
  • Patent number: 8778199
    Abstract: The present disclosure provides a process for manufacturing a solar cell by selectively freeing an epitaxial layer from a single crystal substrate upon which it was grown. In some embodiments the process includes, among other things, providing a first substrate; depositing a separation layer on said first substrate; depositing on said separation layer a sequence of layers of semiconductor material forming a solar cell; mounting and bonding a flexible support on top of the sequence of layers; etching said separation layer while applying an agitating action to the etchant solution so as to remove said flexible support with said epitaxial layer from said first substrate.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: July 15, 2014
    Assignee: Emoore Solar Power, Inc.
    Inventors: Arthur Cornfeld, Daniel McGlynn, Tansen Varghese
  • Patent number: 8758636
    Abstract: A method for producing a medical functional element having a self-supporting lattice structure which has interconnected webs. The method applies a first layer to the substrate layer, the first layer is structured by an etching process, the structured first layer is under-cut of a wet chemical etching process acting on the substrate layer, the substrate layer is removed in order to form the self-supporting lattice structure, a web constructional layer is applied to the first layer. The method is distinguished by the forming the first web attachment layer which has a smaller layer thickness than the web constructional layer and is intimately bonded to the web constructional layer in such a way that the web attachment layer, together with the web constructional layer, forms the webs of the self-supporting lattice structure.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: June 24, 2014
    Assignee: ACANDIS GmbH & Co. KG
    Inventors: Eckhard Quandt, Christiane Zamponi, Rodrigo Lima De Miranda
  • Patent number: 8734659
    Abstract: A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H2O2, thus producing a metallized substrate with one or more trenches. A second silicon etch is optionally employed to remove nanowires inside the one or more trenches.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: May 27, 2014
    Assignee: Bandgap Engineering Inc.
    Inventors: Brent A. Buchine, Faris Modawar, Marcie R. Black
  • Patent number: 8728331
    Abstract: A method of fabricating an imprint mold is disclosed. The method includes: forming a first photo resist pattern on a substrate; etching the substrate using the first photo resist pattern as an etch mask to form a first pattern in the substrate; ashing the first photo resist pattern to form a second photo resist pattern; and etching the substrate using the second photo resist pattern to form a second pattern derived from the substrate and a third pattern derived from the first pattern.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: May 20, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Doo Hee Jang, Dhang Kwon, Hang Sup Cho, Ho Su Kim
  • Patent number: 8726491
    Abstract: A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc0. The NCC layer may have be a composite wherein conductive M(Si) grains are magnetically coupled with adjacent ferromagnetic layers and are formed in an oxide, nitride, or oxynitride insulator matrix. The upper spin valve has a Cu spacer to lower the free layer damping constant. A high annealing temperature of 360° C. is used to increase the MR ratio above 100%. A Jc0 of less than 1×106 A/cm2 is expected based on quasistatic measurements of a MTJ with a similar MgO tunnel barrier and composite free layer.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: May 20, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Cheng T. Horng, Ru-Ying Tong
  • Publication number: 20140098330
    Abstract: A polarizer includes an opening defined in the polarizer and through which light transmits; a non-opening which is adjacent to the opening and blocks the light; a plurality of metal lines elongated in a first direction, and separated from each other in a second direction different than the first direction, in the opening; and a plate-type pattern in the non-opening. A height of the metal lines is smaller than a height of the plate-type pattern, from a same reference; and an interval in the second direction and between adjacent metal lines is smaller than a wavelength of visible light rays.
    Type: Application
    Filed: May 17, 2013
    Publication date: April 10, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jung Gun NAM, Dae-Young LEE, Dae Hwan JANG, Gug Rae JO, Atsushi TAKAKUWA
  • Publication number: 20140093688
    Abstract: Methods of fabricating nano-structures on a substrate surface are provided including the use of small initial pilot nano-structures patterned in a writing layer which are enlarged upon transfer to a pattern transfer layer among process layers applied to the substrate material, before removal of the writing layer to reveal the enlarged nano-structures. Enlarged nano-structures are transferred to the substrate by etch techniques to produce desired final enlarged nano-structures in the substrate surface. Raised out of plane and etched-in-plane nano-structures may be produced. Multiple geometries, configurations and spacings of 2D (such as in-plane nano-structures) and/or 3D (such as out of plane nano-structures) nano-structures and/or grids or arrays thereof may be fabricated on a surface of a substrate according to a single fabrication process.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Yindar CHUO, Clinton LANDROCK, Badr OMRANE, Bozena Kaminska
  • Patent number: 8673161
    Abstract: Methods for fabricating a device component are provided. A substrate comprising a RIE stop layer, an oxide layer formed on the RIE stop layer, and a RIE-able layer formed on the oxide layer may be provided. A resist layer may be patterned on the RIE-able layer. A metal layer may be formed on portions of the RIE-able layer that are not covered by the resist layer. The resist layer may be removed and an RIE performed to remove exposed portions of the RIE-able layer and portions of the oxide layer beneath the exposed portions of the RIE-able layer. Thereafter, the metal layer may be removed, and the component may be formed in an opening in the oxide layer formed during the RIE.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: March 18, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Christian R. Bonhôte, Jeffrey S. Lille, Ricardo Ruiz
  • Patent number: 8661634
    Abstract: A method of manufacturing a flexible piezoelectric device including laminating a first metal layer on a silicon oxide layer on a silicon substrate. The method further includes laminating a device on the first metal layer and annealing the first metal layer to oxidize the first metal into a first metal oxide. The method further includes etching the first metal oxide to separate the device from the silicon oxide layer and transferring the separated device to a flexible substrate using a transfer layer. The metal oxide layer laminated on the silicon substrate is etched to separate the device from the substrate. As a result, physical damage of the silicon substrate is prevented and a cost of using expensive single-crystal silicon substrate is reduced.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: March 4, 2014
    Assignee: KAIST (Korea Advanced Institute of Science and Technology
    Inventors: Keon Jae Lee, Suk Joong L. Kang, Jaemyung Chang, Kwi-il Park, Seungjun Kim, Sang Yong Lee
  • Publication number: 20140034605
    Abstract: The present disclosure provides a patterning process for an oxide film, including: covering a barrier layer composition on a substrate to form a patterned barrier layer, wherein the barrier layer composition includes an inorganic component and an organic binder with a weight ratio of 50-98:2-50; forming an oxide film on the patterned barrier layer and the substrate, wherein a thickness ratio (D1/D2) of the barrier layer (D1) to the oxide film (D2) is about 5-2000; and lifting off the barrier layer and the oxide film thereon, while leaving portions of the oxide film on the substrate.
    Type: Application
    Filed: July 15, 2013
    Publication date: February 6, 2014
    Inventors: Chin-Ching LIN, Yu-Chun CHEN, En-Kuang WANG, Mei-Ching CHIANG, Yi-Chen CHEN
  • Publication number: 20140021167
    Abstract: Methods for creating nano-shaped patterns are described. This approach may be used to directly pattern substrates and/or create imprint lithography molds that may be subsequently used to directly replicate nano-shaped patterns into other substrates in a high throughput process.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 23, 2014
    Applicants: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM, MOLECULAR IMPRINTS, INC.
    Inventors: Sidlgata V. Sreenivasan, Shuqiang Yang, Frank Y. Xu, Dwayne L. LaBrake
  • Publication number: 20140021166
    Abstract: According to one embodiment, a pattern forming method includes forming a physical guide that includes a first predetermined pattern in a first region on a lower layer film, and includes a second predetermined pattern and a dummy pattern in a second region on the lower layer film, forming a block polymer inside the physical guide, making the block polymer microphase-separated to form a pattern having a first polymer section and a second polymer section, removing the second polymer section to form a hole pattern, and processing the lower layer film after removal of the second polymer section, with the physical guide and the first polymer section used as a mask. Shapes of the hole patterns in the first and the second predetermined patterns are transferred to the lower layer film. A shape of the hole pattern in the dummy pattern is not transferred to the lower layer film.
    Type: Application
    Filed: January 30, 2013
    Publication date: January 23, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuriko SEINO, Hirokazu KATO, Hiroki YONEMITSU
  • Patent number: 8628673
    Abstract: Disclosed are: a resin composition for pattern formation, which enables the stable formation of a pattern at a level of the wavelength of light; a method for forming a pattern having a sea-island structure using the composition; and a process for producing a light-emitting element that can achieve high luminous efficiency properties.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: January 14, 2014
    Assignees: Kabushiki Kaisha Toshiba, Asahi Kasei E-Materials Corporation
    Inventors: Koji Asakawa, Ryota Kitagawa, Akira Fujimoto, Yoshiaki Shirae, Tomohiro Yorisue, Akihiko Ikeda