Forming Pattern Using Lift Off Technique Patents (Class 216/40)
  • Patent number: 6040110
    Abstract: The present invention provides a process for the removal of a resist layer formed on a semiconductor substrate, which enables easy removal of a resist layer without causing any damage on a gate oxide layer, and an apparatus therefor. The process comprises the steps of forming a gate oxide layer on the semiconductor substrate; forming a resist layer as a resist pattern on the gate oxide layer; removing the gate oxide layer at unnecessary area utilizing the resist layer as a mask; applying a pressure-sensitive adhesive sheet to the semiconductor substrate such that the gate oxide layer left on the semiconductor substrate and the resist layer are masked, and peeling the pressure-sensitive adhesive sheet together with the resist layer off the semiconductor substrate to separate and remove the resist layer from the semiconductor substrate.
    Type: Grant
    Filed: August 6, 1998
    Date of Patent: March 21, 2000
    Assignee: Nitto Denko Corporation
    Inventors: Seiichirou Shirai, Toshihiko Onozuka, Takayuki Noishiki, Satoshi Sakai, Katsuhiro Sasajima, Eiji Toyoda, Makoto Namikawa
  • Patent number: 6037005
    Abstract: A method for enhancing the conductivity of transparent conductive electrodes on display substrates by providing patterned auxiliary metallic layers adjacent to the transparent conductive material. The method of the present invention eliminates the need for aligning the auxiliary metal layers with preexisting transparent conductive electrodes by providing for simultaneous patterning of the auxiliary metal layers and formation of the independently addressable electrodes.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: March 14, 2000
    Assignee: 3M Innovative Properties Company
    Inventors: Robert S. Moshrefzadeh, Raghunath Padiyath
  • Patent number: 6030541
    Abstract: A pattern in a surface is defined by providing on the surface a hard mask material; depositing an anti-reflective coating on the hard mask material; applying a photoresist layer on the anti-reflective coating; patterning the photoresist layer, anti-reflective layer and hard mask material; and removing the remaining portions of the photoresist layer and anti-reflective layer; and then patterning the substrate using the hard mask as the mask. Also provided is a structure for defining a pattern in a surface which comprises a surface having a hard mask material thereon; an anti-reflective coating located on the hard mask material; and a photoresist located on the anti-reflective coating. Also provided is an etchant composition for removing the hard mask material which comprises an aqueous composition of HF and chlorine.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: February 29, 2000
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Michael Caterer, James T. Marsh, Hung Ng, James M. Oberschmidt, Jed H. Rankin
  • Patent number: 6022803
    Abstract: In a fabrication method of a semiconductor apparatus, the semiconductor apparatus is made with a selective gold plating process rather than an ion-milling process. A tungsten film (W film) as a current supplying layer is formed on the entire front surface of an insulation film. The insulation film is formed on a GaAs substrate on which devices such as FETs are formed. With a mask of a photoresist film, a titanium (Ti) film, a platinum (Pt) film, and a gold (Au) film are successively evaporated and then lift-off process is performed. A photoresist film is patterned. A gold plate film with a thickness of 8 .mu.m is formed. The current supplying layer is removed by magnetron discharge plasma ion-etching process. Thick U-shaped gold plate lines are formed.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: February 8, 2000
    Assignee: NEC Corporation
    Inventor: Kiyoshi Takahashi
  • Patent number: 6022752
    Abstract: A mandrel for forming a nozzle plate having orifices of precise size and location, and method of making the mandrel. The nozzle plate is formed by overcoating a substrate with a metal film. The film is covered with a photoresist material. Portions of the photoresist are exposed to light passing through a photomask having an annular light-transparent regions, of precise diameters and pitch. The photoresist is subjected to a developer bath which dissolves the photoresist exposed to the light, thereby revealing selected portion of the film. Next, an etchant is brought into contact with the film for etching-away the film so as to an annular opening in the film defining a column of precise diameter at the center of each opening. A new photoresist layer is then applied to the film. Portions of the new photoresist layer is exposed to light passing through a second photomask.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: February 8, 2000
    Assignee: Eastman Kodak Company
    Inventors: Jeffrey I. Hirsh, Xin Wen
  • Patent number: 6007731
    Abstract: A soft adjacent layer (SAL) magnetoresistive (MR) sensor element and a method for fabricating the soft adjacent layer (SAL) magnetoresistive (MR) sensor element. To practice the method, there is first provided a substrate. There is formed over the substrate a dielectric layer which has a first surface of the dielectric layer and a second surface of the dielectric layer opposite the first surface of the dielectric layer. The is also formed over the substrate a magnetoresistive (MR) layer in contact with the first surface of the dielectric layer. Similarly, there is also formed over the substrate a soft adjacent layer (SAL) in contact with the second surface of the dielectric layer, where the magnetoresistive (MR) layer, the soft adjacent layer (SAL) and the dielectric layer are planar and preferably at least substantially co-extensive. The invention contemplates a soft adjacent layer (SAL) magnetoresistive (MR) sensor element formed employing the method of the invention.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: December 28, 1999
    Assignee: Headway Technologies, Inc.
    Inventors: Cherng-Chyi Han, Mao-Min Chen, Kochan Ju
  • Patent number: 5944975
    Abstract: A method of fabricating an emitter plate 12 for use in a field emission device comprising the steps of providing an insulating substrate 18 and forming a first conductive layer 13 on the insulating substrate 18. This is followed by the steps of forming an insulating layer 20 on the first conductive layer 13 and forming a second conductive layer 22 on the insulating layer 20. Then, a plurality of apertures 34 are formed through the second conductive layer 22 and through the insulating layer 20. A lift-off layer 36 is then formed on the second conductive layer 22. The lift-off layer 36 is formed by a plating process wherein the plating bath has a pH between 2.25 and 4.5, and current densities of 1 to 2O mA/cm.sup.2. The method may further comprise depositing conductive material through the plurality of apertures 34 to form a microtip 14 in each of the plurality of apertures 34. The excess deposited conductive material 14' and the lift-off layer 36 are then removed from the second conductive layer 22.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: August 31, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Arthur M. Wilson, Chi-Cheong Shen, Saroja Ramamurthi
  • Patent number: 5883011
    Abstract: A method of removing an inorganic antireflective coating from a semiconductor substrate and a method of forming an integrated circuit (IC) are provided. In the former method, a sacrificial layer is formed over a semiconductor substrate, the layer being selectively removable from the substrate and compatible with photolithography. An inorganic antireflective coating such as SiON is then formed over the sacrificial layer. Thereafter, the sacrificial layer is removed from the substrate to lift the coating off the substrate. Preferred materials for the sacrificial layer include TiN, tetraethyl orthosilicate-based silicon oxide, spin-on-glass (SOG) such as hydrogen silsesquioxane and methyl silsesquioxane, and porous polymeric materials. In the latter method, a patterned layer of photoresist material is formed over the anitreflective coating.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: March 16, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Xi-Wei Lin, Satyendra Sethi, Henry Lee
  • Patent number: 5824116
    Abstract: A method for applying an image to a light switch plate is provided. The method specifically enables the application of an image continuously and without interruption to both the surface of the plate and to the heads of the screws that are used in mounting the plate to a wall or other supporting surface.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: October 20, 1998
    Assignee: MCI Products Group, Inc.
    Inventor: Bruce Zutler
  • Patent number: 5788856
    Abstract: A process for fabricating multisegment ridge waveguides is disclosed which is self-aligning and avoids unnecessary masking and etching steps. The process essentially comprises five steps: removing, in a starting layer structure, a top layer (DS) on both sides of areas where segment transitions (ST) are to be formed; depositing a metal contact layer (KM); etching a desired ridge-waveguide structure (R); covering the entire area except the segment transition areas with photoresist; and removing the contact layer (KM) in the segment transition areas by a lift-off step, thus providing electrical separation between the individual segments.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: August 4, 1998
    Assignee: Alcatel NV
    Inventor: Edgar Kuhn
  • Patent number: 5785871
    Abstract: A process for the minute processing of diamonds which comprisespreparing a substrate;forming a first buffer layer on the substrate;forming a second buffer layer, having a higher charge transfer rate than both the substrate and the first buffer layer, on the first layer;selectively removing the first and second buffer layers to selectively expose the surface of the substrate;depositing diamonds on the whole surface of the exposed surface of the substrate and the remaining first and second buffer layer; andremoving the by-products formed on the surface of the second buffer layer and surface thereof.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: July 28, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Hyun Pil Noh
  • Patent number: 5711889
    Abstract: A dichroic filter array is mounted on a wafer by combining microelectronic and microlithography techniques. A release layer of copper is evaporated onto a wafer, and the release layer is coated with a photoresist. The assembly is masked, and the unmasked photoresist, after exposure to ultraviolet light, is developed to expose a predetermined section of the release layer. That section of release layer is then overetched to create an undercut in its walls and to expose the underlying wafer. Dichroic filter material is then deposited onto the wafer by a cold process, and the release layer is then removed, leaving only the dichroic filter material on the wafer. The process is repeated to create an array.
    Type: Grant
    Filed: September 15, 1995
    Date of Patent: January 27, 1998
    Inventor: Philip E. Buchsbaum
  • Patent number: 5665251
    Abstract: A method is provided for constructing well defined plated miniature metallic structures. A seedlayer may be formed over an insulative layer such as a gap layer of a write head. A protective layer, such as alumina or silicon dioxide, is formed on top of the seedlayer to protect it from a subsequent reactive ion etching (RIE) step. A relatively thick layer of material, such as polymeric photoresist, is formed on top of the protective layer, the thick layer being of a type of material which can be patterned by reactive ion etching. By photolithography, an RIE mask, such as a thin layer of patterned metal, is formed on top of the relatively thick resist layer. The pattern of the mask corresponds to the desired shape of the metallic structure to be formed by plating. After masking the relatively thick layer the relatively thick layer is anisotropically etched by RIE.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: September 9, 1997
    Assignee: International Business Machines Corporation
    Inventors: Neil Leslie Robertson, Hugo Alberto Emilio Santini, Clinton David Snyder
  • Patent number: 5658469
    Abstract: A method for forming a re-entrant photoresist lift-off profile for thin film device processing of particular utility in conjunction with self-aligned sputtered films, such as permanent magnet ("PM") films, for use in magnetoresistive ("MR") read heads as well as a device made thereby. Photoresist is patterned in a conventional manner upon the thin film layers overlying a suitable substrate and the photoresist is then exposed to a suitable developer resulting in photoresist regions having substantially vertical sidewalls. An electron beam, or other suitable energy source, is then utilized to cross-link (or render relatively insoluble) the upper portion of the positive tone resist image by accelerating a sufficient dose of electrons into the photoresist to a well controlled depth. A second electron beam is then distributed throughout the entire photoresist thickness to render the lower portion of it relatively more soluble in a developer.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: August 19, 1997
    Assignee: Quantum Peripherals Colorado, Inc.
    Inventor: Michael J. Jennison
  • Patent number: 5656525
    Abstract: A new method for forming an array of high aspect ratio field emitter for flat panel Field Emission Displays (FEDs) was accomplished. The method involves forming on an insulated substrate an array of parallel cathodes and then depositing a dielectric layer and forming a array of parallel gate electrodes essentially orthogonal to the array of cathode electrodes. Opening are then made in the upper gate electrodes and dielectric layer over the lower cathode electrodes. The field emitters with high aspect-ratios are then formed on the cathode by depositing an emitter material, such as molybdenum, in the opening while heating the substrate to high temperatures. The emitter material is removed elsewhere on the substrate by utilizing a release layer and thereby completing the gated field emitter. This high temperature method results in high aspect-ratio gated emitters that allow the inter-electrode dielectric layer to be increased and thereby improving the circuit performance.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: August 12, 1997
    Assignee: Industrial Technology Research Institute
    Inventors: Ching-Yuan Lin, Peng Chao-Chi, Kyan-Lun Chang, Jermmy J. M. Wang
  • Patent number: 5651899
    Abstract: In the method according to the invention for the production of multilayer foil printed circuit board from preliminary products (A), with current paths (B) structured in electrical conductive layers (1,3) and with electrically conductive metal platings (C,D) from conductive layer (1) to conductive layer (3) through an insulating layer (2), or for producing semifinished products for such foil circuit boards, in first method steps a structuring means (7,7',13) is applied in controlled, local manner to the preliminary product (A) and resist layers (8,9) are coated with the preliminary product (A), the structuring means (7,7',13) being applied either to the resist layers (8,9) and the resist layer (8,9) is locally removed, or the resist layers (8,9) are applied to the structuring means (7,7',13) and in a further method step the applied structuring means (7,7',13) are removed, so that openings (10,10') are formed in the resist layers (8,9) and extend down to the insulating layer (2) and in a further method step thr
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: July 29, 1997
    Assignee: Dyconex Patente AG
    Inventors: Walter Schmidt, Marco Martinelli
  • Patent number: 5651898
    Abstract: A field emission cold cathode comprises a conductive substrate, an insulating layer formed on the substrate and having plural cavities each for receiving an emitter, a gate electrode for applying a high electric field to the tips of emitters. An annular portion of the gate electrode each defining an opening overlapping corresponding cavity is located at a distance from the substrate smaller than the distance between another portion of the gate electrode and the substrate. Parasitic capacitance between the gate electrode and the cold cathode including the substrate and the emitter is reduced due to the large distance between the another portion of the gate electrode and the substrate. Between the another portion and the substrate, a second insulating layer or a gap is disposed. The field emission is cold cathode can function in a high frequency range while fabricating conical emitters with a small height due to the small distance between the annular portions and the substrate.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: July 29, 1997
    Assignee: NEC Corporation
    Inventor: Hironori Imura
  • Patent number: 5622634
    Abstract: An electron-emitting device comprising a pair of device electrodes and an electroconductive film including an electron-emitting region is manufactured by a method comprising a process of forming an electroconductive film including steps of forming a pattern on a thin film containing a metal element on the basis of a difference of chemical state, and removing part of the thin film on the basis of the difference of chemical state.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: April 22, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Noma, Seijiro Kato, Fumio Kishi, Hisaaki Kawade, Toshikazu Ohnishi, Michiyo Nishimura, Kumiko Uno, Takahiro Horiguchi, Masato Yamanobe
  • Patent number: 5580604
    Abstract: A method of manufacturing a hot-stamped decal includes step A: preparing a metalized polyester film including a metalized layer disposed on a top surface thereof, a clear polyester sheet disposed to an under side of the metalized layer, an adhesive layer disposed to an under side of the clear polyester sheet and a release sheet disposed to an under side of the adhesive layer, step B: applying a printing process on the metalized layer to form a mark thereon composed of a printed ink layer, step C: preparing an alkaline corrosive solution, step D: flushing the top surface of the metalized layer with the alkaline solution composed of water and NaOH to the top surface of the metalized layer to corrode the metalized layer not covered by the printing ink layer, step E: flushing the top surface of the metalized layer with water and step F: drying the hot-stamped decal.
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: December 3, 1996
    Inventor: Chih C. Chang
  • Patent number: 5559057
    Abstract: Patterns or circuits of semiconductors or metals are produced with dimensions at least as small as 7 nm using nanocrystalline precursors. The substrate is masked with an electron beam sensitive layer and a pattern is traced using a focused electron beam. Exposure to a source of nanocrystalline material and dissolution of the mask material produces patterned features of nanocrystals. The sample may then be heated to form a bulk thin film or left unheated, preserving the electronic properties of the isolated particles. The process is repeatable with different materials to build laminar structures of metals, semiconductors and insulators.
    Type: Grant
    Filed: March 24, 1994
    Date of Patent: September 24, 1996
    Assignee: Starfire Electgronic Development & Marketing Ltd.
    Inventor: Avery N. Goldstein
  • Patent number: 5527766
    Abstract: Novel structures and methods utilize layered copper oxide release materials to separate oxide films from growth substrates. Generally, the method comprises the steps of: first, forming a layered copper oxide sacrificial release material on a growth substrate, in the preferred embodiment being the high temperature superconductor YBCO grown on a compatible substrate such as LaAlO3, second, forming an oxide film on the layered copper oxide release material, in the preferred embodiment, a ferroelectric, an optical material or a oxide film compatible with further high temperature superconductor growth, such as SrTiO3 or CeO2, and third, etching the layered copper oxide release material so as to separate the oxide film from the growth substrate. Optionally, additional layers may be grown on the oxide film prior to etching.
    Type: Grant
    Filed: December 13, 1993
    Date of Patent: June 18, 1996
    Assignee: Superconductor Technologies, Inc.
    Inventor: Michael M. Eddy
  • Patent number: 5509840
    Abstract: A method for fabricating high aspect ratio spacers for a field emission display is described. An array of field emission microtips is formed over a substrate. A layer of lithographic material is formed over the array of field emission microtips. Openings are formed in the layer of lithographic material. The openings may be formed by a plasma etch with oxygen, or by x-ray lithography. A non-outgassing material is formed over the surface of the layer of lithographic material, including in the openings. The openings are filled with a spacer material, the spacer material being a conductive material, an insulator, or, preferably, a combination thereof. Lastly, the layer of lithographic material and the non-outgassing material are removed.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: April 23, 1996
    Assignee: Industrial Technology Research Institute
    Inventors: Jammy C. Huang, David N. Liu
  • Patent number: 5484074
    Abstract: A method for manufacturing a shadow mask for use in a cathode ray tube includes providing a thin metal web having a first and second major surfaces. Photosensitive layers are formed on the first and second major surfaces. The first photosensitive layer is exposed to a first patterned light and the second photosensitive layer is exposed to a second patterned light. The exposure is continued until respective accumulated exposure of the photosensitive layers reaches a predetermined value. Next, a first protective film is applied to the second photosensitive layer to prevent etching of the second surface. The first surface is then etched to form a first cavity. The first cavity has a depth that is less than a distance from the first surface to the second surface. A second protective film is applied to the first surface to prevent additional etching of the first surface. Then the first protective film is removed and the second surface is etched to form a second cavity.
    Type: Grant
    Filed: May 3, 1994
    Date of Patent: January 16, 1996
    Assignee: BMC Industries, Inc.
    Inventors: Dean T. Deibler, Thomas Ratz, Peter L. Takach, Roland Thoms
  • Patent number: 5476131
    Abstract: A unitary micro-flexure structure and a method of making the same, wherein the structure takes the form of an elongate dielectric flexure body having a mounting end and a free end, and which is adapted for cantilevered disposition, wherein the body takes a form which is constructed entirely from thin-film deposition and patterning processes involving the deposition of a metal oxide, and further wherein the body has a topography which is at least partially determined by etch-removable surface-boundary-defining structure.
    Type: Grant
    Filed: December 10, 1992
    Date of Patent: December 19, 1995
    Assignee: Censtor Corporation
    Inventors: Harold J. Hamilton, Timothy W. Martin
  • Patent number: 5453347
    Abstract: A ferroelectric capacitor and method for making the same are disclosed. The ferroelectric capacitor may be constructed on a silicon substrate such as SiO.sub.2 or Si.sub.3 N.sub.4. The ferroelectric capacitor includes a bottom electrode, a layer of ferroelectric material, and a top electrode. The bottom electrode is constructed from a layer of platinum which is bonded to the silicon substrate by a layer of metallic oxide. The metallic oxide does not diffuse into the platinum; hence, a thinner layer of platinum may be utilized for the electrode. This reduces the vertical height of the capacitor and other problems associated with diffusion of the layer used to bond the bottom electrode to the substrate surface.
    Type: Grant
    Filed: June 7, 1994
    Date of Patent: September 26, 1995
    Assignee: Radiant Technologies
    Inventors: Jeff A. Bullington, Carl E. Montross, Jr., Joseph T. Evans, Jr.
  • Patent number: 5451175
    Abstract: An electronic device including a plurality of field emission devices exhibiting dis-similar electron emission characteristics wherein an aperture radius associated with each of the plurality of field emission devices determines the electron emission characteristic.
    Type: Grant
    Filed: January 6, 1994
    Date of Patent: September 19, 1995
    Assignee: Motorola, Inc.
    Inventors: Robert T. Smith, Robert C. Kane
  • Patent number: 5426071
    Abstract: A polyimide copolymer derived from 2,2-bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride, oxydiphthalic dianhydride, m-phenylene diamine and 4,4'-oxydianiline, for use as a high-temperature resistant lift-off layer in the fabrication of integrated circuit substrates.
    Type: Grant
    Filed: March 4, 1994
    Date of Patent: June 20, 1995
    Assignee: E. I. Du Pont de Nemours and Company
    Inventor: John D. Summers