Abstract: A method for patterning a metal layer includes depositing a hard mask layer on a metal layer, depositing a first patterned layer on the hard mask layer, forming a first set of sidewall spacers on sidewalls of features of the first patterned layer, forming a second set of sidewall spacers on sidewalls of the first set of sidewall spacers, removing the first set of sidewall spacers, and performing a reactive ion etching process to pattern portions of the metal layer exposed through the first patterned layer and the second set of sidewall spacers.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: Embodiments of the present disclosure generally provide a method and apparatus for forming features in a material layer utilizing EUV technologies. In one embodiment, a method of patterning a substrate includes disposing a patterned photoresist layer on a mask layer disposed on a substrate, wherein the patterned photoresist layer has openings with different widths defined in the patterned photoresist layer, forming a compensatory layer along sidewalls of the patterned photoresist layer to modify the widths of the openings and etching the mask layer through the openings with the modified width.

Abstract: The present disclosure provides methods for etching features in a silicon material includes performing a remote plasma process formed from an etching gas mixture including chlorine containing gas to remove a silicon material disposed on a substrate.

Abstract: A method for fabricating a semiconductor structure includes providing a base substrate, forming a plurality of core layers on the base substrate, forming a sidewall spacer film on the base substrate covering top and sidewall surfaces of the core layers, and forming a sidewall spacer layer by removing a portion of the sidewall spacer film formed above the top surface of the core layers. The sidewall spacer layer includes a first portion having a first thickness on the sidewall surfaces of the core layers, and a second portion having a second thickness on the base substrate. The method further includes removing the plurality of core layers after forming the sidewall spacer layer, removing the second portion of the sidewall spacer layer from the base substrate after removing the core layers, and using the first portion of the sidewall spacer layer as a hard mask layer.

Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Abstract: A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric layer over the first metal layer. The method includes forming an antireflection layer over the dielectric layer, forming a hard mask layer over the antireflection layer and forming a patterned photoresist layer over the hard mask layer. The method includes etching a portion of the antireflection layer by performing a first etching process and etching through the antireflection layer and etching a portion of the dielectric layer by performing a second etching process. The method includes etching through the dielectric layer by performing a third etching process to form a via portion on the first metal layer. The via portion includes a first sidewall and a second sidewall, and the slope of the first sidewall is different from that of the second sidewall.

Abstract: A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then forming a layer on both a cell region and a peripheral region. The methods may include forming line patterns that extend from the cell region onto the peripheral region and then forming a layer on both the cell region and a peripheral region.

Abstract: A method of manufacturing a semiconductor device includes: forming a resist separation layer on a first main surface of a SiC substrate; applying a resist retaining a shape at a temperature of 200° C. or higher on the resist separation layer; patterning the resist by photolithography; heating a stage an which the SiC substrate is placed to a temperature of 200° C. or higher by a temperature control function, and dry-etching the SiC substrate by using the patterned resist as a mask to form a via hole; and after forming the via hole, removing the resist separation layer to separate the resist from the SiC substrate.

Abstract: A method of manufacturing a semiconductor device includes: forming a resist separation layer on a first main surface of a SiC substrate; applying a resist retaining a shape at a temperature of 200° C. or higher on the resist separation layer; patterning the resist by photolithography; heating a stage an which the SiC substrate is placed to a temperature of 200° C. or higher by a temperature control function, and dry-etching the SiC substrate by using the patterned resist as a mask to form a via hole; and after forming the via hole, removing the resist separation layer to separate the resist from the SiC substrate.

Abstract: A bilayer of silicon dioxide and silicon nitride is formed on exposed surfaces of at least one semiconductor fin having a bottom source/drain region located at the footprint, and on each side, of the at least one semiconductor fin. An upper surface of each horizontal portion of the silicon nitride layer is then carbonized, and thereafter non-carbonized vertical portions of the silicon nitride layer are removed. Next, the carbonized portions of the silicon nitride layer are removed, and thereafter the vertical portions of the silicon dioxide layer are removed from sidewalls of the at least one semiconductor fin utilizing each remaining portion of the silicon nitride layer as an etch mask A bottom spacer structure is provided on each bottom source/drain region in which each bottom spacer structure includes a remaining portion of the silicon dioxide layer and the remaining portion of the silicon nitride layer.

Abstract: Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and performing a first etch on the mandrel layer, the first etch forming a first opening exposing a first portion of the substrate. The mandrel layer is masked with a second mask and a second etch is performed on the mandrel layer. The second etch forms a second opening exposing a second portion of the substrate, and also forms a protective layer on the first portion of the substrate and in the first opening.

Abstract: A substrate treatment method includes: forming a plurality of circular patterns of a resist film on a substrate; thereafter applying a first block copolymer; then phase-separating the first block copolymer into a hydrophilic polymer and a hydrophobic polymer; thereafter selectively removing the hydrophilic polymer; then selectively removing the resist film from a top of the substrate; thereafter applying a second block copolymer to the substrate; then phase-separating the second block copolymer into a hydrophilic polymer and a hydrophobic polymer; and thereafter selectively removing the hydrophilic polymer from the phase-separated second block copolymer. A ratio of a molecular weight of the hydrophilic polymer in the first block copolymer and the second block copolymer is 20% to 40%.

Abstract: Techniques herein include use of a spacer processes for patterning flows during microfabrication for creating hardmasks, features, contact openings, etc. Techniques herein include using a sidewall spacer to define a hard border between features to be patterned. Such a spacer is positioned underneath an overlying relief pattern so that a portion of the spacer is exposed and protecting an underlying layer. Techniques herein can be used for metallization, and, in particular, metallization of a first metal layer above electronic device contacts. More broadly, techniques herein can be used for any type of critical placement where one structure is extremely close to another structure, such as with sub-resolution dimensions.

Abstract: A method for ordering block copolymers including forming a first layer having a first preference mode; and providing a reactive agent in selected regions of the first layer that modifies the selected regions to a second preference mode, wherein the selected regions define other regions of the first layer retaining the first preference mode thereby forming an alignment layer for block copolymers.

Abstract: A fine-patterning method includes forming a mask layer with lower and upper mask layers on an underlying layer, forming a pair of sacrificial patterns on the mask layer, forming a connection spacer between the sacrificial patterns and first spacers that are spaced apart from each other with the pair of sacrificial patterns interposed therebetween and covering side surfaces of the sacrificial patterns, etching the upper mask layer using the first spacers and the connection spacer as an etch mask to form upper mask patterns, forming second spacers to cover side surfaces of the upper mask patterns, etching the lower mask layer using the second spacers as an etch mask to form lower mask patterns, and etching the underlying layer using the lower mask patterns as an etch mask.

Abstract: A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric layer over the first metal layer. The method includes forming an antireflection layer over the dielectric layer, forming a hard mask layer over the antireflection layer and forming a patterned photoresist layer over the hard mask layer. The method includes etching a portion of the antireflection layer by performing a first etching process and etching through the antireflection layer and etching a portion of the dielectric layer by performing a second etching process. The method includes etching through the dielectric layer by performing a third etching process to form a via portion on the first metal layer. The via portion includes a first sidewall and a second sidewall, and the slope of the first sidewall is different from that of the second sidewall.

Abstract: A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.

Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

Abstract: Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and performing a first etch on the mandrel layer, the first etch forming a first opening exposing a first portion of the substrate. The mandrel layer is masked with a second mask and a second etch is performed on the mandrel layer. The second etch forms a second opening exposing a second portion of the substrate, and also forms a protective layer on the first portion of the substrate and in the first opening.

Abstract: A fine-patterning method includes forming a mask layer with lower and upper mask layers on an underlying layer, forming a pair of sacrificial patterns on the mask layer, forming a connection spacer between the sacrificial patterns and first spacers that are spaced apart from each other with the pair of sacrificial patterns interposed therebetween and covering side surfaces of the sacrificial patterns, etching the upper mask layer using the first spacers and the connection spacer as an etch mask to form upper mask patterns, forming second spacers to cover side surfaces of the upper mask patterns, etching the lower mask layer using the second spacers as an etch mask to form lower mask patterns, and etching the underlying layer using the lower mask patterns as an etch mask.

Abstract: A method to fabricate an imprint template for bit-patterned magnetic recording media using block copolymers (BCPs) integrates data region patterning and servo region patterning. A heat sink layer is formed on the imprint substrate only in the data regions. A sublayer for the BCP is deposited over both the data regions and the servo regions and patterned to form stripes in the data regions and servo features in the servo regions. A BCP is then deposited in both the data and servo regions. Only the BCP in the data regions is heated, which causes phase separation of the BCP in the data regions into the two BCP components. The selective heating may be accomplished by directed controlled laser radiation to only the data regions. The heat sink layer below the data regions absorbs the heat from the laser radiation, confining it to the data regions.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a to-be-etched layer; and forming a hard mask layer on the to-be-etched layer. The method also includes forming a photoresist layer on the hard mask layer; and forming a patterned photoresist layer having openings exposing the hard mask layer by exposing and developing the photoresist layer. Further, the method includes forming sidewall spacers on side surfaces of the openings; and forming a patterned hard mask layer by etching the hard mask layer using the patterned photoresist layer and the sidewall spacers as an etching mask such that patterns in the hard mask layer have a substantially right angle at edge. Further, the method also includes forming to-be-etched patterns by etching the to-be-etched layer based on the patterned hard mask layer.

Abstract: The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask.

Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.

Abstract: A method for patterning a substrate is described. The patterning method may include conformally depositing a material layer over a pattern according to a conformal deposition process, selectively depositing a second material layer on an exposed surface of the material layer according to a selected deposition process recipe; partially removing the material layer using a plasma etching process to expose a top surface of the pattern, open a portion of the material layer at a bottom region between adjacent features of the pattern, and retain a remaining portion of the material layer on sidewalls of the pattern; and removing the pattern using one or more etching processes to leave a final pattern comprising the remaining portion of the material layer and the second layer.

Abstract: An etching process includes: forming a metal film on a substrate having a pattern formation region; forming a mask having a predetermined pattern on the metal film in the pattern formation region, and forming a resist film in part or all of a periphery of the pattern formation region; and dry-etching the metal film in the pattern formation region.

Abstract: A method of forming a pattern on a substrate includes forming spaced first features derived from a first lithographic patterning step. Sidewall spacers are formed on opposing sides of the first features. After forming the sidewall spacers, spaced second features derived from a second lithographic patterning step are formed. At least some of individual of the second features are laterally between and laterally spaced from immediately adjacent of the first features in at least one straight-line vertical cross-section that passes through the first and second features. After the second lithographic patterning step, all of only some of the sidewall spacers in said at least one cross-section is removed.

Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Abstract: A method fabricates a magnetic transducer. A sacrificial leading shield is provided on an etch stop layer. A nonmagnetic layer is provided on the sacrificial leading shield. A pole trench is formed in the nonmagnetic layer and on the sacrificial leading shield. A pole is formed. The pole has a bottom and a top wider than the bottom in a pole tip region. Part of the pole in the pole tip region is in the pole trench and at the ABS location. The sacrificial leading shield and part of the nonmagnetic layer adjacent to the pole are removed. An air bridge thus resides in place of the sacrificial leading shield between the portion of the pole and the etch stop layer. As least one shield layer is provided. The at least one shield layer substantially fills the air bridge and form a monolithic shield including a leading and side shields.

Abstract: A method includes forming a hydrophilic guide layer, a DBARC layer and a photoresist film. A portion of the photoresist film and DBARC layer is exposed to form exposed and unexposed portions. The unexposed photoresist film is removed to form a photoresist pattern including the exposed photoresist film portion. A neutral layer is formed on the photoresist pattern. The photoresist pattern and the DBARC layer of the exposed portion are removed to form first opening portions exposing the guide layer. A block copolymer layer includes a block copolymer having first and second polymer blocks coated on the neutral layer while filling the first opening portions. The block copolymer layer is microphase separated to form a pattern layer including first and second patterns. A pattern including one polymer block is removed to form a pattern mask. The object layer is etched to form a pattern including second opening portions.

Abstract: A method of producing plurality of etched features in an electronic device is disclosed that avoids micro-loading problems thus maintaining more uniform sidewall profiles and more uniform critical dimensions. The method comprises performing a first time-divisional plasma etch process step within a plasma chamber to a first depth of the plurality of etched features, and performing a flash process step to remove any polymers from exposed surfaces of the plurality of etched features without requiring an oxidation step. The flash process step is performed independently of the time-divisional plasma etch step. A second time-divisional plasma etch process step is performed within the plasma chamber to a second depth of the plurality of etched features. The method may be repeated until a desired etch depth is reached.

Abstract: Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.

Abstract: Disclosed and claimed herein is a template for directing a pattern in a block copolymer film and the process of making the pattern.

Abstract: Methods for fabrication of nanopillar field effect transistors are described. These transistors can have high height-to-width aspect ratios and be CMOS compatible. Silicon nitride may be used as a masking material. These transistors have a variety of applications, for example they can be used for molecular sensing if the nanopillar has a functionalized layer contacted to the gate electrode. The functional layer can bind molecules, causing an electrical signal in the transistor.

Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.

Abstract: A method of forming a pattern includes forming a plurality of target patterns, forming a plurality of pitch violating patterns that make contact with the plurality of target patterns and are disposed between the plurality of target patterns, classifying the plurality of pitch violating patterns into a first region and a second region adjacent to the first region, and forming an initial pattern corresponding to one of the first region and the second region.

Abstract: The present disclosure provides a TFET, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; a gate stack formed on the channel region, wherein the gate stack comprises: a gate dielectric layer, and at least a first gate electrode and a second gate electrode distributed in a direction from the source region to the drain region and formed on the gate dielectric layer, and the first gate electrode and the second gate electrode have different work functions; and a first side wall and a second side wall formed on a side of the first gate electrode and on a side of the second gate electrode respectively.

Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.

Abstract: A combination of two lithographically patterned mandrels can be employed in conjunction with sidewall spacers to provide two spacers. The two spacers may intersect each other and/or contact sidewall surfaces of each other to provide a thickness that is a sum of the thicknesses of the two spacers. Further, the two spacers may be patterned to provide various patterns. In addition, portions of at least one of the two spacers may be etched employing an etch mask. Additionally or alternately, an additional material may be selectively added to portions of one of the two spacers.

Abstract: A disclosed mask pattern forming method includes isotropically coating a surface of a resist pattern array having a predetermined line width with a silicon oxide film, embedding a gap in the resist pattern array coated by the silicon oxide film with a carbon film, removing the carbon film from the upper portion and etching back the carbon film while leaving the carbon film within the gap in any order, removing the remaining carbon film and etching back the upper portion of the resist pattern array to have a predetermined film thickness in any order, and forming a first mask pattern array which has a center portion having a predetermined width and film sidewall portions sandwiching the predetermined width, and arranged interposing a space width substantially the same as the predetermined line width with an asking process provided to the resist pattern array exposed from the removed silicon oxide film.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.

Abstract: In one embodiment, a pattern forming method includes forming a physical guide that includes a first pattern in a first region and a second pattern in a second region on an underlying film, embedding a polymer material into a concave portion of the physical guide, microphase-separating the polymer material, to form a self-assembly pattern having a first and a second polymer sections, observing the self-assembly pattern in the second region, to determine from an observation result whether or not the self-assembly pattern in the first region has a predetermined shape, and selectively removing the first polymer section in the case of determining that the self-assembly pattern in the first region has the predetermined shape. The second pattern includes a pattern with a larger coverage ratio than the first pattern and a pattern with a smaller coverage ratio than the first pattern.

Abstract: A method of forming a semiconductor memory device includes forming an etch target layer on a substrate, forming a sacrificial layer having preliminary openings on the etch target layer, forming assistance spacers in the preliminary openings, respectively, removing the sacrificial layer, such that the assistance spacers remain on the etch target layer, forming first mask spacers covering inner sidewalls of the assistance spacers, respectively, the first mask spacers respectively defining first openings, forming a second mask spacer covering outer sidewalls of the assistance spacers, the second mask spacer defining second openings between the first openings, the first and second openings being adjacent to each other along a first direction, and etching the etch target layer exposed by the first openings and the second openings to form holes in the etch target layer.

Abstract: A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.

Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.

Abstract: Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.

Abstract: A method for manufacturing a nozzle and an associated funnel in a single plate comprises providing the single plate, the plate being etchable; providing an etch resistant mask on the plate, the mask having a pattern, wherein the pattern comprises a first pattern part for etching the nozzle and a second pattern part for etching the funnel; covering one of the first pattern part and the second pattern part using a first cover; etching one of the nozzle and funnel corresponding to the pattern part not covered in step (c); removing the first cover; etching the other one of the nozzle and funnel; and removing the etch resistant mask.

Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.