Abstract: A method for forming a fine pattern of a semiconductor device includes forming a photoresist pattern over a semiconductor substrate including an underlying layer. A cross-linking layer is formed on the sidewall of the photoresist pattern. The photoresist pattern is then removed to form a fine pattern comprising the cross-linking layer. The underlying layer is etched using the fine pattern as an etching mask. As a result, the underlying layer has a smaller size than a minimum pitch.

Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).

Abstract: An object of this invention is to provide a manufacturing method that, by using a general-purpose semiconductor fabrication process, can easily manufacture an ink jet print head in which energy generating elements are complicatedly installed in the ink path. To this end, the present invention comprising steps of providing a substrate having a removal projected portion, forming an energy generating element along the projected portion, forming a supporting member on the energy generating element, and forming a ink chamber by removing the projected portion from the substrate.

Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the

Abstract: A Method. The method includes forming a substructure, on a substrate, including a feature having a sidewall of a first material and a bottom surface of a second material. Applying a solution including two immiscible polymers and third material to the substructure. The immiscible polymers include a first and second polymer. A selective chemical affinity of the first polymer for the material is greater than a selective chemical affinity of the second polymer for the material. The first polymer is segregated from the second polymer. The first polymer selectively migrates to the at least one sidewall, resulting in the first polymer being disposed between the at least one sidewall and the second polymer. The first polymer is selectively removed. The second polymer remains, resulting in forming structures including the substructure, the third material, and the second polymer. The substructure has a pattern. The pattern is transferred to the substrate.

Abstract: A method realizes a multispacer structure including an array of spacers having same height. The method includes realizing, on a substrate, a sacrificial layer of a first material; b) realizing, on the sacrificial layer, a sequence of mask spacers obtained by SnPT, which are alternately obtained in at least two different materials; c) chemically etching one of the two different materials with selective removal of the mask spacers of this etched material and partial exposure of the sacrificial layer; d) chemically and/or anisotropically etching the first material with selective removal of the exposed portions of the sacrificial layer; e) chemically etching the other one of the two different materials with selective removal of the mask spacers of this etched material and obtainment of the multispacer structure.

Abstract: To form an isolation structure in a semiconductor substrate, at least two trenches are formed with a rib therebetween in the semiconductor substrate, and then the semiconductor material in the area of the trenches and particularly the rib is converted to an electrically insulating material. For example, this is accomplished by thermal oxidation of silicon semiconductor material of the rib.

Abstract: A method of correcting for pattern run out in a desired pattern in directional deposition or etching comprising the steps of providing a test substrate; providing a stencil of known thickness on the test substrate; providing a stencil pattern extending through the stencil to the test substrate.

Abstract: One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.

Abstract: A method for removing a damaged dielectric material following an etch process, an ashing process, or a wet cleaning process is described. A dry, non-plasma removal process is implemented to remove a thin layer of damaged material on a feature following formation of the feature. The dry, non-plasma removal process includes a chemical treatment of the damaged material, followed by a thermal treatment of the chemically treated surface layer. The two steps, chemical and thermal treatment, can be repeated.

Abstract: A process for forming a three-dimensional photonic crystal comprises the steps of providing a base material having a first face and a second face adjoining to each other at a first angle, forming a first mask on the first face, dry-etching the first face in a direction at a second angle to the first face to remove a portion of the base material not protected by the first mask, forming a second mask on the second face, and dry-etching the second face in a direction at a third angle to the second face to remove a portion of the base material not protected by the second mask.

Abstract: A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.

Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have irregular profiles along depths of the photoresist features. The irregular profiles along the depths of the photoresist features of the sidewalls of the photoresist features are corrected comprising at least one cycle, where each cycle comprises a sidewall deposition phase and a profile shaping phase. Feature is etched into the etch layer through the photoresist features. The mask is removed.

Abstract: According to one embodiment, a method of forming patterns is provided, in which the method including forming a resist on an underlying material, pressing a stamper having patterns of protrusions and recesses, sidewalls of which protrusions are tapered, onto the resist to form a patterned resist having patterns of protrusions and recesses, sidewalls of which protrusions are tapered, forming a protective film on the patterned resist, performing anisotropic etching to leave the protective film on the tapered sidewalls of protrusions of the patterned resist, etching a resist residue remaining in recesses of the patterned resist using the protective film as a mask, and etching the underlying material using the protective film and the patterned resist as a mask.

Abstract: We have developed an uncomplicated method of plasma etching deeply recessed features such as deep trenches, of at least 5 ?m in depth, in a silicon-containing substrate, in a manner which generates smooth sidewalls, having a roughness of less than about 1 ?m, typically less than about 500 nm, and even more typically between about 100 nm and 20 nm. Features having a sidewall taper angle, relative to an underlying substrate, typically ranges from about 85° to about 92° and exhibiting the smooth sidewalls are produced by the method. In one embodiment, a stabilizing etchant species is used constantly during the plasma etch process, while at least one other etchant species and at least one polymer depositing species are applied intermittently, typically periodically, relative to each other. In another embodiment, the stabilizing etchant species is used constantly and a mixture of the other etchant species and polymer depositing species is used intermittently.

Abstract: An object to be processed has a chromium-based thin film made of a material containing chromium. The thin film is etched using a resist pattern as a mask. The thin film is etched by the use of a chemical species produced by preparing a dry etching gas containing a halogen-containing gas and an oxygen-containing gas and supplying a plasma excitation power to the dry etching gas to thereby excite plasma. The thin film is etched using, as the plasma excitation power, a power lower than a plasma excitation power at which plasma density jump occurs.

Abstract: In a dry etching method in which clusters formed by agglomeration of atoms or molecules are ionized and accelerated as a cluster ion beam for irradiation of an object surface to etch away therefrom its constituent atoms, the clusters are mixed clusters 42 formed by agglomeration of two or more kinds of atoms or molecules, and the mixed clusters 42 contain atoms 43 of at least one of argon, neon, xenon and krypton, and a component 44 that is deposited on the object surface to form a thin film by reaction therewith. With this method, it is possible to provide an extremely reduced sidewall surface roughness and high vertical machining accuracy.

Abstract: An MEMS sensor of the present invention includes a substrate, a lower thin film provided on a surface of the substrate, an upper thin film opposed to the lower thin film at an interval on the side opposite to the substrate, and a wall portion surrounding the lower thin film and the upper thin film and protruding on the side opposite to the lower thin film with respect to the upper thin film.

Abstract: A method suitable for etching hydrophilic trenches into a substrate, such as silicon, is provided. The method comprises etching and sidewall passivation processes for achieving anisotropy. Sidewalls of the etched trench are made hydrophilic during the etch by virtue of a hydrophilizing dopant in a passivating gas plasma. The method is useful for etching ink supply channels in inkjet printheads.

Abstract: A method is proposed which will enable cavities having optically transparent walls to be produced simply and cost-effectively in a component by using standard methods of microsystems technology. For this purpose, a silicon region is first produced, which is surrounded on all sides by at least one optically transparent cladding layer. At least one opening is then produced in the cladding layer. Over this opening, the silicon surrounded by the cladding layer is dissolved out, forming a cavity within the cladding layer. In this context, the cladding layer acts as an etch barrier layer.

Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.

Abstract: Disclosed are methods and systems of etching copper containing materials so that they have smooth and/or planar surface. In this connection, the systems and methods employ two different solutions to accomplish the etching. The first solution oxidizes the surface of the copper containing material and forms a passivating film. The second solution removes the passivating film in a controlable manner.

Abstract: Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction.

Abstract: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and controlled to isotropically contact particular regions of the inorganic material to allow for trimming and control of a critical dimension associated with the inorganic material.

Abstract: Methods for fabricating sublithographic, nanoscale linear microchannel arrays over surfaces without defined features utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the methods use a multilayer induced ordering approach to align lamellar films to an underlying base film within trenches, and localized heating to anneal the lamellar-phase block copolymer film overlying the trenches and outwardly over the remaining surface.

Abstract: A multilayer antireflective hard mask structure is disclosed. The structure comprises: (a) a CVD organic layer, wherein the CVD organic layer comprises carbon and hydrogen; and (b) a dielectric layer over the CVD organic layer. The dielectric layer is preferably a silicon oxynitride layer, while the CVD organic layer preferably comprises 70-80% carbon, 10-20% hydrogen and 5-15% nitrogen. Also disclosed are methods of forming and trimming such a multilayer antireflective hard mask structure. Further disclosed are methods of etching a substrate structure using a mask structure that contains a CVD organic layer and optionally has a dielectric layer over the CVD organic layer.

Abstract: A method for sidewall etching includes providing a substrate having a trench defined therein, with the trench having fill material disposed over a bottom thereof, along a sidewall thereof, and at the trench opening. The fill material along the sidewall of the trench and at the trench opening is removed without removing the fill material disposed over the bottom of the trench. The fill material along the sidewall and at the trench opening may be removed without removing the fill material disposed over the bottom of the trench by inhibiting a reaction between an etchant and the fill material over the bottom of the trench. The reaction between the etchant and the fill material may be inhibited by causing an air bubble to form at the bottom of the trench. The air bubble may be formed by inverting the substrate, and immersing the inverted substrate in an etchant.

Abstract: An etching method for forming a recess (220) having an opening dimension (R) of millimeter order in an object (212) to be etched such as a semiconductor wafer. A mask (214) having an opening corresponding to the recess (220) is formed on the object (212). The object (212) with the mask (214) is placed in a processing vessel for plasma etching and etched in it using a plasma. The material of the portion around the opening of the mask (214) is the same as the material, for example, silicon of the object (212). Hence, the recess (220) can be so formed as not to form a sub-trench shape (a shape formed by etching the periphery of which is deeper than the center) substantially in the bottom (222).

Abstract: The present invention provides a phase shift mask and fabricating method thereof, by which a critical dimension of a semiconductor pattern can be accurately formed in a manner of compensating a boundary step difference between an active area and an insulating layer. The present invention includes a transparent substrate and at least two halftone layers on the transparent substrate to have light transmittance lower than that of the transparent substrate, each comprising front and rear parts differing in thickness from each other.

Abstract: In a method of forming a patterned thin film, first, an etching stopper film and a film to be patterned are formed in this order on a base layer. Next, a patterned first film is formed on the film to be patterned. Next, a second film is formed over an entire surface on top of the film to be patterned and the first film. Then, by removing the first film, an etching mask is obtained from the second film formed on the film to be patterned. The film to be patterned is selectively etched through dry etching using the etching mask. A patterned thin film having a groove is thereby obtained.

Abstract: A selective etching method with lateral protection function is provided. The steps includes: (a) providing a substrate; (b) forming a plurality of tunnels; (c) forming a lateral strengthening structure at a peripheral wall of the tunnels; (d) removing a bottom portion of the lateral strengthening structure, and a part of the substrate by an etching process so as to form a lower structure and expose an unstrengthened structure; and (f) etching the unstrengthened structure laterally so as to form an upper structure.

Abstract: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

Abstract: According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated into the substrate regions not covered by the masking layer (6). A heat treatment is used to diffuse the substance into a substrate region covered by the masking layer (6) such that a concentration gradient of the substance is created in the substrate region covered by the masking layer (6), proceeding from the edge of the masking layer (6) inward with increasing distance from the edge. The masking layer (6) is then removed to expose the substrate region under this layer, and a near-surface layer of the substrate (3) in the exposed substrate region is converted by a chemical conversion reaction into a coating (9) which has a layer thickness profile corresponding to the concentration gradient of the substance contained in this near-surface layer.

Abstract: An etching method for forming a recess (220) having an opening dimension (R) of millimeter order in an object (212) to be etched such as a semiconductor wafer. A mask (214) having an opening corresponding to the recess (220) is formed on the object (212). The object (212) with the mask (214) is placed in a processing vessel for plasma etching and etched in it using a plasma. The material of the portion around the opening of the mask (214) is the same as the material, for example, silicon of the object (212). Hence, the recess (220) can be so formed as not to form a sub-trench shape (a shape formed by etching the periphery of which is deeper than the center) substantially in the bottom (222).

Abstract: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.

Abstract: A method and structure for reducing optical signal loss in a silicon waveguide formed within a silicon-on-insulator (SOI) structure uses CMOS processing techniques to round the edges/corners of the silicon material along the extent of the waveguiding region. One exemplary set of processes utilizes an additional, sacrificial silicon layer that is subsequently etched to form silicon sidewall fillets along the optical waveguide, the fillets thus “rounding” the edges of the waveguide. Alternatively, the sacrificial silicon layer can be oxidized to consume a portion of the underlying silicon waveguide layer, also rounding the edges. Instead of using a sacrificial silicon layer, an oxidation-resistant layer may be patterned over a blanket silicon layer, the pattern defined to protect the optical waveguiding region.

Abstract: New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Compensation for etching-related structural artifacts can be accomplished by proper use of such an etching delay layer.

Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

Abstract: The invention concerns a piezoelectric resonator piece of a piezoelectric resonator having electrode patterns for forming exciting electrodes each of which is composed of an under a metal layer. Each of the electrode patterns for forming conduction electrodes is composed of the under metal layer except the curved or bent portions of the sides of the piezoelectric resonator piece and each of the electrode patterns in these portions are composed of the under metal layer and a gold electrode layer. It is thus possible to provide a piezoelectric resonator in which, even when noble metal layers are partially removed for increasing adhesion of surface protecting films, exciting electrodes are not brought into an open state between the upper side and the lower side of a piezoelectric resonator piece.

Abstract: A method for manufacturing a liquid jet recording head having an element substrate provided with a plurality of discharge energy generating elements for applying discharging energy to a recording liquid in accordance with image data, a liquid chamber for storing the recording liquid, and a top plate having a plurality of nozzles, is provided. The method includes a step of forming, on an anisotropic-etching mask layer provided on a nozzle surface of the top plate, compensation patterns extending to a liquid chamber region in order to form the nozzles and the liquid chamber by anisotropic etching, and a step of performing anisotropic etching of the top plate through the mask layer and forming the liquid chamber to have a substantially rectangular shape at the nozzle surface of the top plate by over-etching portions with the compensation patterns.

Abstract: A method is provided for forming sub-micron-size structures over a substrate. A width-defining step is formed over the substrate. A width-defining layer is formed over an edge of the width-defining step. The width-defining layer is etched back to leave a spacer adjacent the width-defining step. A length-defining step is formed over the substrate. A length-defining layer is formed over an edge of the length-defining step. The length-defining layer is etched back to leave a spacer adjacent a first edge of the length-defining step and across a first portion of the spacer left by the width-defining layer. The length-defining step is then removed. The spacer left by the width-defining layer is then etched with the spacer left by the length-defining layer serving as a mask, to form the structure.

Abstract: In one embodiment, a semiconductor device processing method, comprising the steps of: (a) using a patterned photoresist to form a structure having at least one edge; (b) prior to removal of the photoresist, forming a conforming layer from an organic compound and patterning the conforming layer to form at least one sidewall spacer which are self-aligned to the at least one edge; (c) performing a processing operation which is at least partially localized by the at least one sidewall spacer; and (d) removing the at least one sidewall spacer and the photoresist, wherein the conforming layer is formed via deposition of at least one organic compound selected from C1 to C8 alkanes C2 to C8 alkenes, C3 to C8 cyclo-alkenes, C4 to C8 cyclo-alkenes, C1 to C8 fluoro-alkanes, C2 to C8 fluoro-alkenes, C3 to C8 cyclofluoro-alkanes, C4 to C8 cyclofluoro-alkenes, or mixtures thereof.

Abstract: A film of hardly-etched material formed on a substrate is etched using a mask formed on the film of hardly-etched material and a plasma, wherein the film of hardly-etched material is etched using the mask formed with a side wall angled at 90 degrees or less with respect to the surface of the substrate, thereby forming the etched film with a taper angle to the surface of the substrate equal to or larger than the taper angle of the mask.

Abstract: The present disclosure pertains to our discovery of a method of etching a shaped cavity in a substrate, where the shaped cavity has a width that is at least as great as its depth. We have discovered that by varying the process chamber pressure during etching of the shaped cavity, we can control lateral etching of the shaped cavity, while allowing the removal of etch process byproducts from the shaped cavity during continued etching. The method of the invention can be used to etch shaped cavities having round or horizontal elliptical shapes. The method of the invention is particularly useful in the etching of buried cavities, where removal of etch byproducts from the cavity can be difficult.

Abstract: The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes.

Abstract: A method for patterning different types of surface features on a semiconductor substrate (e.g. metal pads, etched pits and grooves) where the features are accurately located by a single mask. First, a dielectric layer is formed on the substrate. Next, an etch-resistant metal layer is formed on the dielectric and patterned according to a mask. Then, a patterned resist mask (e.g. PMMA) is formed on the patterned metal so that areas of the dielectric are exposed. The resist mask has edges that lie on top of the patterned metal layer. Therefore, the exposed dielectric areas are bounded by patterned metal. Then, the dielectric layer is etched using a directional dry etch to expose the underlying semiconductor substrate. Then, the semiconductor substrate is etched. The dielectric layer functions as a mask in the substrate etching step. Since the metal pattern determines the areas of the substrate that are etched, all the features are located according to the original mask that defined the metal pattern.

Abstract: A method of etching a silicon-containing material in a substrate comprises placing the substrate in a process chamber and exposing the substrate to an energized gas comprising fluorine-containing gas, chlorine-containing gas and sidewall-passivation gas. The silicon-containing material on the substrate comprises regions having different compositions, and the volumetric flow ratio of the fluorine-containing gas, chlorine-containing gas, and sidewall-passivation gas is selected to etch the compositionally different regions at substantially similar etch rates.

Abstract: A method for etching an organic anti-reflective coating (ARC) layer on a substrate in a plasma processing system comprising: introducing a process gas comprising ammonia (NH3), and a passivation gas; forming a plasma from the process gas; and exposing the substrate to the plasma. The process gas can, for example, constitute NH3 and a hydrocarbon gas such as at least one of C2H4, CH4, C2H2, C2H6, C3H4, C3H6, C3H8, C4H6, C4H8, C4H10, C5H8, C5H10, C6H6, C6H10, and C6H12. Additionally, the process chemistry can further comprise the addition of helium. The present invention further presents a method for forming a bilayer mask for etching a thin film on a substrate, wherein the method comprises: forming the thin film on the substrate; forming an ARC layer on the thin film; forming a photoresist pattern on the ARC layer; and transferring the photoresist pattern to the ARC layer with an etch process using a process gas comprising ammonia (NH3), and a passivation gas.

Abstract: A method for forming many microlenses comparatively easily and effectively is provided. On one end of an optical substrate is formed a plurality of lens planes at regular intervals. Lens areas containing the lens planes are partially covered by an etching mask and etching processing is performed on areas being exposed outside the etching mask to remove the areas to a specified depth. While the lens planes formed on one surface of the optical substrate are being held by a support substrate, polishing processing is performed on another end face of the optical substrate and each microlens formed in the lens areas is separated from the support substrate.

Abstract: The invention relates to a method for trench etching, in particular a method for anisotropic deep trench (DT) etching in an Si substrate by plasma dry etching, such as reactive ion etching (RIE), magnetically enhanced RIE or inductively coupled plasma etching (ICP), and sidewall passivation of the etched trenches in the Si substrate, the Si substrate being provided with an etching mask before the beginning of the etching operation. The invention is intended to provide a method for depth etching which, with a low outlay, makes it possible to achieve a significantly larger etching depth at higher speed and which enables a further reduction of the structure widths without any difficulty.