Abstract: A gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus is provided. The gas distribution system can include a gas supply section, a flow control section and a switching section. The gas supply section provides first and second gases, typically gas mixtures, to the flow control section, which controls the flows of the first and second gases to the chamber. The chamber can include multiple zones, and the flow control section can supply the first and second gases to the multiple zones at desired flow ratios of the gases. The gas distribution system can continuously supply the first and second gases to the switching section and the switching section is operable to switch the flows of the first and second gases, such that one of the first and second process gases is supplied to the chamber while the other of the first and second gases is supplied to a by-pass line, and then to switch the gas flows.

Abstract: A method includes applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with the substrate and projecting upwardly from a surface of the substrate, and etching the surface of the substrate so as to leave second microcontact portions below the first microcontact portions and integral therewith, the final etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step. A microelectronic unit includes a substrate, and a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region remote from the substrate, each microcontact having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract: A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species.

Abstract: A method for forming a deep trench includes providing a substrate with a bottom layer and a top layer; performing a first etching process to etch the top layer, the bottom layer and the substrate so as to form a recess; selectively depositing a liner covering the top layer, the bottom layer and part of the substrate in the recess; using the liner as an etching mask to perform a second dry etching to etch the recess unmasked by the liner so as to form a deep trench; performing a selective wet etching to remove the top layer; and performing a post wet etching to enlarge the deep trench.

Abstract: A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.

Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Abstract: A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.

Abstract: A method of processing a substrate having a processing target layer and an organic film serving as a mask layer includes a mineralizing process of mineralizing the organic film. The mineralizing process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto a surface of the organic film; and an oxidation process for oxidizing the adsorbed silicon-containing gas to be converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.

Abstract: A pattern forming method including: (a) forming a porous layer above an etching target layer; (b) forming an organic material with a transferred pattern on the porous layer; (c) forming, by use of the transferred pattern, a processed pattern in a transfer oxide film that is more resistant to etching than the porous layer; and (d) transferring the processed pattern to the etching target layer by use of the transfer oxide film as a mask.

Abstract: A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature.

Abstract: In the present invention, provided is a method of forming a mask pattern by which a fine thin film pattern may be formed more easily with higher resolution and precision. In the method of forming a mask pattern, a photoresist pattern having an opening is formed on a substrate, then, an inorganic film is formed so as to cover the upper surface of the photoresist pattern and the inside of the opening, then the inorganic film on the upper surface of the photoresist pattern is removed by a dry etching process. Subsequently, an inorganic mask pattern is formed by removing the photoresist pattern. The inorganic mask pattern thus formed hardly produces an issue of deformation such as physical displacement even when it is heated in the dry etching process.

Abstract: A substrate processing method is provided to process a substrate having a structure in which a lower photoresist layer, a hard mask layer containing silicon, and an upper photoresist layer are sequentially formed on a target layer to be processed. The substrate processing method includes reducing by using a plasma a width of a first opening formed in the upper photoresist layer, so that the hard mask layer is exposed; reducing by using a plasma a width of a second opening formed in the hard mask layer through the first opening having the reduced width so that the lower photoresist layer is exposed; forming a third opening through the second opening having the reduced width so that the target layer is exposed; and a third width reducing step of reducing a width of the third opening by using a plasma.

Abstract: A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist.

Abstract: In anisotropic etching of the substrates, ultra-thin and conformable layers of materials can be used to passivate sidewalls of the etched features. Such a sidewall passivation layer may be a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. Alternatively, the sidewall passivation layer may be an inorganic-based material deposited using Atomic Layer Deposition (ALD) method. SAM or ALD s layer deposition can be carried out in a pulsing regime alternating with sputtering and/or etching processes using process gasses with or without plasma. Alternatively, SAM deposition is carried out continuously, while etch or sputtering turns on in a pulsing regime. Alternatively, SAM deposition and etch or sputtering may be carried out continuously.

Abstract: In a metal processing method, a photoresist liquid is applied to both surfaces of a metal plate (210) to form photoresist films (220, 230), respectively (Step S102). Subsequently, the photoresist films (220, 230) are exposed and developed so that the photoresist films (220, 230) is removed while leaving the photoresist films (220, 230) corresponding to portions in which a hole is to be formed (Step S103). Next, metal thin films (240, 250) are formed on both the surfaces of the metal plate (210), respectively, on which the photoresist films (220, 230) are formed (Step S104). Subsequently, the photoresist films (220, 230) are removed, and metal thin films (245, 255) are also removed, which are formed on the photoresist films (220, 230), respectively (Step S105). Finally, the metal plate (210) is immersed in an etchant to be etched, to thereby form a high-precision hole in the metal plate (210) (Step S106).

Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.

Abstract: A micro-lens array and a method for fabricating a micro-lens includes forming a first lens formation material layer on and/or over a micro-lens formation area of a semiconductor substrate, and then forming a portion of the lens formation material layer as a first micro-lens using a first mask. A second lens formation material layer is formed adjacent to the first micro-lens on and/or over the micro-lens formation area. The second lens formation material layer is also formed as a second micro-lens using a second mask which is a different type from that of the first mask.

Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.

Abstract: A method and system provide a magnetoresistive structure from a magnetoresistive stack that includes a plurality of layers. The method and system include providing a mask that exposes a portion of the magnetoresistive stack. The mask has at least one side, a top, and a base at least as wide as the top. The method and system also include removing the portion of the magnetoresistive stack to define the magnetoresistive structure. The method and system further include providing an insulating layer. A portion of the insulating layer resides on the at least one side of the mask. The method and system further include removing the portion of the insulating layer on the at least one side of the mask and removing the mask.

Abstract: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.

Abstract: A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask and

Abstract: Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.

Abstract: A substrate processing method for processing a substrate, on which a processing target layer, an intermediate layer, and a mask layer having an opening to expose a part of the intermediate layer are stacked in this order, includes a shrink etching step. In the shrink etching step, an opening width of the opening of the mask layer is reduced by depositing deposits on a sidewall surface thereof by a plasma generated from a gaseous mixture of depositive gas expressed by a general formula CxHyFz (x, y and z being positive integers) and SF6 gas. Also, there is formed in the intermediate layer an opening having an opening width corresponding to the reduced opening width of the opening of the mask layer by etching the intermediate layer.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a mask material on a semiconductor substrate comprising first and second regions; forming a pattern of a core on the mask material in the first region; forming a sidewall spacer mask on a side surfaces of the core pattern and subsequently removing the core pattern; transferring a pattern of the sidewall spacer mask to the mask material in the first region after removing the core; and thereafter, carrying out trimming of the pattern of the sidewall spacer mask which is transferred to the mask material in the first region, and formation of a predetermined pattern on the mask material in the second region, simultaneously.

Abstract: A method of forming fine patterns of a semiconductor device is provided. The method includes forming plural preliminary first mask patterns, which are spaced apart from each other by a first distance in a direction parallel to a surface of a substrate, on the substrate; forming an acid solution layer on the substrate to cover the plural preliminary first mask patterns; forming plural first mask patterns which are spaced apart from each other by a second distance larger than the first distance, of which upper and side portions are surrounded by acid diffusion regions having first solubility; exposing the first acid diffusion regions by removing the acid solution layer; forming a second mask layer having second solubility lower than the first solubility in spaces between the acid diffusion regions; and forming plural second mask patterns located between the plural first mask patterns, respectively, by removing the acid diffusion regions by the dissolvent.

Abstract: Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In one embodiment, a method comprises the steps of forming etch masking features overlying the semiconductor substrate, the etch masking features having a first thickness, and forming an etch barrier layer overlying the substrate, the etch barrier layer having a second thickness less than or substantially equal to the first thickness. The method also comprises removing the etch masking features to expose the substrate, and etching the substrate using the etch barrier layer as an etch mask.

Abstract: A method of forming side spacers upwardly extending from a substrate, includes: providing a template constituted by a photoresist formed on and in contact with an etch-selective layer laminated on a substrate; anisotropically etching the template in a thickness direction with an oxygen-containing plasma to remove a footing of the photoresist and an exposed portion of the underlying layer; depositing a spacer film on the template by atomic layer deposition (ALD); and forming side spacers using the spacer film by etching. The etch-selective layer has a substantially lower etch rate than that of the photoresist.

Abstract: A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.

Abstract: A metal interconnect structure, which includes a bond pad, an overlying anti-reflective coating layer, an overlying passivation layer, and an opening that exposes a top surface of the bond pad, eliminates corrosion resulting from the anti-reflective layer being exposed to moisture during reliability testing by utilizing a side wall spacer in the opening that touches the side wall of the passivation layer, the side wall of the anti-reflective coating layer, and the top surface of the bond pad.

Abstract: A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.

Abstract: The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.

Abstract: Methods are provided for fabricating an electronic device having at least one sidewall spacer formed adjacent a selected surface. In one embodiment, the method includes the step of depositing spacer material adjacent first and second raised structures formed on the substrate and extending along substantially perpendicular axes. The method further includes the step of selectively removing spacer material laterally adjacent one of the first raised structure and the second raised structure. During the step of selectively removing, the electronic device is bombarded with ions from a first predetermined direction forming a first predetermined grazing angle with the substrate such that the spacer material adjacent a first sidewall of the first raised structure is substantially exposed to the ion bombardment while the spacer material adjacent opposing sidewalls of the second raised structure is substantially shielded therefrom.

Abstract: An edge-sealed barrier film composite. The composite includes a substrate and at least one initial barrier stack adjacent to the substrate. The at least one initial barrier stack includes at least one decoupling layer and at least one barrier layer. One of the barrier layers has an area greater than the area of one of the decoupling layers. The decoupling layer is sealed by the first barrier layer within the area of barrier material. An edge-sealed, encapsulated environmentally sensitive device is provided. A method of making the edge-sealed barrier film composite is also provided.

Abstract: A method in the fabrication of a semiconductor device simultaneously forms different patterns on the same level of the device. The device has a first area and a second area. A low density mask pattern of at least one relatively wide topographic feature is formed on the second area, a plurality of relatively narrow topographic features is formed on the first area, first spacers are formed on side walls of the narrow topographic features in the first area, the relatively narrow topographic features are removed, and the patterns of the first spacers and the relatively wide topographic feature(s) are simultaneously transcribed in the first and second areas, respectively.

Abstract: Disclosed is a method of etching a substrate having a layered structure in which a photoresist mask with a pattern, a coating film made of silicon oxide, and an organic film are laminated in that order from the top. Before etching the coating film of silicon oxide, a deposit is deposited on the photoresist mask by using plasma generated from a hydrocarbon gas such as CH4 gas so as to narrow the size of openings in the pattern of the photoresist mask. The pattern of the photoresist mask is well transferred to the organic film through the coating film, and a pattern with openings having a high aspect ratio can be formed in the organic film and toppling of the pattern in the organic film can be prevented. The organic film with the transferred pattern is used as an etch mask for etching the underlying layer.

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns.

Abstract: Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes.

Abstract: A mask for performing high speed media finishing on airfoils includes a thicker portion and a thinner portion. The thicker portion is spaced further from an edge that will become a leading edge in the final airfoil than the thinner portion. The media is redirected by the thicker portion toward the edge where the finishing is to occur.

Abstract: A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios.

Abstract: A microfluidic device for nucleic acid analysis includes a monolithic semiconductor body (13), a microfluidic circuit (10), at least partially accommodated in the monolithic semiconductor body (13), and a micropump (11). The microfluidic circuit (10) includes a sample preparation channel (18) formed on the monolithic semiconductor body (13) and at least one microfluidic channel (20, 22) buried in the monolithic semiconductor body (13). The micropump (11), includes a plurality of sealed chambers (40) provided with respective openable sealing elements (41) and having a first pressure therein that is different from a second pressure in the microfluidic circuit (10). In addition, the micropump (11) and the microfluidic circuit (10) are configured so that opening the openable sealing elements (41) provides fluidic coupling between the respective chambers (40) and the microfluidic circuit (10). The openable sealing elements (41) are integrated in the monolithic semiconductor body (13).

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a core material on a workpiece; forming a coating film comprising an amorphous material so as to cover an upper surface and side faces of the core material; crystallizing the coating film by applying heat treatment; forming a sidewall mask by removing the crystallized coating film while leaving a portion thereof located on the side faces of the core material; removing the core material after forming the sidewall mask; and etching the workpiece using the sidewall mask as a mask after removing the core material.

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region.

Abstract: The method of manufacturing a nozzle plate which includes a nozzle having a tapered section and a linear section includes the steps of: forming an etching stopper layer for stopping dry etching of a silicon substrate, on a first surface of the silicon substrate; forming a mask layer on a second surface of the silicon substrate reverse to the first surface; performing a first patterning process with respect to the mask layer so that an opening section is formed in the mask layer; carrying out the dry etching of the silicon substrate through the opening section in the mask layer so that the tapered section of the nozzle is formed in the silicon substrate; carrying out dry etching of the etching stopper layer through the opening section in the mask layer so that at least a part of the linear section of the nozzle is formed in the etching stopper layer; and removing the mask layer.

Abstract: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.

Abstract: A semiconductor fabricating process is provided. First, a substrate is provided. The substrate has thereon a stacked structure and a mask layer disposed on the stacked structure. Thereafter, an oxide layer is formed on a surface of the mask layer and a surface of at least a portion of the stacked structure. Afterwards, a first spacer is formed on a sidewall of the stacked structure. Then, a second spacer is formed on a sidewall of the first spacer. Further, a first etching process is performed to remove the oxide layer on the surface of the mask layer. Thereafter, a second etching process is performed to simultaneously remove the mask layer and the second spacer.

Abstract: For integrated circuit fabrication, at least one spacer support structure is formed in a first area over a semiconductor substrate, and a mask material is deposited on exposed surfaces of the spacer support structure and on a second area over the semiconductor substrate. A masking structure is formed on a portion of the mask material in the second area, and the mask material is patterned to form spacers on sidewalls of the spacer support structure and to form a mask pattern under the masking structure. The spacer support structure and the masking structure are comprised of respective high carbon content materials that have been spin-coated and have substantially a same etch selectivity.

Abstract: A method and apparatus is provided for controlling the etch profile of a multilayer layer stack by depositing a first and second material layer with differential etch rates in the same or different processing chamber.

Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.