Nongaseous Phase Etching Patents (Class 216/53)
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Patent number: 6387285Abstract: It is an object of a method of manufacturing a thin-film magnetic head of the invention to improve the insulating property between an electrode connected to a magnetoresistive element and a shield layer without increasing the thickness of an insulating layer between the magnetoresistive element and the shield layer. In the method, a pair of conductive layers to be the electrode (lead) connected to the MR element are formed on an insulating layer. Magnetic layers are formed to surround the conductive layers while an insulating film is placed between the magnetic layers and the conductive layers. Next, an insulating layer of alumina, for example, is formed over the entire surfaces of the magnetic layers. This insulating layer is polished to the surfaces of the conductive layers and flattened.Type: GrantFiled: November 9, 1999Date of Patent: May 14, 2002Assignee: TDK CorporationInventor: Yoshitaka Sasaki
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Patent number: 6365059Abstract: The stamping process and a method of fabrication of nano-stamps with characteristic dimensions below 1 nm and up to 100 nm intended for usage in making patterns of characteristic dimensions the same as those of the nano-stamp on surface of a substrate is provided. In the process a very hard stamp is fabricated by first depositing alternating layers of two materials, one of which has very high hardness, on some sacrificial substrate via PVD, CVD or any other deposition procedure that produces alternating layers of selected thickness, from sub 1 nm to above 100 nm. The layered film is then polished to an atomically smooth finish perpendicular to the plane of the layers and etched to produce dips in the softer layers. These steps produce a grid of parallel elevations and valleys on the etched surface, which now can be used as a stamp to stamp out patterns on a substrate of lower hardness than the hardness of the elevated layers.Type: GrantFiled: April 28, 2000Date of Patent: April 2, 2002Inventor: Alexander Pechenik
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Publication number: 20010047931Abstract: Before submitting a sample, including a first material layered upon a substrate, to an ion milling process, whereby a second material is sputtered onto the surface of the first material and the sample is then submitted to an etching process, an irregularity is formed on the surface of the first material. The overall process results in the formation of cones, or micro-tip structures, which may then be layered with a layer of low work function material, such as amorphous diamond. The irregularity in the surface of the first material may be formed by polishing, sandblasting, photolithography, or mechanical means such as scratching.Type: ApplicationFiled: February 7, 2001Publication date: December 6, 2001Applicant: SI Diamond Technology, Inc.Inventors: Chenggang Xie, Dean Joseph Eichman
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Publication number: 20010044259Abstract: A ultra fine particle film forming apparatus is provided which is capable of forming a ultra fine particle film which has ultra fine particles sufficiently bonded together, sufficient density, flat surface and uniform density. A planarized ultra fine particle film forming method for forming a planarized ultra fine particle film from a deposited film of ultra fine particles formed by supplying the ultra fine particles to a substrate, the method comprising one or more of a planarizing step of planarizing a surface of the deposited film of the ultra fine particles supplied to the substrate.Type: ApplicationFiled: December 30, 2000Publication date: November 22, 2001Inventor: Jun Akedo
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Patent number: 6309580Abstract: The addition of thin coatings (less than and approaching monomolecular coatings) of persistent release materials comprising preferred compounds of the formula: RELEASE-M(X)n−1— RELEASE-M(X)n−m−1 Qm, or RELEASE-M(OR)n−1—, wherein RELEASE is a molecular chain of from 4 to 20 atoms in length, preferably from 6 to 16 atoms in length, which molecule has either polar or non-polar properties; M is a metal atom, semiconductor atom, or semimetal atom; X is halogen or cyano, especially Cl, F, or Br; Q is hydrogen or alkyl group; m is the number of Q groups; R is hydrogen, alkyl or phenyl, preferably hydrogen or alkyl of 1 to 4 carbon atoms; and; n is the valence −1 of M, and n−m−1 is at least 1 provides good release properties.Type: GrantFiled: June 30, 1998Date of Patent: October 30, 2001Assignee: Regents of the University of MinnesotaInventor: Stephen Y. Chou
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Patent number: 6306752Abstract: A method of making a connection component for a microelectronic element includes providing a sheet comprising an electrically conductive layer, a photoresist layer overlying the conductive layer and a photoimageable dielectric layer disposed under the conductive layer. The method includes lithographically forming at least one opening in the photoresist layer to uncover a portion of the conductive layer, forming a plurality of circuit features from the conductive layer by removing the uncovered portion of the conductive layer, at least some of the circuit features being leads, and lithographically forming at least one aperture in the photoimageable dielectric layer.Type: GrantFiled: September 15, 1999Date of Patent: October 23, 2001Assignee: Tessera, Inc.Inventors: Thomas H. DiStefano, Joseph Fjeslstad, John W. Smith
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Publication number: 20010030172Abstract: A sputtering target is provided which provides early stabilization of the film-deposition rate of the sputtering target from its initial stage of use. The sputtering target surface subjected to erosion is formed with a surface-deformed layer. The surface-deformed layer is reduced by precision machining and removed by etching. The extent of etching is controlled so that the surface roughness (Ra) is in a range between 0.1% and 10% of the mean crystal grain diameter of the material constituting the target. The surface roughness (Ra) is defined as the mean roughness on the center line of the surface.Type: ApplicationFiled: May 24, 2001Publication date: October 18, 2001Inventors: Hideyuki Takahashi, Tateo Ohhashi, Kazuhiro Seki
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Publication number: 20010030171Abstract: A new polish cleaning apparatus and a cleaning method are described for cleaning an HGA (head gimbal assembly) to meet the increasing requirements for cleanliness of read-write heads in the disk drive industry. The HGA polish cleaning apparatus includes an HGA polish cleaning assembly having a set of HGA carriers for effectively simultaneously polish clean a plurality of HGAs against a back and forth moving polish finger wrapped with anti-static polyester cloth. A plurality of HGAs to be polished are simultaneously loaded into the HGAs carriers which are then immersed in a polish cleaning tank containing a solution. The HGA carriers are driven by a pneumatic cylinder unit which is individually controlled by a programmable controller for exact polish cleaning. It also has a plurality of press-pins to fix the HGAs and supply proper friction between the slider ABS surface and the polish surface. The polish cleaning tank has an overflow weir, a pump, and a filter canister with a 0.Type: ApplicationFiled: March 16, 2001Publication date: October 18, 2001Inventors: Mingbing Wong, Fuhong Yu, Liang Qian, Feng Xie
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Patent number: 6296740Abstract: Before submitting a sample, including a first material layered upon a substrate, to an ion milling process, whereby a second material is sputtered onto the surface of the first material and the sample is then submitted to an etching process, an irregularity is formed on the surface of the first material. The overall process results in the formation of cones, or micro-tip structures, which may then be layered with a layer of low work function material, such as amorphous diamond. The irregularity in the surface of the first material may be formed by polishing, sandblasting, photolithography, or mechanical means such as scratching.Type: GrantFiled: April 24, 1995Date of Patent: October 2, 2001Assignee: SI Diamond Technology, Inc.Inventors: Chenggang Xie, Dean Joseph Eichman
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Publication number: 20010013503Abstract: Planarizing machines, carrier heads for planarizing machines and methods for planarizing microelectronic-device substrate assemblies in mechanical or chemical-mechanical planarizing processes. In one embodiment of the invention, a carrier head includes a backing plate, a bladder attached to the backing plate, and a retaining ring extending around the backing plate. The backing plate has a perimeter edge, a first surface, and a second surface opposite the first surface. The second surface of the backing plate can have a perimeter region extending inwardly from the perimeter edge and an interior region extending inwardly from the perimeter region. The perimeter region, for example, can have a curved section extending inwardly from the perimeter edge of the backing plate or from a flat rim at the perimeter edge. The curved section can curve toward and/or away from the first surface to influence the edge pressure exerted against the substrate assembly during planarization.Type: ApplicationFiled: March 16, 2001Publication date: August 16, 2001Inventors: Daniel G. Custer, Aaron Trent Ward
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Patent number: 6274059Abstract: A method to remove metal contaminants in a substrate cleaning process. The present invention may replace or be used in conjunction with other substrate cleaning systems. This method comprises adding a citric acid solution to the liquid medium of a semiconductor substrate cleaning system. This method is described in the manner it is used in conjunction with a scrubber wherein both sides of a wafer are scrubbed.Type: GrantFiled: March 11, 1996Date of Patent: August 14, 2001Assignee: Lam Research CorporationInventors: Wilbur C. Krusell, Igor J. Malik
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Patent number: 6264851Abstract: The present invention is for a method wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.Type: GrantFiled: March 17, 1998Date of Patent: July 24, 2001Assignee: International Business Machines CorporationInventors: Voya R. Markovich, William E. Wilson, Michael Wozniak
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Patent number: 6241903Abstract: A diffuser master is provided which is manufactured mechanically instead of holographically. The master can be made from a suitable substrate including relatively hard materials such as plastic, glass or metal. A substrate having a first side is worked to form a diffuser surface relief structure thereon. The substrate can be buffed using a buffing agent of a selected grit in order to form surface scratches in the first side of the substrate. The substrate can also be blasted with shot particles in order to form indentations and depressions in the first side. The substrate can alternatively be acid or alkali etched in order to form surface irregularities in the first side. The scratches, depressions or irregularities can be formed in order to create a desired surface relief and hence desired diffuser output characteristics.Type: GrantFiled: August 20, 1998Date of Patent: June 5, 2001Assignee: Physical Optics CorporationInventors: Gajendra D. Savant, Kevin H. Yu, Andrew A. Kostrzewski
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Patent number: 6217787Abstract: We are familiar with etching printed circuit boards chemically by providing a copper board with a mask and etching copper away chemically at those points where the mask is not present. This is disadvantageous, e.g. from environmental standpoints, because the chemical liquid is increasingly enriched with copper, and, when the liquid has been used, it can no longer be employed and is also difficult to dispose of. The invention is based on the object of providing a method of either applying or removing conductive material electrically.Type: GrantFiled: June 29, 1998Date of Patent: April 17, 2001Assignee: Deutsche Thomson-Brandt GmbHInventor: Hans-Otto Haller
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Patent number: 6193898Abstract: A plurality of reflectors respectively having the same rough reflecting surfaces are formed substantially simultaneously on a transparent substrate of a large area. A photosensitive resin film is formed on a surface of a transparent substrate. An embossing die having a rough working surface is pressed against a photosensitive resin part of the photosensitive resin film and the photosensitive resin part is irradiated with ultraviolet rays from below the transparent substrate to form a prehardened photosensitive resin part. Those steps are repeated to form a plurality of prehardened, embossed photosensitive resin parts on the transparent substrate, and then parts not prehardened of the photosensitive resin film are removed by etching. The prehardened, embossed photosensitive resin parts are heated for hardening, and a metal reflecting film is formed on the hardened embossed photosensitive resin parts to complete a plurality of reflectors.Type: GrantFiled: October 13, 1998Date of Patent: February 27, 2001Assignee: Alps Electric Co., Ltd.Inventors: Mitsuru Kano, Tomomasa Takatsuka, Kenji Omote
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Patent number: 6174448Abstract: A method of removing a diffusion aluminide coating on a component designed for use in a hostile environment, such as superalloy turbine, combustor and augmentor components of a gas turbine engine. The method selectively removes an aluminide coating by stripping aluminum from the coating without causing excessive attack, alloy depletion and gross thinning of the underlying superalloy substrate. Processing steps generally include contacting the coating with a mixture that contains a halogen-containing activator and a metallic powder containing an aluminide-forming metal constituent, such as by pack cementation-type process. The mixture is then heated to a temperature sufficient to vaporize the halogen-containing activator and for a duration sufficient to cause the halogen-containing activator to provide a transfer mechanism for the removal of aluminum from at least a portion of the diffusion aluminide coating, while the metallic powder absorbs the removed aluminum.Type: GrantFiled: March 2, 1998Date of Patent: January 16, 2001Assignee: General Electric CompanyInventors: Nripendra N. Das, Howard J. Farr, Raymond W. Heidorn
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Patent number: 6152995Abstract: A hydrogen-permeable metal membrane with increased hydrogen flux compared to conventional metal membranes is disclosed. Without sacrificing selectivity, the membrane enables a greater throughput of purified hydrogen. A method for preparing the invention includes at least one etching step in which a controlled volume of etchant is used to selectively remove material from the membrane's surface. Methods for repairing holes or other defects in the membrane are also disclosed.Type: GrantFiled: March 22, 1999Date of Patent: November 28, 2000Assignee: IdaTech LLCInventor: David J. Edlund
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Patent number: 6090688Abstract: A method for fabricating an SOI substrate is provided, which has an active substrate formed as a thin film. The method comprises the steps of: using a both-side polishing apparatus to polish both sides of a supporting substrate 1; bonding an active substrate 2 onto the supporting substrate 1. to form a bonded-wafer; removing an unbonded portion formed at the circumference of the bonded-wafer; flat grinding the active substrate 2 to reduce the thickness thereof; etching the active substrate 2 by spin etching; and processing the active substrate to be a thin film by PACE processing.Type: GrantFiled: November 15, 1996Date of Patent: July 18, 2000Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Tadashi Ogawa, Akihiro Ishii, Yuichi Nakayoshi
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Patent number: 6066562Abstract: A method of fabricating a silicon semiconductor discrete wafer is disclosed that assures excellent finishing accuracy and productivity. The method for fabricating a discrete wafer having a double-layer structure including an impurity diffused layer at one side and an impurity non-diffused layer at the opposite side includes cutting a wafer, having one of the impurity diffused layers formed on both surfaces of the silicon semiconductor wafer and having an oxide film formed on the surface of the diffused layer, into two pieces at the center of thickness with an ID saw slicing machine. Then, both surfaces of the cutting surface are ground to a predetermined thickness with a surface grinding machine, and the grinding surfaces are lapped with abrasive grains having a count of at least #2000 and no more than #6000. The processing surface is wet-etched as the final processing.Type: GrantFiled: July 22, 1997Date of Patent: May 23, 2000Assignee: Naoetsu Electronics CompanyInventors: Hisashi Ohshima, Tsutomu Satoh
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Patent number: 6066266Abstract: A process for compensating for degradation of a first polishing pad during polishing on the first polishing pad of a plurality of substrate surfaces that have substantially similar film stacks is described. The process includes: (a) characterizing a test polishing pad, which characterization includes determining changes in film removal rates of layers of the film stack during polishing of the plurality of the substrate surfaces on the test polishing pad; (b) polishing a first substrate surface on the first polishing pad, which is substantially similar to the test polishing pad, under a first set of polishing conditions; and (c) polishing a second substrate surface on the first polishing pad under a second set of polishing conditions. A difference between the second set of polishing conditions and the first set of polishing conditions is designed to minimize the changes in the film removal rates of the layers of the film stack and thereby compensate for degradation of the first polishing pad.Type: GrantFiled: July 8, 1998Date of Patent: May 23, 2000Assignee: LSI Logic CorporationInventors: Richard S. Osugi, Ronald J. Nagahara, Dawn M. Lee
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Patent number: 6057602Abstract: The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low friction material positioned over the substrate, and an upper layer deposited on the low friction material stratum. The low friction stratum has a polish-stop surface positioned at a level substantially proximate to a desired endpoint of the chemical-mechanical planarization process. The upper layer, which is made from either a conductive material or an insulative material, has a higher polishing rate than that of the low friction stratum. In operation, the low friction stratum resists chemical-mechanical planarization with either hard or soft polishing pads to stop the planarization process at the desired endpoint.Type: GrantFiled: August 14, 1998Date of Patent: May 2, 2000Assignee: Micron Technology, Inc.Inventors: Guy F. Hudson, Russell C. Zahorik
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Patent number: 6024828Abstract: A workpiece with a back surface and a front surface has a layer formed on the front surface thereof which is to be etched by plasma etching. The workpiece is placed on a lower electrode in a plasma etching system with the back surface resting on the lower electrode. The workpiece is clamped to the lower electrode. A gas circulation system is formed in the surface of the lower electrode to supply heated gas, under pressure, to the back surface of a workpiece placed thereon to cause the workpiece to bow thereby forming a vaulted space below the workpiece. Then, while heating the back of the workpiece in this way, plasma etching of the layer upon the workpiece is performed.Type: GrantFiled: March 9, 1998Date of Patent: February 15, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Yuan Ko Hwang
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Patent number: 6015506Abstract: A method for polishing computer rigid disks comprising bringing at least one surface of the rigid disk into contact with a polishing pad and applying a dispersion to the rigid disk to give a polished rigid disk having an rms roughness less than about 1.4 nm. Also disclosed is a dispersion and polishing slurry for polishing rigid disks.Type: GrantFiled: April 18, 1997Date of Patent: January 18, 2000Assignee: Cabot CorporationInventors: Christopher C. Streinz, Matthew Neville, Steven K. Grumbine, Brian L. Mueller
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Patent number: 5993677Abstract: A thin film is transferred from an initial substrate onto a final substrate. The process includes the following successive stages: joining of the thin film (112) onto a handle substrate (120) comprising a cleavage zone, elimination of the initial substrate, joining of the thin film (112) with a final substrate (132), and cleavage of the handle substrate (120) following the cleavage zone. The cleavage zone includes a film of micro-bubbles formed by ion implantation. The invention has, in particular, applications in the fabrication of three-dimensional structures of integrated circuits.Type: GrantFiled: January 10, 1997Date of Patent: November 30, 1999Assignee: Commissariat a L'Energie AtomiqueInventors: Beatrice Biasse, Michel Bruel, Marc Zussy
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Patent number: 5958288Abstract: A chemical mechanical polishing composition comprising an oxidizing agent and at least one catalyst having multiple oxidation states, the composition being useful when combined with an abrasive or with an abrasive pad to remove metal layers from a substrate.Type: GrantFiled: November 26, 1996Date of Patent: September 28, 1999Assignee: Cabot CorporationInventors: Brian L. Mueller, Christopher C. Streinz, Steven K. Grumbine
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Patent number: 5932114Abstract: An optical module includes support substrate, an optical waveguide on the support substrate, a photoreception device on the support substrate, an optical path conversion part for converting an optical path of an optical beam guided through the optical waveguide from a first optical path to a second optical path that leads to a photodetection area of said photoreception device, wherein the optical path conversion part is provided on the photodetection device as a part thereof, such that the optical beam emitted from the optical waveguide impinges upon the photodetection area of the photoreception device.Type: GrantFiled: September 12, 1997Date of Patent: August 3, 1999Assignee: Fujitsu LimitedInventor: Masao Makiuchi
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Patent number: 5925259Abstract: A process for producing lithographic features in a substrate layer is is described, comprising the steps of lowering a stamp (15) carrying an reactant (14) onto a substrate (10), confining the subsequent reaction to the desired pattern, lifting said stamp and removing the debris of the reaction from the substrate. Preferably, the stamp carries the pattern to be etched or depressions corresponding to such a pattern. Using the described methods, patterns with submicron features can be generated. The method allows a general solution to parallel handling and transfer of materials in a variety of technical fields.Type: GrantFiled: August 1, 1996Date of Patent: July 20, 1999Assignee: International Business Machines CorporationInventors: Hans Andre Biebuyck, Bruno Michel
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Patent number: 5895583Abstract: Silicon carbide wafers are prepared for semiconductor epitaxial growth by first lapping a silicon carbide wafer derived from a boule, by placing the wafer in a recess of a metal backed template and moving the wafer over and against a rotating plate. Two different diamond slurry mixtures of progressively smaller diamond grit sizes are sequentially used, along with a lubricant, for a predetermined period of time. The lapping operation is followed by a polishing operation which sequentially utilizes two different diamond slurry mixtures of progressively smaller diamond grit sizes, along with three different apertured pads sequentially applied to a rotatable plate, with the pads being of progressively softer composition. In a preferred embodiment the wafers are cleaned and the templates are changed after each new diamond slurry mixture used.Type: GrantFiled: November 20, 1996Date of Patent: April 20, 1999Assignee: Northrop Grumman CorporationInventors: Godfrey Augustine, Donovan L. Barrett, Elizabeth Ann Halgas
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Patent number: 5882539Abstract: A wafer processing method which can polish the chamfered portion of a wafer quickly, is disclosed. The processing method comprises the steps of: chamfering a peripheral portion of a wafer obtained by slicing an ingot, by grinding; lapping the wafer; etching the chamfered or lapped wafer; thereafter honing the entirety of the chamfered peripheral portion of the wafer by using a grinding stone while applying a predetermined load to the grinding stone; and thereafter polishing the entirety of the chamfered peripheral portion and the front and rear surfaces of the wafer.Type: GrantFiled: August 14, 1996Date of Patent: March 16, 1999Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumihiko Hasegawa, Yasuyoshi Kuroda, Masayuki Yamada
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Patent number: 5863449Abstract: This invention relates to a method of making fiber optic interferometers. First, a plurality of optical fibers are bundled and placed into a sleeve. The bundle is then encased in the sleeve and the fiber ends are cut and polished. An area of cladding is stripped back from the polished fiber ends and layers of material are deposited on the fiber ends. These layers of material have varying indexes of refraction and form a grating. The bundle of optical fibers is then removed from encasing in the sleeve.Type: GrantFiled: March 29, 1996Date of Patent: January 26, 1999Assignee: The Whitaker CorporationInventor: Dimitry G. Grabbe
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Patent number: 5863829Abstract: The present invention provides a process for fabricating an SOI substrate with no peripheral scratches and with enhanced fabrication efficiency. The present process includes bonding a semiconductor wafer of an active substrate 1 and a semiconductor base wafer 2 to form a bonded wafer 4; surface-grinding the active substrate 1; spin etching the surface-ground active substrate 1; and PACE processing the etched active substrate 1 to form the active substrate into a thin film and simultaneously, to remove the non-bonded peripheral portion of the bonded wafer 4.Type: GrantFiled: November 13, 1996Date of Patent: January 26, 1999Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Yuichi Nakayoshi, Hiroaki Yamamoto, Akihiro Ishii
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Patent number: 5851411Abstract: A method for manufacturing a display, which includes first and second substrates, each having an inner light shielding region and an edge light shielding region, includes the steps of defining the edge light shielding region into a first portion and a second portion, and defining an area of the first substrate. The area includes the first portion of the edge light shielding region. The area including the first portion of the edge light shielding region is removed and leaves the second portion of the edge light shielding region. The first and second substrates are combined at the second portion of the edge light shielding region.Type: GrantFiled: November 1, 1996Date of Patent: December 22, 1998Assignee: LG Electronics, Inc.Inventors: Sang-Sik An, Sang-Ho Lee, Dong-Hyo Gu, Min-Choel Shin
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Patent number: 5840205Abstract: A method of fabricating a specimen for analyzing defects of a semiconductor device is disclosed. The method includes the steps of: cutting a wafer to be adjacent to a defective portion that exists in a patterned layer formed on a substrate; molding the first specimen with a resin; grinding the substrate of the first specimen with a predetermined slope; and etching the ground face to expose the defective layer, wherein the wafer includes a semiconductor substrate and patterned layers where memory devices are formed on the semiconductor substrate.Type: GrantFiled: July 19, 1996Date of Patent: November 24, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Jeong-Hoi Koo, Doo-Jin Park
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Patent number: 5772905Abstract: A lithographic method and apparatus for creating ultra-fine (sub-25 nm) patterns in a thin film coated on a substrate is provided, in which a mold having at least one protruding feature is pressed into a thin film carried on a substrate. The protruding feature in the mold creates a recess of the thin film. The mold is removed from the film. The thin film then is processed such that the thin film in the recess is removed exposing the underlying substrate. Thus, the patterns in the mold is replaced in the thin film, completing the lithography. The patterns in the thin film will be, in subsequent processes, reproduced in the substrate or in another material which is added onto the substrate.Type: GrantFiled: November 15, 1995Date of Patent: June 30, 1998Assignee: Regents of the University of MinnesotaInventor: Stephen Y. Chou
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Patent number: 5770036Abstract: For a condensed matter system containing a guest interstitial species such as hydrogen or its isotopes dissolved in the condensed matter host lattice, the invention provides tuning of the molecular orbital degeneracy of the host lattice to enhance the anharmonicity of the dissolved guest sublattice to achieve a large anharmonic displacement amplitude and a correspondingly small distance of closest approach of the guest nuclei. The tuned electron molecular orbital topology of the host lattice creates an energy state giving rise to degenerate sublattice orbitals related to the second nearest neighbors of the guest bonding orbitals. Thus, it is the nuclei of the guest sublattice that are set in anharmonic motion as a result of the orbital topology. This promotion of second nearest neighbor bonding between sublattice nuclei leads to enhanced interaction between nuclei of the sublattice.Type: GrantFiled: May 2, 1996Date of Patent: June 23, 1998Assignee: Massachusetts Institute of TechnologyInventors: Brian S. Ahern, Keith H. Johnson, Harry R. Clark, Jr.
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Patent number: 5746931Abstract: This application describes a new method for rapid thinning, planarizing and fine polishing surfaces of diamond to the submicron/nanometer level so that large area, uniform thickness diamond wafers can be obtained. The method combines both chemical (dissolution of carbon in molten metals) and mechanical (rotating or moving sample fixtures in contact with the dissolving metals) polishing to achieve flat, smooth surface finishes in a relatively short period of time, thus improving the quality and economics of the overall polishing process. Several embodiments of apparatus for performing such chemical-mechanical polishing (CMP) of diamond are described.Type: GrantFiled: December 5, 1996Date of Patent: May 5, 1998Assignee: Lucent Technologies Inc.Inventors: John Edwin Graebner, Sungho Jin, Wei Zhu
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Patent number: 5736061Abstract: A semiconductor sensor mount is formed as follows: through holes are formed that penetrate a glass plate; and then the glass plate having the through holes is dipped into hydrofluoric acid etchant to smooth the inner peripheral surfaces of the respective through holes. By etching the inner peripheral surfaces of the respective through holes after the through hole formation, minute roughness and cracks formed on the inner peripheral surfaces are removed, and thereby the areas for adsorbing gas are substantially reduced. That is, vacuums within the through holes can be maintained at a high degree during the anodic bonding, whereby undesirable electric discharge phenomena are prevented even if a relatively high voltage is applied during the anodic bonding. Accordingly, the yield of products can be improved while improving productivity.Type: GrantFiled: June 27, 1996Date of Patent: April 7, 1998Assignees: Nippondenso Co. Ltd., Iwaki Glass Co., Ltd.Inventors: Tsuyoshi Fukada, Yasutoshi Suzuki, Koushu Satoh, Hiroaki Kawashima
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Patent number: 5665252Abstract: The method of shaping a polycrystalline diamond (PCD) body (exemplarily a wafer of CVD-PCD) utilizes our discovery that the rate and amount of diamond removal from a given region of a PCD body depends, for a given metal "etchant" at a given temperature, on the thickness of the etchant layer overlying the given region, with relatively larger etchant thickness being associated with relatively higher removal rate and amount. Exemplarily, the method can be used to substantially remove thickness variations and/or film curvature from as-produced PCD films. An exemplary metal that can be used in the practice of the invention is mischmetal. The metal etchant can be molten, partially molten or solid.Type: GrantFiled: July 12, 1995Date of Patent: September 9, 1997Assignee: Lucent Technologies Inc.Inventors: Sungho Jin, Wei Zhu