Abstract: The present invention includes a method for making an emitter for a display device, an emitter array produced by such method, an etch mask used during such method, and a method for making such an etch mask. The method for making the emitter is practiced by providing a substrate, forming a conducting layer on the substrate, forming an emitting layer on the conducting layer, forming an etch mask having a controlled distribution of a plurality of mask sizes over the emitting layer, and forming at least one emitter by removing portions of the emitting layer using the etch mask. The method for making the etch mask is practiced by forming an etch mask layer over an emitting layer, forming a patterning layer having a controlled distribution of mask sizes over the etch mask layer, and forming the etch mask by removing portions of the etch mask layer using the controlled distribution of mask sizes in the patterning layer.

Abstract: When in a chamber, an upper electrode and a lower electrode (suscepter) are provided opposite to each other and with a to-be-treated substrate supported by the lower electrode, the high-frequency electric field is formed between the upper electrode and the lower electrode to generate plasma of the process gas while introducing the process gas into the chamber held to the reduced pressure, and an etching is provided to the to-be-treated substrate with this plasma, the high frequency in the range from 50 to 150 MHZ, for example, 60 MHz, is applied to the upper electrode, and the high frequency in the range from 1 to 4 MHz, for example, 2 MHz, is applied to the lower electrode.

Abstract: A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration.

Abstract: Low acoustic solid wave attenuation structures are formed with an electroformed nickel mold, and are incorporated within acoustic ink emitters, between the focusing lens and surface of an ink layer. The structures have characteristics of low attenuation of acoustic waves to increase the efficiency of acoustic wave transmission within the acoustic ink emitter. Using the described structures, acoustic ink printers can accurately emit materials having high viscosity, including hot melt inks.

Abstract: An etching gas is supplied into a process chamber and turned into plasma so as to etch a silicon nitride film arranged on a field silicon oxide film on a wafer (w). A mixture gas containing at least CH2F2 gas and O2 gas is used as the etching gas. Parameters for planar uniformity, by which the etching apparatus is set in light of a set value of the planar uniformity, include the process pressure and the mixture ratio (CH2F2/O2) of the mixture gas. As the set value of the planar uniformity is more strict, either one of the process pressure and the mixture ratio is set higher.

Abstract: A method of etching silicon using a chlorine and sulfur dioxide gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 100 sccm of sulfur dioxide, regulated to a total chamber pressure of 2-100 mTorr.

Abstract: In order to manufacture an integrated optical circuit, a first mask is formed on a first region of a substrate and defines the shape of at least one optical device (such as a waveguide). A second mask is formed on a second region of the substrate and corresponds to an optical structure (such as a periodic array structure or photonic crystal) to be formed in a second region of the substrate distinct from the first region. The first mask and the second mask are each made of a material which substantially resists a predetermined etching gas. The second mask may formed, patterned, and etched without adversely affecting the characteristics of the first mask.

Abstract: A method of forming a needle includes the step of anisotropically etching a channel into the back side of a semiconductor substrate. The front side of the semiconductor substrate is then isotropically etched to form a vertical axial surface surrounding the channel. The resultant needle has an elongated body formed of a semiconductor material. The elongated body includes an axial surface positioned between a first end and a second end. The axial surface defines a channel between the first end and the second end. In one embodiment, the first end has a sloping tip with a single circumferential termination point.

Abstract: The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus in which a concentration of oxygen at flash striking is greater than a concentration during etching.

Abstract: A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners.

Abstract: In accordance with the present invention, during a polysilicon etch back, a controlled amount of oxygen (O2) is added to the plasma generation feed gases, to reduce pitting of the etched back polysilicon surface. The plasma etchant is generated from a plasma source gas comprising: (i) at least one fluorine-containing gas, and (ii) oxygen. The invention may be practiced in any of a number of apparatus adapted to expose polysilicon to a plasma etchant. One preferred apparatus is a decoupled plasma source (DPS™, Applied Materials, Santa Clara, Calif.) etching system. Another preferred apparatus is a magnetically enhanced plasma (MXP™, Applied Materials, Santa Clara, Calif.) etching system.

Abstract: The invention concerns a method for simultaneously forming a metallization and contact structure in an integrated circuit. The method involves the steps of etching a trench dielectric layer of a composite structure having a semiconductor substrate with an active region, a gate structure thereon, at least one dielectric spacer adjacent to the gate structure, a contact dielectric layer over the semiconductor substrate, the gate structure and the dielectric spacer, an etch stop layer over the contact dielectric layer, and a trench dielectric layer over the etch stop layer, to form a trench in the trench dielectric under etch conditions which do not substantially etch the etch stop layer; thereafter, forming an opening in the etch stop layer and the contact dielectric layer by etching under conditions which do not damage the gate structure to expose the active region; and depositing a conductive material into the opening and the trench.

Abstract: A plasma process for etching oxide and having a high selectivity to silicon including flowing into a plasma reaction chamber a fluorine-containing etching gas and maintaining a temperature of an exposed silicon surface within said chamber at a temperature of between 200° C. and 300° C. An example of the etching gas includes SiF4 and a fluorocarbon gas. The plasma may be generated by a capacitive discharge type plasma generator or by an electromagnetically coupled plasma generator, such as an inductively coupled plasma generator. The high selectivity exhibited by the etch process permits use of an electromagnetically coupled plasma generator, which in turn permits the etch process to be performed at low pressures of between 1 and 30 milliTorr, resulting the etching of vertical sidewalls in the oxide layer.

Abstract: A method and apparatus for selectively removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other materials that may be thereon, by exposing the silicon wafer to an etchant gas including NF3 while simultaneously exposing the wafer to ultraviolet radiation, and heating the wafer to a temperature of 100-400° C.

Abstract: A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes, with an efficient sputtering inert gas, such as Ar, replaced or reduced with an He inefficient sputtering inert gas such as He. By reducing the sputtering component, sidewall deposition from the sputtered material is reduced. Consequently, gaps with aspect ratios of 6.0:1 and higher can be filled without the formation of voids and without damaging circuit elements.

Abstract: A method and an apparatus for etching a semiconductor device which can perform an etching process without causing electrical and physical damages using a neutral beam generated by a simple apparatus. In the method, ions of an ion beam having a predetermined polarity are extracted from an ion source and accelerated. An accelerated ion beam is reflected by a reflector and neutralized. A substrate to be etched positioned in the path of the neutral beam in order to etch a special material layer on the substrate with the neutral beam. The gradient of the reflector is adjusted to control an angle of incidence of the ion beam incident on the reflector, and a voltage is applied to the reflector to control the path of an incident ion beam.

Abstract: A method and apparatus is provided for locating with improved vertical positioning accuracy a discrete element on a semiconductor optoelectronic integrated circuit. The method employs an etch stop layer located beneath a series of semiconductor layers. The semiconductor layers may include waveguides to couple light between integrated or discrete elements. Pits with accurate depth are etched in the semiconductor layers down to the etch stop layer. Accurate alignment between a discrete element and another element is made possible by controlling their respective distances from the etch stop layer.

Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.

Abstract: Hybrid molds for molding a multiplicity of solder balls for use in a molten solder screening process and methods for preparing such molds are disclosed. A method for forming the multiplicity of cavities in a pyramidal shape by anisotropically etching a crystalline silicon substrate along a specific crystallographic plane is utilized to form a crystalline silicon face plate used in the present invention hybrid mold. In a preferred embodiment, a silicon face plate is bonded to a borosilicate glass backing plate by adhesive means in a method that ensures coplanarity is achieved between the top surfaces of the silicon face plate and the glass backing plate. In an alternate embodiment, an additional glass frame is used for bonding a silicon face plate to a glass backing plate, again with ensured coplanarity between the top surfaces of the silicon face plate and the glass frame. In a second alternate embodiment, a silicon face plate is encased in an extender material which may be borosilicate glass or a polymer.

Abstract: An oxide etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention uses one of three hydrogen-free fluorocarbons having a low F/C ratio, specifically hexafluorobutadiene (C4F6), hexafluorocyclobutene (C4F6), and hexafluorobenzene (C6F6). At least hexafluorobutadiene has a boiling point below 10° C. and is commercially available. The fluorocarbon together with a substantial amount of a noble gas such as argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. Preferably, one of two two-step etch process is used. In the first, the source and bias power are reduced towards the end of the etch.

Abstract: An apparatus and method for scavenging etchant species from a plasma formed of etchant gas prior to the etchant gas entering a primary processing chamber of a plasma reactor. There is at least one scavenging chamber, each of which is connected at an inlet thereof to an etchant gas source and at an outlet thereof to a gas distribution device of the primary processing chamber. Each scavenging chamber has a radiation applicator that irradiates the interior of the scavenging chamber and creates a plasma therein from etchant gas flowing through the chamber from the etchant gas source to the gas distribution apparatus of the primary processing chamber. The applicator uses either an inductive discharge, capacitive discharge, direct current (DC) discharge or microwave discharge to irradiate the interior of the scavenging chamber and ignite the plasma. An etchant species scavenging source is also disposed within the scavenging chamber.

Abstract: A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma.

Abstract: The present disclosure relates to semiconductor processing, and to the plasma etching of organic layers, and in particular antireflective coating layers. We have discovered a particular combination of gases useful in producing chemically reactive plasma species, which provides unexpected control over etched feature critical dimension, etch profile, and uniformity of etch across a substrate surface, despite a difference in the spacing of etched features over the substrate surface. The combination of gases which produces chemically reactive plasma species consists essentially of CxHyFz, a bromine-comprising compound (which is typically HBr), and O2, where x ranges from 1 to 4, y ranges from 0 to 3, and z ranges from 1 to 10. Oxygen atoms may be substituted for hydrogen atoms in the CxHyFz compound to a limited extent Essentially inert gases which do not produce chemically reactive species may be added to the combination of etchant-species producing gases.

Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel. In an embodiment of the present invention, a semiconductor structure is placed into a first treatment vessel and chemically treated. Following the chemical treatment, the semiconductor structure is transferred directly to a second treatment vessel where it is rinsed with DI water and then dried. The second treatment vessel is flooded with both DI water and a gas that is inert to the ambient, such as nitrogen, to form a DI water bath upon which an inert atmosphere is maintained during rinsing. Next, an inert gas carrier laden with IPA vapor is fed into the second treatment vessel. After sufficient time, a layer of IPA has formed upon the surface of the DI water bath to form an IPA-DI water interface.

Abstract: The present disclosure pertains to an integrated post-etch treatment method which is performed after a dielectric etch process. Using the method of the invention, byproducts formed on the sidewalls of contact vias during the dielectric etch process can be removed efficiently. The method of the invention also reduces or eliminates the problem of polymer accumulation on process chamber surfaces. An overlying photoresist layer and anti-reflection layer are removed during the performance of the post-etch treatment method. Typically, after the etch of a dielectric material to define pattern or interconnect filling spaces, a series of post-etch treatment steps is performed to remove residues remaining on the wafer after the dielectric etch process. According to the method of the present invention, a post-etch treatment method including one or more steps is performed after the dielectric etch process, preferably within the same processing chamber in which the dielectric etch process was performed.

Abstract: An ink-jet head is produced by means of an etching employing a mask member which is formed without defects such as pinholes. More specifically, a polyetheramide resin layer is employed as an etching-resistance mask when processing a substrate by means of the etching, in which the polyetheramide resin layer is etched by means of an etching gas containing oxygen as main component.

Abstract: A microelectromechanical (MEMS) apparatus has a base and a flap with a portion coupled to the base may be fabricated by an inventive process. The process generally involves etching one or more trenches in a backside of a base, e.g., by anisotropic etch. The trench may be etched such that an orientation of a sidewall is defined by a crystal orientation of the base material. A layer of insulating material is formed on one or more sidewalls of one or more of the trenches. A conductive layer is formed on the layer of insulating material on one or more sidewalls of one or more of the trenches. The conductive layer may completely fill up the trench between the insulating materials on the sidewalls to provide the isolated electrode. Base material is removed from a portion of the base bordered by the one or more trenches to form a cavity in the base. The trench etch may stop on an etch-stop layer so that the cavity does not form all the way through the base.

Abstract: A method for forming a multi-level metal interconnection, comprising the step of forming a first metal interconnection over an underlying layer; forming an insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole to contact with the first metal interconnection; etching the insulating layer by a portion of the selected thickness; forming a pair of metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through one of the metal spacers.

Abstract: The method of present invention etches a layer of polysilicon formed on a substrate disposed within a substrate processing chamber. The method flows an etchant gas including sulfur hexafluoride, an oxygen source and a nitrogen source into the processing chamber and ignites a plasma from the etchant gas to etch the polysilicon formed over the substrate. In a preferred embodiment, the etchant gas consists essentially of SF6, molecular oxygen (O2) and molecular nitrogen (N2). In a more preferred embodiment the etchant gas includes a volume ratio of molecular oxygen to the sulfur hexafluoride of between 0.5:1 and 1:1 inclusive and a volume ratio of the sulfur hexafluoride to molecular nitrogen of between 1:1 and 4:1 inclusive. In an even more preferred embodiment, the volume ratio of O2 to sulfur hexafluoride is between 0.5:1 and 1:1 inclusive and the volume ratio of sulfur hexafluoride to N2 is between 1.5:1 and 2:1 inclusive.

Abstract: An improved dry plasma cleaning process for the removal of native oxides, or other oxide films or growth residue, from openings formed in an insulating layer provided over a semiconductor substrate, without damaging the substrate or significantly affecting the critical dimension of the opening is disclosed. A mixture of nitrogen trifluoride (NF3), ammonia (NH3) and oxygen (O2) is first injected upstream into a microwave plasma source and is exited, and then the plasma is flowed downstream from the plasma source into a reaction chamber containing the substrate.

Abstract: A dual damascene type of structure of vias and trenches formed using layers of low k dielectric material is disclosed, and a process for making same without damage to the low k dielectric material during removal of photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings in the layers of low k dielectric material. Damage to the low k dielectric material is avoided by forming a first layer of low k dielectric material on an integrated circuit structure; forming a first hard mask layer over the first layer of low k dielectric material; forming over the first hard mask layer a first photoresist mask having a pattern of via openings therein; and then etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein, using an etch system which will also remove the first photoresist mask.

Abstract: A process for making at least one suspended element uses an etching technique for micro-machining a structure comprising a substrate covered in sequence by a first layer called a stop layer made of a first material, and a second layer made of a second material in which the suspended element is formed. The process uses a dry etching technique using a gas with sufficient selectivity to enable etching of the second layer without etching the stop layer, under conditions defined to enable anisotropic etching of the second material, the etching being carried out according to a first phase to delimit the suspended element as far as the level of the stop layer and being continued in a second phase during which the suspended element is released by etching of the surface layer of the suspended element delimited in the first phase and which is adjacent to the stop layer.

Abstract: A plasma etch process, particularly applicable to an self-aligned contact etch in a high-density plasma for selectively etching oxide over nitride, although selectivity to silicon is also achieved. In the process, a fluoropropane or a fluoropropylene is a principal etching gas in the presence of a substantial amount of an inactive gas such as argon. Good nitride selectivity has been achieved with hexafluoropropylene (C3F6), octafluoropropane (C3F8), heptafluoropropane (C3HF7), hexafluoropropane (C3H2F6). The process may use one or more of the these gases in proportions to optimize selectivity and a wide process window. Difluoromethane (CH2F2) or other fluorocarbons may be combined with the above gases, particularly with C3F6 for optimum selectivity over other materials without the occurrence of etch stop in narrow contact holes and with a wide process window.

Abstract: A phase shifting mask repair process is described. The process uses an etching gas or a hydrofluoric acid solution to etch the quartz substrate and the characteristics of the phase shifter layer being only slightly etched when clean with a NH3/H2O2/H2O2 solution to calculate and adjust the respective processing time accordingly. As a result, the phase difference between the quartz substrate and the MoSiON phase shifter layer stays relatively the same before and after the repair process.

Abstract: In the manufacture of a micromechanical device, a substrate, having a mask thereon, is etched using a flourine-containing etchant gas or vapour in the absence of a plasma through an opening in the mask to a desired depth to form a trench having a side wall and a base in the substrate. A layer of protecting substance is deposited on the exposed surfaces of the substrate and mask, and the protecting substance is then selectively removed from the base. The base is then etched using the fluorine-containing etchant.

Abstract: A method and apparatus are disclosed for electrically monitoring processing variations of a material deposited using a collimated process. In one embodiment, the method and apparatus are directed to monitoring variations in step coverage of a conductive material deposited using a collimated sputtering process. A substrate having a plurality of trenches is used to mimic features desired to be monitored, such as contact holes. The resistance of metal deposited into the trenches is monitored to determine the effectiveness of the collimated sputtering process.

Abstract: A method for producing periodic nanometer-scale arrays of metal or semiconductor junctions on a clean semiconductor substrate surface is provided comprising the steps of: etching the substrate surface to make it hydrophilic, forming, under an inert atmosphere, a crystalline colloid layer on the substrate surface, depositing a metal or semiconductor material through the colloid layer onto the surface of the substrate, and removing the colloid from the substrate surface. The colloid layer is grown on the clean semiconductor surface by withdrawing the semiconductor substrate from a sol of colloid particles.

Abstract: A phase shift mask blank includes a transparent substrate and a phase shift film composed primarily of a metal and silicon. The substrate has an etch rate A and the phase shift film has an etch rate B when the blank is patterned by reactive ion etching, such that the etch selectivity B/A is at least 5.0. When a phase shift mask is manufactured from the blank, the substrate is less prone to overetching, providing good controllability and in-plane uniformity of the phase shift in patterned areas. The phase shift mask can be used to fabricate semiconductor integrated circuits to a smaller minimum feature size and a higher level of integration.

Abstract: A method of forming a pattern in a layer of material on a substrate, comprising providing a plurality of spheres, covering the layer on the substrate with the plurality of spheres to form a mask, reducing the diameter of at least one sphere of the plurality of spheres, etching the layer on the substrate using the at least one sphere having a reduced diameter as a mask, and etching the substrate.

Abstract: A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask.

Abstract: One embodiment of a microneedle array is constructed of silicon and silicon dioxide compounds using MEMS technology and standard microfabrication techniques to create hollow cylindrical individual microneedles. The resulting array of microneedles is designed to penetrate the stratum corneum and epidermis layers of skin, but not into the dermis. In a second embodiment, an array of hollow (or solid) microneedles are constructed of molded plastic, in which a micro-machining technique is used to fabricate the molds used in a plastic microforming process. Such molds contain a micropillar array and/or microhole array. The manufacturing procedures for creating plastic arrays of microneedles include: “self-molding,” micromolding, microembossing, and microinjection techniques. In the “self-molding” method, a plastic (e.g.

Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.

Abstract: A plasma etching system using a ground electrode made of silicon carbide and a cover made of a dielectric material not containing aluminum, where the cover is laid over the substrate electrode, thereby preventing aluminum from being produced out of these parts and reducing device damage. Namely, a plasma etching system has a substrate electrode mounted in a vacuum process chamber, a ground electrode and a plasma generating source, and uses plasma to provide etching of substrates mounted on said substrate electrode. The plasma etching system is characterized in that the ground electrode is made of carbon or silicon carbide, and the dielectric material containing a Si compound covers the surface portion of the substrate electrode facing inside the substrate installation portion of the vacuum process chamber, except for the substrate installation portion.

Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: In a dry etching method for etching a structure obtained by successively depositing, on a substrate, a gate insulating film, a silicon base film, a tungsten film or an alloy film containing tungsten, the dry etching includes a first process of dry-etching the tungsten film or the alloy film including tungsten, and a second process of dry-etching the silicon base film, and the first process employs, as an etching gas, a gas mixture obtained by mixing O2 gas into a gas including at least C and F, with the flow ratio of the O2 gas being 10˜50% by volume percentages. This dry etching method realizes highly-precise dry etching by which a vertical configuration of the poly-metal structure is obtained, and the selection ratio of W with respect to poly-Si can be controlled and, moreover, penetration through the underlying gate oxide film is prevented.

Abstract: The slider according to the invention can prevent the phenomenon of sticking and reduce entrapping of foreign particles between the sliding surfaces. The method for making micro-protrusions or micro-cavities on a surface of a substrate comprises the steps of: placing the substrate in a process chamber; supporting a mask member, having a micro shielding surface, independent of and in front of the substrate; and irradiating fast atomic beams onto the surface of the substrate through the mask member.

Abstract: A method of etching an underlying inorganic substrate through a patterned photoresist, including exposing a structure comprising said inorganic substrate and patterned photoresist to a plasma etchant generated from a plasma source gas including at least one fluorine-comprising gas and sulfur dioxide (SO2). The amount of sulfur dioxide present in said plasma source gas may be varied during the etching process. The method is particularly useful when the photoresist is a DUV photoresist. One of the preferred embodiments of the method is the etching of silicon nitride (SiNx) through a DUV photoresist, where the plasma source gas used to provide the etchant includes at least one fluorine-comprising gas, argon, and sulfur dioxide. Other preferred fluorine-comprising gases include nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), and sulfur hexafluoride (SF6).

Abstract: A method of forming a line of FLASH memory cells includes forming a first line of floating gates over a crystalline silicon semiconductor substrate. An alternating series of SiO2 isolation regions and active areas are provided in the semiconductor substrate in a second line adjacent and along at least a portion of the first line of floating gates. The series of active areas define discrete transistor source areas. A masking layer is formed over the floating gates, the regions and the areas. A third line mask opening is formed in the masking layer over at least a portion of the second line. Anisotropic etching is conducted of the SiO2 isolation regions exposed through the third line mask opening substantially selectively relative to crystalline silicon exposed through the third line mask opening using a gas chemistry comprising a combination of at least one non-hydrogen containing fluorocarbon having at least three carbon atoms and at least one hydrogen containing fluorocarbon.

Abstract: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high aspect ratios can be etched.

Abstract: A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.