Abstract: Methods of etching dielectric materials in a semiconductor processing apparatus use a thick silicon upper electrode that can be operated at high power levels for an extended service life.

Abstract: A method of depositing a film on a substrate disposed in a substrate processing chamber. In one embodiment the method includes depositing a first portion of the film to at partially fill a gap formed between to adjacent features formed on the substrate. The first portion of film is deposited using a high density plasma formed from a first gaseous mixture flown into the process chamber. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a two step etching process that includes a first physical etch step and a subsequent chemical etch step. The physical etch step sputter etches the first portion of film by forming a plasma from a sputtering agent introduced into the processing chamber and biasing the plasma towards the substrate. After the physical etching step, the film is chemically etched by forming a plasma from a reactive etchant gas introduced into the processing chamber.

Abstract: The present invention relates to a method of manufacturing a piezoelectric device of high sensitivity using direct bonded quartz plate. To achieve this object, the invented method comprises the steps of covalently bonding a plurality of quartz plates, dry etching the bonded quartz plates with plasma from one side of its surfaces down to a bonded plane, and dry etching with plasma thereafter from the other side of the surfaces.

Abstract: A method of reducing notching during reactive ion etching (RIE) is provided. The method is useful when RIE is performed to pass through a silicon layer on a multi-layered structure on which the silicon layer, an insulating layer and a silicon substrate are sequentially deposited. The method includes the steps of: forming an insulating layer on a silicon substrate; forming trenches on the insulating layer to expose the silicon substrate; forming a silicon layer on the insulating layer to fill the trenches; and patterning the silicon layer to form first etch regions, which pass through the silicon layer, to include the trenches. According to the method, it is possible to remarkably reduce notching without depositing a metal layer, when a multi-layered structure including a silicon layer which is etched to be passed through during RIE is fabricated.

Abstract: A nozzle arrangement for an ink jet printhead includes a wafer substrate having a nozzle chamber defined therein. The nozzle arrangement has a nozzle chamber wall that defines an ink ejection port and a rim about the ink ejection port. A series of radially positioned actuators are connected to the wafer substrate and extend radially inwardly towards the rim. Each actuator is configured so that a radially inner edge of each actuator is displaceable, with respect to the nozzle rim, into the chamber, upon actuation of the actuator and so that, upon such displacement, a pressure within the nozzle chamber is increased, resulting in the ejection of ink from the ejection port.

Abstract: A method of etching a trench in a substrate using a dry plasma etch technique that allows precise control of lateral undercut. The method includes optionally forming at least one on-chip device or micro-machined structure in a surface of a silicon substrate, and covering the surface with a masking layer. A trench pattern is then imaged in or transferred to the masking layer for subsequent etching of the substrate. Upper portions of the trench are anisotropically etched in the substrate. The trench is then semi-anisotropically etched and isotropically etched in the substrate. By modifying isotropic etching time, a controlled lateral undercut can be achieved as the trench is etched vertically in the substrate.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: Disclosed are a processing method and apparatus for removing a native oxide film from the surface of a subject to be treated. In this method and apparatus, gas generated from N2, H2 and NF3 gases is reacted with the surface of the subject to degenerate the native oxide film into a reactive film. If the subject is heated to a given temperature, the reactive film is sublimated and thus the native oxide film is removed. Plasma is generated from the N2 and H2 gases and then activated to form an activated gas species. The NF3 gas is added to the activated gas species to generate an activated gas of these three gases. In the step of forming the reactive film, the subject is cooled to not higher than a predetermined temperature by a cooling means. In the step of sublimating the reactive film, the subject is lifted up to a predetermined heating position.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: A process for etching a substrate 25 in an etching chamber 30, and simultaneously cleaning a thin, non-homogeneous, etch residue deposited on the surfaces of the walls 45 and components of the etching chamber 30. In the etching step, process gas comprising etchant gas is used to etch a substrate 25 in the etching chamber 30 thereby depositing etch residue inside the chamber 30. Cleaning gas is added to the process gas for a sufficient time and in a volumetric flow ratio that is sufficiently high, to react with and remove substantially all the etch residue deposited by the process gas. The present method advantageously cleans the etch residue in the chamber 30, during the etching process, and without use of separate cleaning, conditioning, and seasoning process steps.

Abstract: A method for cleaning a contact area of a metal line wherein a nitride barrier layer is formed on a sidewall of an insulating interlayer within the contact area by introducing the nitrogen-based radical to the contact area, whereby it is possible to prevent a low dielectric insulating interlayer from becoming deteriorated by the redeposition of metal ions and by hydrogen radical activated during reactive cleaning, thereby maintaining a low dielectric characteristic of the insulating interlayer.

Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.

Abstract: A process for forming a microelectromechanical system (MEMS) device by a deep reactive ion etching (DRIE) process during which a substrate overlying a cavity is etched to form trenches that breach the cavity to delineate suspended structures. A first general feature of the process is to define suspended structures with a DRIE process, such that the dimensions desired for the suspended structures are obtained. A second general feature is the proper location of specialized features, such as stiction bumps, vulnerable to erosion caused by the DRIE process. Yet another general feature is to control the environment surrounding suspended structures delineated by DRIE in order to obtain their desired dimensions. A significant problem identified and solved by the invention is the propensity for the DRIE process to etch certain suspended features at different rates.

Abstract: Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.

Abstract: A bubble-jet type ink-jet printhead, a manufacturing method thereof and a method of ejecting ink, wherein, in the printhead, a manifold supplying ink, a hemispherical ink chamber, and an ink channel for connecting the manifold with the ink chamber are integrally formed on the substrate. A nozzle plate on the substrate having a nozzle, and a heater formed in an annular shape and centered around the nozzle are integrated without a complex process such as bonding. Thus, this simplifies the manufacturing process and facilitates high volume production. Furthermore, according to the ink ejection method, a doughnut-shaped bubble is formed to eject ink, thereby preventing a back flow of ink as well as formation of satellite droplets that may degrade image resolution.

Abstract: A method of forming a pattern in a layer of material on a substrate, comprising providing a plurality of spheres, covering the layer on the substrate with the plurality of spheres to form a mask, reducing the diameter of at least one sphere of the plurality of spheres, etching the layer on the substrate using at least one sphere having a reduced diameter as a mask, and etching the substrate.

Abstract: A method of micromechanically manufacturing fixed and movable layer-like electrodes of a semiconductor element, for example, a capacitive acceleration sensor, which are exposed over a substrate over a certain area is provided. A sacrificial layer may be arranged between the substrate and the fixed and movable electrodes being removed in an etching step in order to expose the electrodes with respect to the substrate. The thickness of the sacrificial layer located in the area of the fixed electrodes may be less than the thickness of the sacrificial layer located in the area of the movable electrodes.

Abstract: A method for manufacturing an ink-jet printhead having a hemispherical ink chamber, wherein a nozzle plate is formed on a surface of substrate; a heater is formed on the nozzle plate; a manifold for supplying ink; an electrode is formed on the nozzle plate to be electrically connected to the heater; a nozzle is formed by etching the nozzle plate inside the heater; a groove for forming an ink channel is formed to expose the substrate so that the groove extends from the outside of the heater toward the manifold; an ink chamber is formed to have a diameter greater than the diameter of the heater and be hemispherical by etching the substrate exposed by the nozzle; an ink channel is formed to be in flow communication with the ink chamber and the manifold; and the groove is closed by forming a material layer on the nozzle plate.

Abstract: A method of forming a contact in an integrated circuit between a first metalization layer and a silicon substrate. In one embodiment the method comprises forming a premetal dielectric layer over the silicon substrate, etching a contact hole through the premetal dielectric layer and then forming a thin silicon nitride layer on an outer surface of the contact hole. The silicon nitride layer reduces overetching that may otherwise occur when oxidation build-up is removed from the silicon interface within the contact hole by a preclean process. After the preclean process, the contact hole is then filled with one or more conductive materials. In various embodiments the silicon nitride layer is formed by exposing the contact hole to a nitrogen plasma, depositing the layer by a chemical vapor deposition process and depositing the layer by an atomic layer deposition process. In other embodiments, the method is applicable to the formation of vias through intermetal dielectric layers.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: A method of purging a semiconductor manufacturing apparatus comprises a step of etching a CVD-deposited film deposited in a chamber constituting a semiconductor manufacturing apparatus which has performed a process of forming a CVD film using a CVD process over a semiconductor wafer by using an etching gas containing at least a halogen gas, and a step of purging a cleaning gas remaining in the chamber by causing a gas containing hydrogen to flow into the chamber after the step of etching the CVD-deposited film by using the cleaning gas.

Abstract: A method of fabricating an STI structure comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. A hard mask layer is formed over the pad oxide layer. The hard mask layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure. The opening having exposed side walls. A spacer layer is formed over the patterned hard mask layer, the exposed side walls of the opening and lining the opening. The structure is subjected to an STI trench etching process to: (1) remove the spacer layer from over the patterned hard mask layer; form spacers over the side walls; (2) the spacers being formed in-situ from the spacer layer; and (3) etch an STI trench within the silicon structure wherein the spacers serve as masks during at least a portion of time in which the STI trench is formed. The STI trench having corners. Any remaining portion of the spacers are removed.

Abstract: An etching processing method capable of etching a low dielectric constant layer at a reduced cost by using an etching processing apparatus comprising a vacuum vessel, a sample loading electrode disposed in the vacuum vessel, a gas introduction device for introducing a reaction gas into the vacuum vessel, an antenna for forming plasmas in the vacuum vessel, and a high frequency power supply for supplying a bias power to a sample loaded on the sample loading electrode, wherein the bias power to be supplied to the sample is 3 W/cm2 or less, and the gas introduction device introduces a gas containing chlorine atoms or bromine atoms to apply etching processing to an inorganic insulation material of low dielectric constant loaded on the loading electrode.

Abstract: A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as vias to connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude toward each other. Thus, when the contacts are moved toward each other by actuating the MEM switch, they connect firmly without obstruction.

Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of “cycles” of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.

Abstract: A method is proposed for producing three-dimensional structures, especially microlenses, in a substrate using an etching process, at least one original shape having a known original surface shape being present initially on the substrate in a plurality of places. The etching process has at least one first etching removal rate a1 and a second etching removal rate a2 which are material-dependent, and of which at least one is changeable as a function of time. The original shape is converted to a target shape by the etching process, the original surface shape of the original shape and the target surface shape of the target shape to be reached being known before the beginning of the etching process. In order to achieve the target surface shape, at least one of the etching rates a2 or a1 is set by a change of at least one etching parameter calculated before the beginning of the etching process as a function of the etching time.

Abstract: This cleaning method and cleaning apparatus for a film deposition apparatus includes a processing container 4 accommodating a mounting table 10 for mounting an object W to be processed, a gas-introduction unit 52 for introducing a designated gas into the processing container, a vacuum exhausting system 36 for exhausting an atmosphere in the processing container in vacuum, and an automatic pressure regulating valve 42 interposed in the vacuum exhausting system so that a pressure in the processing container can be maintained at a constant value by changing an opening degree of the automatic pressure regulating valve.

Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

Abstract: Reactive atom plasma processing can be used to shape, polish, planarize, and clean surfaces of difficult materials with minimal subsurface damage. The apparatus and methods use a plasma torch, such as a conventional ICP torch. The workpiece and plasma torch are moved with respect to each other, whether by translating and/or rotating the workpiece, the plasma, or both. The plasma discharge from the torch can be used to shape, planarize, polish, clean and/or deposit material on the surface of the workpiece, as well as to thin the workpiece. The processing may cause minimal or no damage to the workpiece underneath the surface, and may involve removing material from, and/or redistributing material on, the surface of the workpiece.

Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.

Abstract: An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.

Abstract: An optical element which controls both the phase and irradiance distribution, thereby completely specifying the E-field, of light, allowing completely arbitrary control of the light at any plane. Such an optical element includes a portion that controls the phase and a portion that controls the irradiance. The portion that controls the irradiance is an apodized irradiance mask having its transmission varying with position in a controlled fashion. This apodized irradiance mask is preferably a pattern of metal. In order to insure a smoothly varying pattern of metal with minimized diffraction effects, a very thin mask spaced from a substrate is used to provide the metal on the substrate. The apodized irradiance mask may be placed directly on the phase control portion, or may be on an opposite side of a substrate of the phase controlled portion.

Abstract: Problems caused by a nonuniform processing profile are avoided by altering the area to be processed so as to compensate for the processing profile. More specifically, with regard to etching, problems caused by a nonuniform etch profile can be avoided by altering the mask employed in specifying the etch area so as to compensate for the etch profile. Nonuniform parameters of interest of structures which result from a nonuniform etch profile during the etching of a mask in which all the structures were identical can be avoided for by altering the mask employed in specifying the etch area so as to compensate for the etch profile. The mask is changed in a manner that is inversely proportional to the etch profile for each particular structure characteristic that determines the parameter of interest for which uniformity is desired.

Abstract: Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.

Abstract: A method of forming a manifold through a substrate of a printhead substructure is disclosed. The substrate has an ink reservoir-facing side and an opposing transducer-supporting side. The transducer-supporting side of the substrate is introduced to an etchant. A laser beam is used to irradiate the etchant contacting side of the substrate. The irradiated areas of the substrate are thereby etched to define a first portion of the manifold therein. A second portion of the manifold is formed, preferably by sand blasting, to connect to the first portion. A printhead substructure that includes a substrate having a manifold formed according to the method is also disclosed.

Abstract: A tool for embossing high aspect ratio microstructures is provided, wherein the microstructures provide decreased surface reflection and increased transmission through an optical component. The tool is fabricated by a process that comprises etching columnar pits in a silicon substrate using inductively coupled plasma, followed by reactive ion etching of the columnar pits to create relatively pointed obelisks. The silicon substrate is then preferably rinsed prior to vapor depositing a conductive layer thereon. Finally, a metal is electroformed over the conductive layer to form the embossing tool. The embossing tool is then pressed against an optical coating, for example a polymer sheet, to create microstructures having aspect ratios from 1 to 5.

Abstract: A method of forming an emitter electrode of a bipolar transistor. The emitter electrode includes a double-layered structure of a polysilicon layer and a refractory metal silicide layer. The method includes the steps of removing a natural oxide film from a surface of a polysilicon layer by a sputter-etching process using inert gas ions in the range of acceleration energy from 5 eV to 50 eV; depositing a refractory metal layer on the surface of the polysilicon layer; and carrying out a heat treatment to cause a silicidation reaction to form a refractory metal silicide layer over the polysilicon layer.

Abstract: At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited in said cavity to preclude diffusion of copper 7. The protective layer 7 at the bottom of the cavity 6 is subjected to an anisotropic etching treatment and also the encapsulation layer 2 is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching the encapsulation layer do not contaminate the dielectric material 3.

Abstract: Methods for making a micromachined device (e.g. an microoptical submount) having positive features (extending up from a device surface) and negative features (extending into the device surface). The present techniques locate the postive feature and negative features according to a single mask step. In one embodiment, a hard mask is patterned on top of the device layer of an SOI wafer. Then, RIE is used to vertically etch to the etch stop layer, forming the positive feature. Then, the positive feature is masked, and metal or hard mask is deposited on the exposed areas of the etch stop layer. Then, portions of the device layer are removed, leaving the patterned metal layer on the etch stop layer. Then, the etch stop layer is removed in an exposed area, uncovering the handle layer. Then, the handle layer is etched in an exposed area to form the negative feature.

Abstract: A method of forming via hole metal layers, including the steps of forming via holes in a Si layer by etching an SOI substrate having a SiO2 layer and the Si layer formed on a Si substrate in order of precedence, the via holes being extended to the SiO2 layer, and forming the via hole metal layers in the via holes.

Abstract: A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF6 and Ar, the volumetric flow ratio of SF6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF4 and Ar, the volumetric flow ratio of CF4 to other components of the second process gas being from about 1:0 to about 1:10.

Abstract: An oxide etching process, particular useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention preferably uses the unsaturated 4-carbon fluorocarbons, specifically hexafluorobutadiene (C4F6), which has a below 10°C. and is commercially available. The hexafluorobutadiene together with argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. Preferably, a two-step etch is used process is used in which the above etching gas is used in the main step to provide a good vertical profile and a more strongly polymerizing fluorocarbon such as difluoromethane (CH2F2) is added in the over etch to protect the nitride corner.

Abstract: The invention concerns a method for treating a surface for the protection and functionalisation of polymers (4) by gas plasma deposit in a confined chamber (10) of one or several silicon alloy layers (43). The silicon alloy is selected among silicon and its oxides, nitrides, oxynitrides; the deposit is performed at a temperature less than the degradation temperature of the polymer, and a physico—chemical surface pre-treatment by plasma is performed in the same chamber before the silicon alloy is deposited; the pre-treatment consisting in a surface treatment comprising etching a surface zone of the polymer and step which consists in depositing a polymeric carbon compound.

Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: A phase shifting mask repair process is described. The process uses an etching gas or a hydrofluoric acid solution to etch the quartz substrate and the characteristics of the phase shifter layer being only slightly etched when clean with a NH3/H2O2/H2O2 solution to calculate and adjust the respective processing time accordingly. As a result, the phase difference between the quartz substrate and the MoSiON phase shifter layer stays relatively the same before and after the repair process.

Abstract: We have discovered a method for plasma etching a carbon-containing silicon oxide film which provides excellent etch profile control, a rapid etch rate of the carbon-containing silicon oxide film, and high selectivity for etching the carbon-containing silicon oxide film preferentially to an overlying photoresist masking material. When the method of the invention is used, a higher carbon content in the carbon-containing silicon oxide film results in a faster etch rate, at least up to a carbon content of 20 atomic percent. In particular, the carbon-containing silicon oxide film is plasma etched using a plasma generated from a source gas comprising NH3 and CxFy. It is necessary to achieve the proper balance between the relative amounts of NH3 and CxFy in the plasma source gas in order to provide a balance between etch by-product polymer deposition and removal on various surfaces of the substrate being etched.

Abstract: A processing gas constituted of C5F8, O2 and Ar achieving a flow rate ratio of 1≦C5F8 flow rate/O2 flow rate≦1.625 is supplied into a processing chamber 102 of an etching apparatus 100 and the atmosphere pressure is set within a range of 45 mTorr˜50 mTorr. High-frequency power is applied to a lower electrode 110 sustained within a temperature range of 20° C.˜40° C. on which a wafer W is mounted to raise the processing gas to plasma, and using the plasma, a contact hole 210 is formed at an SiO2 film 208 on an SiNx film 206 formed at the wafer W. The use of C5F8 and O2 makes it possible to form a contact hole 210 achieving near-perfect verticality at the SiO2 film 208 and also improves the selection ratio of the SiO2 film 208 relative to the SiNx film 206. C5F8, which becomes decomposed over a short period of time when released into the atmosphere, does not induce the greenhouse effect.

Abstract: An oxide etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. One aspect of the invention uses one of four hydrogen-free fluorocarbons having a low F/C ratio, specifically hexafluorobutadiene (C4F6), octafluoropentadiene (C5F8), hexafluorocyclobutene (C4F6), and hexafluorobenzene (C6F6). At least hexafluorobutadiene has a boiling point below 10° C. and is commercially available. Another aspect of the invention, uses an unsaturated fluorocarbon such as pentafluoropropylene (C3HF5), and trifluoropropyne (C3HF3), both of which have boiling points below 10° C. and are commercially available.

Abstract: A method in which etching or ashing is conducted by providing satisfactory kinetic energy of reaction seeds such as ions or radicals without damaging a substrate, and an apparatus used in this method are provided. A predetermined film of for example polycrystalline silicon on the substrate is etched in vapor phase using reaction seeds or precursors thereof generated by contacting a reaction gas such as CF4 with a heated catalyst of for example tungsten.

Abstract: A method for SAC etching is provided involving a) etching a Si wafer having a nitride present thereon with a first etching gas containing a first perfluorocarbon and carbon monoxide, and b) etching the resultant Si wafer having an initially etched nitride photoresist thereon with a second etching gas containing a second perfluorocarbon in the substantial absence of carbon monoxide, wherein the etching steps a) and b) are performed at high RF power and low pressure compared to conventional processes to provide higher selectivity etching and a larger process window for SAC etching, as well as the ability to perform SAC etching and island contact etching under the same conditions with high verticality of the island contact and SAC walls.