Silicon Containing Substrate Is Glass Patents (Class 216/80)
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Patent number: 10866504Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.Type: GrantFiled: December 22, 2017Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
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Patent number: 10679868Abstract: Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of NO activation of an oxide surface. Once activated, a fluorine-containing gas or vapor etches the activated surface. Etching is self-limiting as once the activated surface is removed, etching stops since the fluorine species does not spontaneously react with the un-activated oxide surface. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where accurate removal of one or multiple atomic layers of material is desired.Type: GrantFiled: July 21, 2016Date of Patent: June 9, 2020Assignee: LAM RESEARCH CORPORATIONInventors: Ivan L. Berry, III, Pilyeon Park, Faisal Yaqoob
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Patent number: 9963381Abstract: Embodiments of the present invention provide a method for finishing a glass product including a glass layer, the glass layer comprising boron. The method includes the step of cleaning the glass layer in order to remove boron at least at the surface of the glass layer. The step of cleaning includes the substep of esterification using a medium comprising an alcohol.Type: GrantFiled: July 24, 2015Date of Patent: May 8, 2018Assignee: INFINEON TECHNOLOGIES AGInventors: David Baum, Kurt Sorschag, Martin Kulterer
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Patent number: 9960031Abstract: In a plasma processing apparatus comprising a processing chamber arranged in a vacuum chamber, a sample stage arranged under the processing chamber and having its top surface on which a wafer to be processed is mounted, a vacuum decompression unit for evacuating the interior of the processing chamber to reduce the pressure therein, and introduction holes arranged above said sample stage to admit process gas into the processing chamber, the wafer having its top surface mounted with a film structure and the film structure being etched by using plasma formed by using the process gas, the film structure is constituted by having a resist film or a mask film, a poly-silicon film and an insulation film laminated in this order from top to bottom on a substrate and before the wafer is mounted on the sample stage and the poly-silicon film underlying the mask film is etched, plasma is formed inside the processing chamber to cover the surface of members inside the processing chamber with a coating film containing a compoType: GrantFiled: October 14, 2016Date of Patent: May 1, 2018Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Masahiro Sumiya, Motohiro Tanaka
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Patent number: 9017571Abstract: A dry etching agent according to the present invention preferably contains: (A) 1,3,3,3-tetrafluoropropene; (B) at least one kind of additive gas selected from the group consisting of H2, O2, O3, CO, CO2, COCl2, COF2, CF3OF, NO2, F2, NF3, Cl2, Br2, I2, CH4, C2H2, C2H4, C2H6, C3H4, C3H6, C3H8, HF, HI, HBr, HCl, NO, NH3 and YFn (where Y represents Cl, Br or I; and n represents an integer satisfying 1?n?7); and (C) an inert gas. This dry etching agent has less effect on the global environment and can obtain a significant improvement in process window and address processing requirements such as low side etching ratio and high aspect ratio even without any special substrate excitation operation.Type: GrantFiled: June 24, 2011Date of Patent: April 28, 2015Assignee: Central Glass Company, LimitedInventors: Tomonori Umezaki, Yasuo Hibino, Isamu Mori, Satoru Okamoto, Akiou Kikuchi
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Patent number: 9017566Abstract: A glass article including: at least one anti-glare surface having haze, distinctness-of-image, surface roughness, and uniformity properties, as defined herein. A method of making the glass article includes, for example: depositing deformable particles on at least a portion of a glass surface of the article; causing the deposited deformable particles on the surface to deform and adhere to the surface; and contacting the surface having the adhered particles with an etchant to form the anti-glare surface. A display system that incorporates the glass article, as defined herein, is also disclosed.Type: GrantFiled: October 11, 2011Date of Patent: April 28, 2015Assignee: Corning IncorporatedInventors: Charles Warren Lander, Timothy Edward Myers, Kelvin Nguyen, Alan Thomas Stephens, II
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Patent number: 8992789Abstract: According to one embodiment, a method is disclosed for manufacturing a mold. The method can include forming a second major surface receded from a first major surface by irradiating a portion of the first major surface with a charged beam to etch a base material having the first major surface. The method can include forming a mask pattern on the first major surface and the second major surface. In addition, the method can include forming a first pattern on the first major surface and a second pattern on the second major surface by etching the base material through the mask pattern.Type: GrantFiled: February 28, 2013Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masato Suzuki, Tetsuro Nakasugi
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Patent number: 8932406Abstract: The molecular etcher carbonyl fluoride (COF2) or any of its variants, are provided for, according to the present invention, to increase the efficiency of etching and/or cleaning and/or removal of materials such as the unwanted film and/or deposits on the chamber walls and other components in a process chamber or substrate (collectively referred to herein as “materials”). The methods of the present invention involve igniting and sustaining a plasma, whether it is a remote or in-situ plasma, by stepwise addition of additives, such as but not limited to, a saturated, unsaturated or partially unsaturated perfluorocarbon compound (PFC) having the general formula (CyFz) and/or an oxide of carbon (COx) to a nitrogen trifluoride (NF3) plasma into a chemical deposition chamber (CVD) chamber, thereby generating COF2. The NF3 may be excited in a plasma inside the CVD chamber or in a remote plasma region upstream from the CVD chamber.Type: GrantFiled: March 15, 2013Date of Patent: January 13, 2015Assignee: Matheson Tri-Gas, Inc.Inventors: Glenn Mitchell, Ramkumar Subramanian, Carrie L. Wyse, Robert Torres, Jr.
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Patent number: 8894868Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.Type: GrantFiled: October 6, 2011Date of Patent: November 25, 2014Assignee: Electro Scientific Industries, Inc.Inventors: Andy Hooper, Daragh Finn, Tim Webb, Lynn Sheehan, Kenneth Pettigrew, Yu Chong Tai
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Patent number: 8828244Abstract: A method for making a support of at least one substrate, including: making a stack including at least two substrates, each of the two substrates including two opposite main faces, both substrates being secured to each other such that one of the main faces of a first of the two substrates is positioned facing one of the main faces of the second of the two substrates and against an etch-stop material; etching, through the first of the two substrates and with stop on the etch-stop material, at least one location that can receive a substrate that can be supported by the support.Type: GrantFiled: May 19, 2011Date of Patent: September 9, 2014Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Frank Fournel, Laurent Bally, Marc Zussy, Dominique Jourde
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Patent number: 8806738Abstract: A method for manufacturing a quartz crystal unit, comprising the steps of forming a quartz crystal tuning fork shape having a quartz crystal tuning fork base, and first and second quartz crystal tuning fork tines, a quartz crystal tuning fork resonator having the quartz crystal tuning fork shape, forming at least one groove in at least one of opposite main surfaces of each of the first and second quartz crystal tuning fork tines, determining each of a length of the at least one groove and an overall length of the quartz crystal tuning fork resonator so that a series resistance R1 of a fundamental mode of vibration of the quartz crystal tuning fork resonator is less than a series resistance R2 of a second overtone mode of vibration thereof, housing the quartz crystal tuning fork resonator in a case, connecting a lid to the case, and disposing a metal or a glass in a through-hole of the case.Type: GrantFiled: February 15, 2013Date of Patent: August 19, 2014Assignee: Piedek Technical LaboratoryInventor: Hirofumi Kawashima
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Patent number: 8790529Abstract: A gas supply system for supplying a gas into a processing chamber for processing a substrate to be processed includes: a processing gas supply unit; a processing gas supply line; a first and a second branch line; a branch flow control unit; an additional gas supply unit; an additional gas supply line; and a control unit. The control unit performs, before processing the substrate to be processed, a processing gas supply control and an additional gas supply control by using the processing gas supply unit and the additional gas supply unit, respectively, wherein the additional gas supply control includes a control that supplies the additional gas at an initial flow rate greater than a set flow rate and then at the set flow rate after a lapse of a period of time.Type: GrantFiled: January 24, 2011Date of Patent: July 29, 2014Assignee: Tokyo Electron LimitedInventors: Shinichiro Hayasaka, Ken Horiuchi, Fumiko Yagi, Takeshi Yokouchi
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Publication number: 20140037920Abstract: A hard-to-dry-etch material may be patterned by forming a layer of dry-etchable material on a surface of the hard-to-dry etch substrate, and dry etching the dry-etchable material. The hard-to-dry etch substrate produces substantial quantities of non-volatile etch byproducts that redeposit when subject to the dry etching. The dry-etchable material has similar material properties to the hard-to-dry-etch substrate material is formed. The dry-etchable material is one that does not produce substantial quantities of non-volatile etch byproducts that redeposit when the dry-etchable material is subject to the dry etching. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: ApplicationFiled: August 1, 2012Publication date: February 6, 2014Applicant: Rolith, Inc.Inventor: Boris Kobrin
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Patent number: 8592315Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.Type: GrantFiled: February 24, 2010Date of Patent: November 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Keun Kim, Chung-Ki Min, Yong-Sun Ko, Kyung-Hyun Kim
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Patent number: 8568600Abstract: A method of manufacturing touch screen panels includes forming a photoresist film on a first surface of a substrate having high transmittance, removing the photoresist film in regions between unit cells by utilizing exposing and developing processes, etching the substrate in the regions where the photoresist film has been removed, removing the photoresist film from the substrate after the etching, performing a tempering process on the substrate including the etched regions, forming touch screen panels at the unit cells defined by the etched regions on the first surface of the substrate, and cutting the substrate at the etched regions to separate the touch screen panels.Type: GrantFiled: December 4, 2009Date of Patent: October 29, 2013Assignee: Samsung Display Co., Ltd.Inventors: Sung-Ku Kang, Jung-Mok Park
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Patent number: 8535551Abstract: A plasma etching method includes plasma-etching a silicon oxide layer through a mask using a process gas, the process gas containing oxygen gas and a fluorohydrocarbon shown by the formula (1), CxHyFz, wherein x is an integer from 4 to 6, y is an integer from 1 to 4, and z is a positive integer, provided that (y+z) is 2x or less. A contact hole having a very small diameter and a high aspect ratio can be formed in a substantially vertical shape without necking by plasma-etching the silicon oxide layer using a single process gas.Type: GrantFiled: September 26, 2008Date of Patent: September 17, 2013Assignee: Zeon CorporationInventors: Takefumi Suzuki, Tatsuya Sugimoto, Masahiro Nakamura
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Patent number: 8501020Abstract: A method for making a three-dimensional nano-structure array includes following steps. First, a substrate is provided. Next, a mask is formed on the substrate. The mask is a monolayer nanosphere array or a film defining a number of holes arranged in an array. The mask is then tailored and simultaneously the substrate is etched by the mask. Lastly, the mask is removed.Type: GrantFiled: December 16, 2010Date of Patent: August 6, 2013Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Zhen-Dong Zhu, Qun-Qing Li, Shou-Shan Fan
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Patent number: 8497211Abstract: A method of depositing a phosphosilicate glass (PSG) film on a substrate disposed in a substrate processing chamber includes depositing a first portion of the PSG film over the substrate using a high-density plasma process. Thereafter, a portion of the first portion of the PSG film may be etched back. The etch back process may include flowing a halogen precursor to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the etch back. The method also includes flowing a halogen scavenger to the substrate processing chamber to react with residual halogen in the substrate processing chamber, and exposing the first portion of the PSG film to a phosphorus-containing gas to provide a substantially uniform phosphorus concentration throughout the first portion of the PSG film.Type: GrantFiled: June 6, 2012Date of Patent: July 30, 2013Assignee: Applied Materials, Inc.Inventors: Young S. Lee, Anchuan Wang, Lan Chia Chan, Shankar Venkataraman
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Patent number: 8435902Abstract: A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.Type: GrantFiled: December 2, 2010Date of Patent: May 7, 2013Assignee: Applied Materials, Inc.Inventors: Jing Tang, Nitin Ingle, Dongqing Yang, Shankar Venkataraman
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Patent number: 8429809Abstract: A method for manufacturing a mirror device is presented. The method includes forming a mirror from a first substrate and forming a hinge/support structure from a second substrate. The hinge/support structure is formed with a recessed region and a torsional hinge region. The mirror is attached to the hinge/support structure at the recessed region. Further, a driver system is employed to cause the mirror to pivot about the torsional hinge region.Type: GrantFiled: January 10, 2012Date of Patent: April 30, 2013Assignee: Texas Instruments IncorporatedInventor: John W. Orcutt
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Patent number: 8414787Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation. In one example an electron beam array such as a carbon nanotube array is used to selectively expose a surface during a processing operation.Type: GrantFiled: May 14, 2010Date of Patent: April 9, 2013Assignee: Micron Technology, Inc.Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu
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Patent number: 8375559Abstract: A method of manufacturing a quartz crystal unit comprises disposing a metal film on opposite surfaces of a quartz crystal wafer and then etching the wafer to form a two-line tuning fork resonator vibratable in a flexural mode of an inverse phase. A groove is formed in the opposite main surfaces of both tines, and the length of each groove is determined relative to the length of the resonator so that the series resistance of the fundamental mode of vibration of the resonator is less than the series resistance of the second overtone mode of vibration thereof. The resonator is then mounted in case after which the resonant frequency of the resonator is adjusted.Type: GrantFiled: November 10, 2010Date of Patent: February 19, 2013Assignee: Piedek Technical LaboratoryInventor: Hirofumi Kawashima
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Patent number: 8372756Abstract: A process for selectively etching a material comprising SiO2 over silicon, the method comprising the steps of: placing a silicon substrate comprising a layer of a material comprising SiO2 within a reactor chamber equipped with an energy source; creating a vacuum within the chamber; introducing into the reactor chamber a reactive gas mixture comprising a fluorine compound, a polymerizable fluorocarbon, and an inert gas, wherein the reactive gas mixture is substantially free of added oxygen; activating the energy source to form a plasma activated reactive etching gas mixture within the chamber; and selectively etching the material comprising SiO2 preferentially to the silicon substrate.Type: GrantFiled: July 16, 2009Date of Patent: February 12, 2013Assignee: Air Products and Chemicals, Inc.Inventors: Glenn Michael Mitchell, Stephen Andrew Motika, Andrew David Johnson
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Patent number: 8361233Abstract: The present invention provides a glass support system, including methods and equipment for supporting a glass substrate on a column of air. The disclosed glass alignment equipment may be used to prevent or reduce defects or contamination on the surface of a glass substrate which may arise when the glass is aligned prior to etching. In particular, a support pin of the present invention may be used with an air circulation system to support or align glass over a column of air so as to reduce or prevent defects or contamination on the glass in dry etching processes used in the manufacturing of LCDs and other devices.Type: GrantFiled: June 23, 2005Date of Patent: January 29, 2013Assignee: LG Display Co., Ltd.Inventor: Hyuk Min Kwon
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Manufacturing method of flexible display panel and manufacturing method of electro-optical apparatus
Patent number: 8298431Abstract: A first etching stop layer and an active layer are formed on an inner surface of a first glass substrate, and a second etching stop layer and a cover layer are formed on an inner surface of a second glass substrate. A display media is formed between the first glass substrate and the second glass substrate. A first passivation layer is formed on an outer surface of the second glass substrate. A first etching process is performed to expose the first etching stop layer. A first flexible substrate is formed on the exposed first etching stop layer, and a second passivation layer is formed on the first flexible substrate. The first passivation layer is removed. A second etching process is performed to expose the second etching stop layer. A second flexible substrate is formed on the exposed second etching stop layer, and the second passivation layer is removed.Type: GrantFiled: December 8, 2008Date of Patent: October 30, 2012Assignee: Au Optronics CorporationInventors: Jong-Wen Chwu, Chao-Cheng Lin, Che-Yao Wu, Yu-Chen Liu, Wei-Chieh Yang -
Patent number: 8246846Abstract: A method for fabricating integrated MEMS switches and filters includes forming cavities in a silicon substrate, metalizing a first pattern on a quartz substrate to form first switch and filter elements, bonding the quartz substrate to the silicon substrate so that the first switch and filter elements are located within one of the cavities, thinning the quartz substrate, forming conductive vias in the quartz substrate, metalizing a second pattern on a second surface of the quartz substrate to form second switch and filter elements, etching the quartz substrate to separate MEMS switches from filters, forming protrusions on a host substrate, metalizing a third metal pattern on the host substrate to form metal anchors and third switch elements, compression bonding the metal anchors on the host substrate to second switch and filter elements, forming signal lines to integrate the MEMS switches and filters and removing the silicon substrate.Type: GrantFiled: September 24, 2010Date of Patent: August 21, 2012Assignee: HRL Laboratories, LLCInventors: David T. Chang, Tsung-Yuan Hsu
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Patent number: 8240023Abstract: A method for manufacturing a quartz crystal unit comprises the steps of forming a quartz crystal tuning fork resonator vibratable in a flexural mode of an inverse phase and having a quartz crystal tuning fork base and first and second quartz crystal tuning fork tines connected to the quartz crystal tuning fork base, forming at least one groove having at least three stepped portions in at least one of opposite main surfaces of each of first and second quartz crystal tuning fork tines, disposing an electrode on a surface of one of the at least three stepped portions of the at least one groove and an electrode on one of opposite side surfaces of each of the first and second quartz crystal tuning fork tines, mounting the quartz crystal tuning fork resonator on a mounting portion of a case, and connecting a lid to the case to cover an open end of the case, wherein the step of forming the quartz crystal tuning fork base and the first and second quartz crystal tuning fork tines is performed before the step of forminType: GrantFiled: April 16, 2009Date of Patent: August 14, 2012Assignee: Piedek Technical LaboratoryInventor: Hirofumi Kawashima
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Patent number: 8226837Abstract: A process for producing through simple operations a molding die for optical device having an antireflective structure of nano-order microscopic uneven plane on a substratum surface. The molding die for optical device having microscopic uneven plane (antireflective structure die plane) on a surface of substratum is produced by a process comprising forming one or more etching transfer layers on substratum; forming thin film for formation of semispherical microparticles on the etching transfer layers; causing the thin film to undergo aggregation, or decomposition, or nucleation of the material by the use of any of thermal reaction, photoreaction and gas reaction or a combination of these reactions so as to form multiple semispherical islandlike microparticles; and using the multiple islandlike microparticles as a protective mask, carrying out sequential etching of the etching transfer layers and substratum by reactive gas to thereby form a conical pattern on the microscopic surface of the substratum.Type: GrantFiled: October 2, 2007Date of Patent: July 24, 2012Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Kazuma Kurihara, Takayuki Shima, Junji Tominaga
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Patent number: 8182708Abstract: The present invention is to provide a method by which the waviness generated in a glass substrate surface during pre-polishing are removed and the glass substrate is finished so as to have a highly flat surface. The present invention relates a method of finishing a pre-polished glass substrate surface, the glass substrate being made of quartz glass containing a dopant and comprising SiO2 as a main component, the finishing method comprising: measuring a concentration distribution of the dopant contained in the glass substrate; and measuring a surface shape of the glass substrate in the pre-polished state, wherein conditions for processing the glass substrate surface are set for each part of the glass substrate based on the measurement results of the concentration distribution of the dopant and the surface shape of the glass substrate.Type: GrantFiled: December 14, 2007Date of Patent: May 22, 2012Assignee: Asahi Glass Company, LimitedInventor: Koji Otsuka
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Patent number: 8177990Abstract: Disclosed is a method of etching a substrate having a layered structure in which a photoresist mask with a pattern, a coating film made of silicon oxide, and an organic film are laminated in that order from the top. Before etching the coating film of silicon oxide, a deposit is deposited on the photoresist mask by using plasma generated from a hydrocarbon gas such as CH4 gas so as to narrow the size of openings in the pattern of the photoresist mask. The pattern of the photoresist mask is well transferred to the organic film through the coating film, and a pattern with openings having a high aspect ratio can be formed in the organic film and toppling of the pattern in the organic film can be prevented. The organic film with the transferred pattern is used as an etch mask for etching the underlying layer.Type: GrantFiled: March 29, 2007Date of Patent: May 15, 2012Assignee: Tokyo Electron LimitedInventors: Ryou Mochizuki, Jun Yashiro
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Patent number: 8173030Abstract: A method for forming a self-aligned hole through a substrate to form a fluid feed passage is provided by initially forming an insulating layer on a first side of a substrate having two opposing sides; and forming a feature on the insulating layer. Next, etch an opening through the insulating layer, such that the opening is physically aligned with the feature on the insulating layer; and coat the feature with a layer of protective material. Patterning the layer of protective material will expose the opening through the insulating layer. Dry etching from the first side of the substrate forms a blind feed hole in the substrate corresponding to the location of the opening in the insulating layer, the blind feed hole including a bottom. Subsequently, grind a second side of the substrate and blanket etch it to form a hole through the entire substrate.Type: GrantFiled: September 30, 2008Date of Patent: May 8, 2012Assignee: Eastman Kodak CompanyInventors: John Andrew Lebens, Weibin Zhang, Christopher Newell Delametter
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Patent number: 8153016Abstract: The fabrication of a touch sensor panel having co-planar single-layer touch sensors fabricated on the back side of a cover glass is disclosed. It can be desirable from a manufacturing perspective to perform all thin-film processing steps on a motherglass before separating it into separate parts. To perform thin-film processing on a motherglass before separation, a removable sacrificial layer such as a photoresist can be applied over the thin-film layers. Next, the motherglass can be scribed and separated, and grinding and polishing steps can be performed prior to removing the sacrificial layer. In alternative embodiments, after the protective sacrificial layer is applied, the bulk of the coverglass can be dry-etched using a very aggressive anisotropic etching that etches primarily in the z-direction. In this embodiment, the etching can be patterned using photolithography to create rounded corners or any other shape. The photoresist can then be removed.Type: GrantFiled: February 12, 2008Date of Patent: April 10, 2012Assignee: Apple Inc.Inventors: Steve Porter Hotelling, John Z. Zhong, Joseph Edward Clayton
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Patent number: 8127426Abstract: An electronic apparatus has a display portion, and first and second oscillating circuits each having a quartz crystal resonator, the quartz crystal resonator of each of the first and second oscillating circuits vibrating in a different mode from each other. One of the quartz crystal resonators is a quartz crystal tuning fork resonator having first and second tuning fork tines. Electrodes are disposed on side surfaces of each of the first and second tuning fork tines so that the electrodes of the first tuning fork tine have an electrical polarity opposite to an electrical polarity of the electrodes of the second tuning fork tine. The capacitance ratio r1 of a fundamental mode of vibration of the quartz crystal tuning fork resonator is less than a capacitance ratio r2 of a second overtone mode of vibration thereof. An output signal of the oscillating circuit having the quartz crystal tuning fork resonator is a clock signal used to display time information at the display portion of the electronic apparatus.Type: GrantFiled: July 21, 2008Date of Patent: March 6, 2012Assignee: Piedek Technical LaboratoryInventor: Hirofumi Kawashima
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Patent number: 8122587Abstract: A method for manufacturing a quartz crystal unit comprises the steps of adjusting an oscillation frequency of a quartz crystal tuning fork resonator that is vibratable in a flexural mode of an inverse phrase and that has first and second quartz crystal tuning fork tines, forming at least one groove in each of two of opposite main surfaces of each of first and second quartz crystal tuning fork tines, disposing an electrode on a surface of the at least one groove formed in each of two of the opposite main surfaces and each of two of opposite side surfaces of each of the first and second quartz crystal tuning fork tines so that the electrodes of the grooves of the first quartz crystal tuning fork tine are connected to the electrodes of the side surfaces of the second quartz crystal tuning fork tine and the electrodes of the grooves of the second quartz crystal tuning fork tine are connected to the electrodes of the side surfaces of the first quartz crystal tuning fork tine, the quartz crystal tuning fork resonatType: GrantFiled: April 16, 2009Date of Patent: February 28, 2012Assignee: Piedek Technical LaboratoryInventor: Hirofumi Kawashima
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Patent number: 8119019Abstract: A method of fabricating a printhead ejection nozzle is provided which includes depositing sacrificial material on a planar substrate form a scaffold of the sacrificial material on the substrate, defining openings in the sacrificial material to the plane of the substrate at positions for sidewalls of a nozzle chamber and a filter structure for the nozzle chamber, depositing roof material over, and into the openings of, the sacrificial material so as to form the sidewalls of the nozzle chamber on the substrate, a roof of the nozzle chamber bridging the sidewalls, and the filter structure, etching the roof material to the sacrificial material to form a nozzle aperture through the roof of the nozzle chamber, and removing the sacrificial material.Type: GrantFiled: November 27, 2008Date of Patent: February 21, 2012Assignee: Silverbrook Research Pty LtdInventor: Kia Silverbrook
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Patent number: 8088296Abstract: The present invention prevents drop in the function of a plasma processing device caused by reduction of a plasma generating chamber by reductive plasma that is generated from the introduced process gas, and extends the life of members which are in contact with reductive plasma, especially the plasma generating chamber member. The plasma processing device of this embodiment is a device for treating the surface of a processing subject S using radicals generated by exciting a process gas, wherein a plasma generating chamber member 6, having a internal plasma generating chamber 6a, is connected to a gas introduction tube 5 attached to the outside of the process chamber 1, and a gas regulator 7 is provided on the end of the plasma generating chamber member 6.Type: GrantFiled: May 19, 2005Date of Patent: January 3, 2012Assignee: Shibaura Mechatronics CorporationInventor: Katsuhiro Yamazaki
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Patent number: 8088297Abstract: The present invention relates firstly to HF/fluoride-free etching and doping media which are suitable both for the etching of silicon dioxide layers and also for the doping of underlying silicon layers. The present invention also relates secondly to a process in which these media are employed.Type: GrantFiled: June 13, 2006Date of Patent: January 3, 2012Assignee: Merck Patent GmbHInventors: Armin Kuebelbeck, Werner Stockum
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Patent number: 8069549Abstract: A quartz crystal device includes a crystal resonator element and a package including a plurality of components. The plurality of components are bonded using a metal paste sealing material containing a metallic particle having an average particle size from 0.1 to 1.0 ?m, an organic solvent, and a resin material in proportions of from 88 to 93 percent by weight from 5 to 15 percent by weight, and from 0.01 to 4.0 percent by weight, respectively, to hermetically seal the crystal resonator element in the package.Type: GrantFiled: March 19, 2008Date of Patent: December 6, 2011Assignee: Seiko Epson CorporationInventors: Yoji Nagano, Tatsuya Anzai, Hideo Tanaya
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Patent number: 8070973Abstract: Apparatus including: a substrate layer having a substantially planar top surface; an optically conductive peak located and elongated on, and spanning a first thickness measured in a direction generally away from, the top surface; the optically conductive peak having first and second lateral walls each including distal and proximal lateral wall portions, the proximal lateral wall portions intersecting the top surface; and first and second sidewall layers located on the distal lateral wall portions, the sidewall layers not intersecting the top surface and spanning a second thickness that is less than the first thickness measured in the same direction.Type: GrantFiled: September 29, 2008Date of Patent: December 6, 2011Assignee: Alcatel LucentInventors: Young-Kai Chen, Andreas Bertold Leven, Yang Yang
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Patent number: 8062536Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: March 22, 2010Date of Patent: November 22, 2011Assignee: United Microelectronics Corp.Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Patent number: 8057690Abstract: Methods for creating at least one micro-electromechanical (MEMS) structure in a silicon-on-insulator (SOI) wafer. The SOI wafer with an extra layer of oxide is etched according to a predefined pattern. A layer of oxide is deposited over exposed surfaces. An etchant selectively removes the oxide to expose the SOI wafer substrate. A portion of the SOI substrate under at least one MEMS structure is removed, thereby releasing the MEMS structure to be used in the formation of an accelerometer.Type: GrantFiled: March 11, 2009Date of Patent: November 15, 2011Assignee: Honeywell International Inc.Inventor: Lianzhong Yu
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Patent number: 8043972Abstract: Methods for accurate and conformal removal of atomic layers of materials make use of the self-limiting nature of adsorption of at least one reactant on the substrate surface. In certain embodiments, a first reactant is introduced to the substrate in step (a) and is adsorbed on the substrate surface until the surface is partially or fully saturated. A second reactant is then added in step (b), reacting with the adsorbed layer of the first reactant to form an etchant. The amount of an etchant, and, consequently, the amount of etched material is limited by the amount of adsorbed first reactant. By repeating steps (a) and (b), controlled atomic-scale etching of material is achieved. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where removal of one or multiple atomic layers of material is desired.Type: GrantFiled: July 16, 2008Date of Patent: October 25, 2011Assignee: Novellus Systems, Inc.Inventors: Xinye Liu, Joshua Collins, Kaihan A. Ashtiani
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Patent number: 8038892Abstract: The removal of partial areas of a coating (11, 12) on at least one surface (37, 38) of a glass pane (2) takes place by means of a plasma jet (14, 15) which emerges from a plasma nozzle (5, 6). The plasma nozzle (5, 6) is part of a plasma unit and two such plasma units are provided. Both of the plasma nozzles (5, 6) are oriented towards each other and form a pair of nozzles. A glass pane (2) is machined between both of the nozzles (5, 6). A distance sensor (23, 24) is arranged on both of the nozzles (5, 6), and said nozzles (5, 6) are positioned at the correct distance in relation to the surface (37, 38) of the glass pane (2).Type: GrantFiled: November 14, 2005Date of Patent: October 18, 2011Assignee: Vetrotech Saint-Gobain (International) AGInventors: Christian Müller, Norbert Schwankhaus, Friedrich Triebs, Udo Gelderie
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Patent number: 8029851Abstract: Techniques for making nanowires with a desired diameter are provided. The nanowires can be grown from catalytic nanoparticles, wherein the nanowires can have substantially same diameter as the catalytic nanoparticles. Since the size or the diameter of the catalytic nanoparticles can be controlled in production of the nanoparticles, the diameter of the nanowires can be subsequently controlled as well. The catalytic nanoparticles are melted and provided with a gaseous precursor of the nanowires. When supersaturation of the catalytic nanoparticles with the gaseous precursor is reached, the gaseous precursor starts to solidify and form nanowires. The nanowires are separate from each other and not bind with each other to form a plurality of nanowires having the substantially uniform diameter.Type: GrantFiled: August 29, 2008Date of Patent: October 4, 2011Assignee: Korea University Research and Business FoundationInventor: Kwangyeol Lee
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Patent number: 8025776Abstract: Embodiments of the present invention may provide a microchip applicable to an electrophoresis employing UV detection and a method of manufacturing the same. The microchip of the present invention has a glass channel plate, which is formed on an upper surface thereof with a loading channel and a separation channel and is provided on the upper surface thereof with an optical slit layer made of silicon except the channel region, and a glass reservoir plate, which is formed with sample solution reservoirs and buffer solution reservoirs. The loading channel and the separation channel are formed on the channel plate by deep reactive ion etching. The sample solution reservoirs and the buffer solution reservoirs are formed in the reservoir plate by sand blasting. The channel plate and the reservoir plate are combined by anodic bonding the optical slit layer and the reservoir plate. Electrodes for sample and electrodes for buffer are deposited by sputtering Pt with a shadow mask after anodic bonding.Type: GrantFiled: October 29, 2007Date of Patent: September 27, 2011Assignee: Korea Institute of Science and TechnologyInventors: Myung-Suk Chun, Tae Ha Kim
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Patent number: 8021561Abstract: The optical device includes a plurality of waveguides and an optical grating. A first portion of the waveguides act as input waveguide configured to carry a light beam that includes multiple light signals to the optical grating. The optical grating is configured to demultiplex the light signals. A second portion of the waveguides act as output waveguides configured to carry the demultiplexed light signals away from the optical grating. A method of forming the optical device includes sequentially forming the waveguides and the optical grating while a single mask defines the location of the waveguides and the optical grating.Type: GrantFiled: January 16, 2009Date of Patent: September 20, 2011Assignee: Kotura, Inc.Inventors: Wei Qian, Joan Fong, Dazeng Feng
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Patent number: 8012366Abstract: A method is provided for defining a pattern on a workpiece such as a transparent substrate or mask or a workpiece that is at least transparent within a range of optical wavelengths. The method includes defining a photoresist pattern on the top surface of the mask, the pattern including a periodic structure having a periodic spacing between elements of the structure. The method further includes placing the mask on a support pedestal in a plasma reactor chamber and generating a plasma in the chamber to etch the top surface of the mask through openings in the photoresist pattern. The method also includes transmitting light through the pedestal and through the bottom surface of the mask, while viewing through the support pedestal light reflected from the periodic structure and detecting an interference pattern in the reflected light. The method further includes determining from the interference pattern a depth to which periodic structure has been etched in the top surface.Type: GrantFiled: October 30, 2006Date of Patent: September 6, 2011Assignee: Applied Materials, Inc.Inventors: Richard Lewington, Michael N. Grimbergen, Khiem K. Nguyen, Darin Bivens, Madhavi R. Chandrachood, Ajay Kumar
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Patent number: 8008209Abstract: A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.Type: GrantFiled: October 24, 2007Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Michael R. Sievers, Kaushik A. Kumar, Andres F. Munoz, Richard Wise
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Patent number: 7988875Abstract: A method and apparatus is provided for controlling the etch profile of a multilayer layer stack by depositing a first and second material layer with differential etch rates in the same or different processing chamber.Type: GrantFiled: February 7, 2008Date of Patent: August 2, 2011Assignee: Applied Materials, Inc.Inventors: Soo Young Choi, Gaku Furuta
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Patent number: 7975364Abstract: A method for producing a tuning-fork type crystal vibrating piece relates to a crystal tuning fork comprising a basal portion, a first vibrating arm, and a second vibrating arm, wherein both arms extend from the basal portion. The method for producing a crystal tuning fork comprises a step of forming a first metallic film into a shape including the contours of the basal portion, the first vibrating arm and second vibrating arm on a first surface of a quartz wafer; a step of forming a second metallic film on the second surface opposite to the first surface of the quartz wafer into a shape covering at least a root area near the basal portion between the first vibrating arm and the second vibrating arm, and a step of wet-etching the quartz substrate in etching solution after forming the first and second metallic films.Type: GrantFiled: October 5, 2007Date of Patent: July 12, 2011Assignee: Nihon Dempa Kogyo Co., Ltd.Inventor: Takehiro Takahashi